Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14334187	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

60676008

1

T1

3220

T2

6138

T3

1541

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37396761	1			T1	1768		T2	3088		T3	4254
values[0x0]	17377330	1			T1	827		T2	1537		T3	1423
values[0x1]	20236104	1			T1	957		T2	1513		T3	2840

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7142627	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

67867568

1

T1

3388

T2

6138

T3

5003

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	322841	1			T1	14		T2	22		T3	13
valid_sources[0x01]	259598	1			T1	15		T2	24		T3	18
valid_sources[0x02]	373550	1			T1	19		T2	23		T3	28
valid_sources[0x03]	262994	1			T1	13		T2	12		T3	48
valid_sources[0x04]	287151	1			T1	10		T2	29		T3	2
valid_sources[0x05]	275265	1			T1	11		T2	44		T3	66
valid_sources[0x06]	295363	1			T1	16		T2	31		T3	22
valid_sources[0x07]	338542	1			T1	12		T2	16		T3	102
valid_sources[0x08]	337152	1			T1	18		T2	21		T3	35
valid_sources[0x09]	273102	1			T1	11		T2	18		T3	16
valid_sources[0x0a]	261210	1			T1	12		T2	21		T3	18
valid_sources[0x0b]	297913	1			T1	14		T2	33		T3	27
valid_sources[0x0c]	307867	1			T1	10		T2	25		T3	21
valid_sources[0x0d]	281539	1			T1	15		T2	25		T3	54
valid_sources[0x0e]	285549	1			T1	15		T2	24		T3	33
valid_sources[0x0f]	312686	1			T1	21		T2	23		T3	33
valid_sources[0x10]	271180	1			T1	13		T2	21		T3	33
valid_sources[0x11]	282842	1			T1	14		T2	15		T3	19
valid_sources[0x12]	261634	1			T1	18		T2	16		T3	65
valid_sources[0x13]	291428	1			T1	18		T2	31		T3	42
valid_sources[0x14]	281057	1			T1	14		T2	20		T3	28
valid_sources[0x15]	331317	1			T1	9		T2	25		T3	61
valid_sources[0x16]	299168	1			T1	8		T2	20		T3	9
valid_sources[0x17]	287038	1			T1	7		T2	33		T3	73
valid_sources[0x18]	300101	1			T1	8		T2	13		T3	32
valid_sources[0x19]	267087	1			T1	15		T2	15		T3	36
valid_sources[0x1a]	338495	1			T1	11		T2	20		T3	52
valid_sources[0x1b]	309368	1			T1	10		T2	16		T3	28
valid_sources[0x1c]	349885	1			T1	13		T2	22		T3	50
valid_sources[0x1d]	309085	1			T1	17		T2	22		T3	11
valid_sources[0x1e]	305421	1			T1	11		T2	34		T3	30
valid_sources[0x1f]	321964	1			T1	20		T2	34		T3	17
valid_sources[0x20]	280345	1			T1	21		T2	34		T3	26
valid_sources[0x21]	276471	1			T1	18		T2	18		T3	8
valid_sources[0x22]	351232	1			T1	15		T2	35		T3	33
valid_sources[0x23]	363116	1			T1	14		T2	26		T3	56
valid_sources[0x24]	262462	1			T1	17		T2	25		T3	7
valid_sources[0x25]	276809	1			T1	9		T2	26		T3	35
valid_sources[0x26]	302111	1			T1	6		T2	28		T3	56
valid_sources[0x27]	267593	1			T1	12		T2	30		T3	12
valid_sources[0x28]	260946	1			T1	20		T2	15		T3	48
valid_sources[0x29]	331753	1			T1	11		T2	18		T3	31
valid_sources[0x2a]	305848	1			T1	14		T2	31		T3	10
valid_sources[0x2b]	308052	1			T1	10		T2	26		T3	31
valid_sources[0x2c]	278113	1			T1	11		T2	26		T3	43
valid_sources[0x2d]	265983	1			T1	18		T2	32		T3	45
valid_sources[0x2e]	262866	1			T1	9		T2	17		T3	18
valid_sources[0x2f]	307581	1			T1	12		T2	25		T3	33
valid_sources[0x30]	272179	1			T1	10		T2	17		T3	17
valid_sources[0x31]	295079	1			T1	11		T2	28		T3	42
valid_sources[0x32]	336197	1			T1	18		T2	23		T3	63
valid_sources[0x33]	275987	1			T1	16		T2	18		T3	71
valid_sources[0x34]	314966	1			T1	9		T2	15		T3	40
valid_sources[0x35]	305169	1			T1	13		T2	16		T3	37
valid_sources[0x36]	295210	1			T1	16		T2	23		T3	32
valid_sources[0x37]	296517	1			T1	5		T2	25		T3	54
valid_sources[0x38]	260121	1			T1	18		T2	17		T3	65
valid_sources[0x39]	270066	1			T1	12		T2	16		T3	72
valid_sources[0x3a]	314796	1			T1	17		T2	23		T3	41
valid_sources[0x3b]	271942	1			T1	19		T2	24		T3	22
valid_sources[0x3c]	282809	1			T1	12		T2	19		T3	71
valid_sources[0x3d]	324264	1			T1	13		T2	17		T3	18
valid_sources[0x3e]	283435	1			T1	7		T2	25		T3	29
valid_sources[0x3f]	264747	1			T1	16		T2	24		T3	33
valid_sources[0x40]	297962	1			T1	19		T2	22		T3	59
valid_sources[0x41]	307371	1			T1	16		T2	12		T3	11
valid_sources[0x42]	267227	1			T1	13		T2	31		T3	39
valid_sources[0x43]	291438	1			T1	18		T2	17		T3	17
valid_sources[0x44]	269777	1			T1	12		T2	26		T3	41
valid_sources[0x45]	272244	1			T1	12		T2	15		T3	29
valid_sources[0x46]	277227	1			T1	13		T2	30		T3	23
valid_sources[0x47]	262406	1			T1	14		T2	24		T3	4
valid_sources[0x48]	297700	1			T1	14		T2	26		T3	47
valid_sources[0x49]	289466	1			T1	13		T2	26		T3	61
valid_sources[0x4a]	350974	1			T1	15		T2	24		T3	54
valid_sources[0x4b]	326981	1			T1	17		T2	31		T3	33
valid_sources[0x4c]	277651	1			T1	12		T2	29		T3	78
valid_sources[0x4d]	341801	1			T1	14		T2	21		T3	29
valid_sources[0x4e]	303444	1			T1	14		T2	25		T3	74
valid_sources[0x4f]	272673	1			T1	11		T2	16		T3	22
valid_sources[0x50]	333537	1			T1	24		T2	17		T3	9
valid_sources[0x51]	277609	1			T1	18		T2	19		T3	29
valid_sources[0x52]	306259	1			T1	15		T2	35		T3	32
valid_sources[0x53]	262946	1			T1	14		T2	22		T3	105
valid_sources[0x54]	264603	1			T1	16		T2	29		T3	21
valid_sources[0x55]	270408	1			T1	9		T2	32		T3	59
valid_sources[0x56]	317476	1			T1	15		T2	17		T3	13
valid_sources[0x57]	306882	1			T1	10		T2	23		T3	8
valid_sources[0x58]	307301	1			T1	11		T2	17		T3	23
valid_sources[0x59]	272958	1			T1	11		T2	13		T3	14
valid_sources[0x5a]	338530	1			T1	11		T2	32		T3	10
valid_sources[0x5b]	274642	1			T1	20		T2	24		T3	42
valid_sources[0x5c]	317395	1			T1	18		T2	20		T3	6
valid_sources[0x5d]	286466	1			T1	12		T2	24		T3	15
valid_sources[0x5e]	282589	1			T1	17		T2	31		T3	12
valid_sources[0x5f]	361168	1			T1	17		T2	28		T3	1
valid_sources[0x60]	314822	1			T1	9		T2	26		T3	29
valid_sources[0x61]	291308	1			T1	6		T2	43		T3	31
valid_sources[0x62]	297775	1			T1	14		T2	27		T3	31
valid_sources[0x63]	309851	1			T1	4		T2	23		T3	37
valid_sources[0x64]	321384	1			T1	14		T2	22		T3	25
valid_sources[0x65]	264871	1			T1	15		T2	33		T3	8
valid_sources[0x66]	265889	1			T1	17		T2	34		T3	14
valid_sources[0x67]	255920	1			T1	15		T2	30		T3	14
valid_sources[0x68]	325592	1			T1	11		T2	20		T3	31
valid_sources[0x69]	290828	1			T1	14		T2	36		T3	18
valid_sources[0x6a]	295907	1			T1	16		T2	34		T3	59
valid_sources[0x6b]	282423	1			T1	9		T2	32		T3	25
valid_sources[0x6c]	264023	1			T1	14		T2	18		T3	50
valid_sources[0x6d]	349862	1			T1	14		T2	16		T3	55
valid_sources[0x6e]	293927	1			T1	13		T2	20		T3	59
valid_sources[0x6f]	344669	1			T1	6		T2	19		T3	15
valid_sources[0x70]	285588	1			T1	11		T2	25		T3	23
valid_sources[0x71]	302357	1			T1	11		T2	33		T3	30
valid_sources[0x72]	282691	1			T1	12		T2	26		T3	45
valid_sources[0x73]	278911	1			T1	10		T2	28		T3	10
valid_sources[0x74]	336283	1			T1	16		T2	25		T3	27
valid_sources[0x75]	308730	1			T1	10		T2	19		T3	23
valid_sources[0x76]	305215	1			T1	13		T2	38		T3	42
valid_sources[0x77]	275570	1			T1	20		T2	11		T3	55
valid_sources[0x78]	263817	1			T1	15		T2	20		T3	13
valid_sources[0x79]	317669	1			T1	16		T2	16		T3	19
valid_sources[0x7a]	272794	1			T1	10		T2	38		T3	32
valid_sources[0x7b]	274634	1			T1	12		T2	15		T3	22
valid_sources[0x7c]	295610	1			T1	15		T2	35		T3	13
valid_sources[0x7d]	271514	1			T1	10		T2	16		T3	25
valid_sources[0x7e]	370259	1			T1	17		T2	21		T3	23
valid_sources[0x7f]	308284	1			T1	18		T2	16		T3	22
valid_sources[0x80]	306209	1			T1	14		T2	15		T3	21

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30233873

1

T1

1607

T2

3088

T3

803

values[0x0]

all_enables

biggest_size

15224395

1

T1

781

T2

1537

T3

382

values[0x1]

all_enables

biggest_size

15217740

1

T1

832

T2

1513

T3

356

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36812	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

136997

1

T1

18

T2

2

T4

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	50122	1			T1	32		T5	588		T8	23
values[0x0]	59445	1			T1	17		T4	1		T5	683
values[0x1]	64242	1			T1	17		T2	2		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27863	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

145946

1

T1

22

T2

2

T4

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	514	1			T5	4		T25	15		T63	1
valid_sources[0x01]	577	1			T1	1		T5	10		T25	13
valid_sources[0x02]	542	1			T5	12		T25	8		T63	1
valid_sources[0x03]	582	1			T5	11		T25	13		T26	17
valid_sources[0x04]	584	1			T5	7		T25	9		T26	8
valid_sources[0x05]	631	1			T5	7		T25	17		T26	8
valid_sources[0x06]	564	1			T5	1		T25	16		T26	8
valid_sources[0x07]	839	1			T5	7		T25	14		T26	11
valid_sources[0x08]	751	1			T5	10		T25	5		T26	7
valid_sources[0x09]	567	1			T5	7		T25	12		T26	5
valid_sources[0x0a]	788	1			T5	6		T25	11		T26	6
valid_sources[0x0b]	889	1			T1	1		T5	7		T25	16
valid_sources[0x0c]	910	1			T5	14		T25	10		T26	15
valid_sources[0x0d]	714	1			T5	7		T25	16		T26	8
valid_sources[0x0e]	605	1			T5	8		T25	18		T26	11
valid_sources[0x0f]	868	1			T5	5		T25	16		T9	40
valid_sources[0x10]	688	1			T5	11		T25	10		T26	10
valid_sources[0x11]	651	1			T5	9		T25	13		T26	8
valid_sources[0x12]	1078	1			T5	4		T27	2		T25	14
valid_sources[0x13]	888	1			T1	1		T5	4		T25	10
valid_sources[0x14]	542	1			T5	8		T25	10		T62	1
valid_sources[0x15]	579	1			T5	11		T25	12		T26	9
valid_sources[0x16]	664	1			T5	9		T25	16		T26	16
valid_sources[0x17]	694	1			T5	6		T25	16		T26	11
valid_sources[0x18]	1258	1			T5	7		T25	13		T26	11
valid_sources[0x19]	747	1			T1	1		T5	4		T25	15
valid_sources[0x1a]	952	1			T5	8		T25	13		T26	13
valid_sources[0x1b]	607	1			T5	10		T25	14		T26	16
valid_sources[0x1c]	726	1			T1	1		T5	7		T25	13
valid_sources[0x1d]	750	1			T5	10		T25	4		T26	7
valid_sources[0x1e]	569	1			T5	13		T25	23		T26	10
valid_sources[0x1f]	883	1			T1	1		T5	10		T23	1
valid_sources[0x20]	589	1			T1	1		T5	4		T23	1
valid_sources[0x21]	646	1			T1	1		T5	10		T25	12
valid_sources[0x22]	498	1			T5	13		T25	10		T28	1
valid_sources[0x23]	495	1			T5	12		T25	10		T26	10
valid_sources[0x24]	703	1			T5	13		T25	12		T63	1
valid_sources[0x25]	707	1			T5	7		T25	12		T26	5
valid_sources[0x26]	797	1			T5	9		T27	2		T25	9
valid_sources[0x27]	758	1			T1	1		T5	9		T25	12
valid_sources[0x28]	773	1			T5	17		T8	1		T25	13
valid_sources[0x29]	775	1			T5	6		T25	10		T26	12
valid_sources[0x2a]	517	1			T1	3		T5	3		T10	2
valid_sources[0x2b]	666	1			T1	1		T5	8		T27	1
valid_sources[0x2c]	573	1			T5	6		T25	11		T26	12
valid_sources[0x2d]	691	1			T1	1		T5	4		T55	2
valid_sources[0x2e]	705	1			T1	1		T5	3		T10	4
valid_sources[0x2f]	856	1			T1	1		T5	10		T25	8
valid_sources[0x30]	703	1			T1	1		T5	9		T25	13
valid_sources[0x31]	731	1			T5	5		T8	1		T25	10
valid_sources[0x32]	626	1			T5	7		T25	12		T26	10
valid_sources[0x33]	595	1			T5	8		T25	14		T26	14
valid_sources[0x34]	859	1			T1	1		T5	6		T25	7
valid_sources[0x35]	651	1			T5	7		T25	9		T26	17
valid_sources[0x36]	535	1			T5	2		T25	6		T26	13
valid_sources[0x37]	679	1			T1	1		T5	9		T25	12
valid_sources[0x38]	769	1			T1	1		T5	10		T25	7
valid_sources[0x39]	661	1			T5	8		T25	9		T26	8
valid_sources[0x3a]	644	1			T5	5		T25	14		T26	12
valid_sources[0x3b]	905	1			T5	4		T25	11		T26	18
valid_sources[0x3c]	590	1			T5	12		T25	15		T26	8
valid_sources[0x3d]	523	1			T5	8		T25	15		T26	13
valid_sources[0x3e]	638	1			T5	15		T25	10		T26	10
valid_sources[0x3f]	604	1			T1	1		T5	16		T25	18
valid_sources[0x40]	622	1			T1	1		T5	5		T25	13
valid_sources[0x41]	598	1			T5	6		T25	15		T26	10
valid_sources[0x42]	738	1			T5	4		T11	1		T25	7
valid_sources[0x43]	561	1			T5	8		T25	14		T26	5
valid_sources[0x44]	577	1			T5	15		T27	3		T25	15
valid_sources[0x45]	628	1			T5	7		T25	9		T26	12
valid_sources[0x46]	616	1			T1	1		T5	7		T25	7
valid_sources[0x47]	636	1			T5	7		T25	13		T26	8
valid_sources[0x48]	678	1			T5	8		T10	3		T25	15
valid_sources[0x49]	724	1			T5	9		T25	14		T26	8
valid_sources[0x4a]	652	1			T5	7		T25	5		T26	2
valid_sources[0x4b]	821	1			T1	1		T5	4		T25	14
valid_sources[0x4c]	610	1			T5	4		T25	11		T26	10
valid_sources[0x4d]	554	1			T1	1		T5	12		T25	5
valid_sources[0x4e]	569	1			T5	15		T11	1		T25	12
valid_sources[0x4f]	566	1			T1	1		T5	6		T25	14
valid_sources[0x50]	1065	1			T5	16		T25	20		T26	11
valid_sources[0x51]	780	1			T5	1		T25	16		T26	12
valid_sources[0x52]	603	1			T5	5		T25	6		T26	12
valid_sources[0x53]	639	1			T1	1		T5	4		T8	13
valid_sources[0x54]	659	1			T5	8		T11	1		T25	16
valid_sources[0x55]	581	1			T1	1		T5	10		T27	3
valid_sources[0x56]	768	1			T1	1		T5	8		T25	9
valid_sources[0x57]	848	1			T5	8		T10	2		T25	11
valid_sources[0x58]	600	1			T5	3		T25	16		T26	12
valid_sources[0x59]	591	1			T1	1		T5	9		T13	8
valid_sources[0x5a]	799	1			T1	1		T5	3		T25	7
valid_sources[0x5b]	842	1			T5	10		T25	11		T26	6
valid_sources[0x5c]	582	1			T5	7		T25	15		T26	6
valid_sources[0x5d]	568	1			T5	9		T25	10		T26	19
valid_sources[0x5e]	1013	1			T5	6		T10	2		T25	13
valid_sources[0x5f]	492	1			T5	6		T27	2		T25	10
valid_sources[0x60]	561	1			T1	1		T5	14		T25	12
valid_sources[0x61]	789	1			T5	12		T25	8		T26	10
valid_sources[0x62]	568	1			T5	9		T25	12		T26	11
valid_sources[0x63]	473	1			T5	3		T25	16		T26	7
valid_sources[0x64]	715	1			T1	1		T5	7		T46	1
valid_sources[0x65]	766	1			T5	6		T27	1		T25	12
valid_sources[0x66]	719	1			T1	1		T5	4		T25	13
valid_sources[0x67]	883	1			T5	15		T25	6		T26	7
valid_sources[0x68]	854	1			T5	11		T25	17		T26	11
valid_sources[0x69]	605	1			T5	11		T25	9		T26	5
valid_sources[0x6a]	834	1			T5	5		T25	15		T26	12
valid_sources[0x6b]	839	1			T5	4		T27	1		T25	12
valid_sources[0x6c]	554	1			T1	1		T5	11		T42	1
valid_sources[0x6d]	733	1			T5	8		T7	4		T25	11
valid_sources[0x6e]	611	1			T5	14		T12	1		T25	11
valid_sources[0x6f]	674	1			T5	8		T25	14		T26	16
valid_sources[0x70]	674	1			T5	8		T25	11		T26	6
valid_sources[0x71]	906	1			T5	6		T25	18		T26	8
valid_sources[0x72]	591	1			T5	9		T24	1		T25	15
valid_sources[0x73]	671	1			T5	8		T25	12		T26	10
valid_sources[0x74]	1054	1			T5	1		T8	6		T25	17
valid_sources[0x75]	640	1			T5	8		T25	15		T26	10
valid_sources[0x76]	604	1			T5	9		T25	18		T26	9
valid_sources[0x77]	666	1			T1	1		T5	14		T41	2
valid_sources[0x78]	535	1			T5	6		T25	10		T63	1
valid_sources[0x79]	872	1			T5	6		T25	12		T26	8
valid_sources[0x7a]	1014	1			T5	11		T8	6		T25	10
valid_sources[0x7b]	1063	1			T5	14		T25	10		T63	1
valid_sources[0x7c]	589	1			T5	9		T25	13		T26	7
valid_sources[0x7d]	662	1			T5	9		T10	4		T25	6
valid_sources[0x7e]	599	1			T5	22		T25	16		T26	10
valid_sources[0x7f]	598	1			T5	10		T25	14		T26	1
valid_sources[0x80]	796	1			T5	8		T25	11		T26	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

37350

1

T1

9

T5

521

T8

11

values[0x0]

all_enables

biggest_size

50731

1

T1

8

T4

1

T5

672

values[0x1]

all_enables

biggest_size

48916

1

T1

1

T2

2

T5

676