Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14003924

1

T1

110

T3

6976

T4

10013

full_word

55474282

1

T1

982

T2

6138

T3

1541

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	69477866	1			T1	1092		T2	6138		T3	8517
auto[TlIntgErrCmd]	114	1			T66	6		T67	6		T68	8
auto[TlIntgErrData]	123	1			T66	1		T67	7		T68	6
auto[TlIntgErrBoth]	103	1			T66	3		T67	7		T68	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31792870

1

T1

527

T2

3088

T3

4254

auto[1]

37685336

1

T1

565

T2

3050

T3

4263

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6688722	1			T1	50		T3	3451		T4	5044
auto[TlIntgErrNone]	partial	auto[1]	7314886	1			T1	60		T3	3525		T4	4969
auto[TlIntgErrNone]	full_word	auto[0]	25103990	1			T1	477		T2	3088		T3	803
auto[TlIntgErrNone]	full_word	auto[1]	30370268	1			T1	505		T2	3050		T3	738
auto[TlIntgErrCmd]	partial	auto[0]	50	1			T66	3		T67	2		T68	3
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T66	3		T67	4		T68	5
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T132	2		T133	1		-	-
auto[TlIntgErrData]	partial	auto[0]	54	1			T67	2		T68	3		T134	3
auto[TlIntgErrData]	partial	auto[1]	57	1			T66	1		T67	5		T68	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T134	1		T135	1		T136	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T68	1		T135	1		T137	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T66	1		T67	2		T68	4
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T66	2		T67	5		T68	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T137	1		T138	1		T139	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T137	1		T138	1		T132	1