Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	753468	1			T5	7		T7	4537		T10	971
auto[1]	10280181	1			T1	454		T2	3088		T3	22
auto[2]	631988	1			T5	5		T7	4026		T10	609
auto[3]	10158028	1			T1	500		T2	3049		T3	18

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14184805	1			T1	790		T2	6137		T4	76411
auto[1]	2072910	1			T1	73		T3	8		T4	7521
auto[2]	2097568	1			T1	86		T3	1		T4	7656
auto[3]	3468382	1			T1	5		T3	31		T4	774

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8208058

1

T1

952

T2

6131

T3

40

auto[1]

13615607

1

T1

2

T2

6

T4

92362

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	299823	1			T5	6		T7	3745		T10	802
auto[0]	auto[0]	auto[1]	30727	1			T5	1		T7	365		T10	79
auto[0]	auto[0]	auto[2]	30476	1			T7	389		T10	83		T27	2
auto[0]	auto[0]	auto[3]	7198	1			T7	35		T10	7		T27	1
auto[0]	auto[1]	auto[0]	3089391	1			T1	385		T2	3085		T5	3
auto[0]	auto[1]	auto[1]	324104	1			T1	24		T3	7		T7	388
auto[0]	auto[1]	auto[2]	311682	1			T1	43		T7	74		T10	52
auto[0]	auto[1]	auto[3]	60639	1			T1	2		T3	15		T7	46
auto[0]	auto[2]	auto[0]	257401	1			T5	4		T7	3386		T10	470
auto[0]	auto[2]	auto[1]	26430	1			T7	361		T10	42		T8	80
auto[0]	auto[2]	auto[2]	29146	1			T5	1		T7	246		T10	89
auto[0]	auto[2]	auto[3]	6136	1			T7	28		T10	8		T27	5
auto[0]	auto[3]	auto[0]	3043439	1			T1	404		T2	3046		T5	2
auto[0]	auto[3]	auto[1]	306288	1			T1	48		T3	1		T7	33
auto[0]	auto[3]	auto[2]	323113	1			T1	43		T3	1		T5	1
auto[0]	auto[3]	auto[3]	62065	1			T1	3		T3	16		T7	28
auto[1]	auto[0]	auto[0]	13193	1			T7	3		T54	115		T63	1
auto[1]	auto[0]	auto[1]	57148	1			T54	463		T97	438		T149	844
auto[1]	auto[0]	auto[2]	57007	1			T54	459		T97	380		T150	1
auto[1]	auto[0]	auto[3]	257896	1			T54	2052		T97	1812		T151	2
auto[1]	auto[1]	auto[0]	3737625	1			T2	3		T4	38267		T7	2
auto[1]	auto[1]	auto[1]	662552	1			T4	3780		T42	2		T23	5988
auto[1]	auto[1]	auto[2]	644607	1			T4	3861		T42	1		T23	6072
auto[1]	auto[1]	auto[3]	1449581	1			T4	382		T23	649		T54	6131
auto[1]	auto[2]	auto[0]	9001	1			T7	4		T8	3		T92	1
auto[1]	auto[2]	auto[1]	39623	1			T7	1		T20	1		T69	1
auto[1]	auto[2]	auto[2]	48391	1			T54	371		T92	1		T97	351
auto[1]	auto[2]	auto[3]	215860	1			T54	1897		T97	1643		T149	3312
auto[1]	auto[3]	auto[0]	3734932	1			T1	1		T2	3		T4	38144
auto[1]	auto[3]	auto[1]	626038	1			T1	1		T4	3741		T23	5975
auto[1]	auto[3]	auto[2]	653146	1			T4	3795		T10	1		T42	2
auto[1]	auto[3]	auto[3]	1409007	1			T4	392		T23	566		T54	6016