Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	341478629	204061	0	0
ctrl_regwen_rd_A	341478629	4209	0	0
exec_rd_A	341478629	4089	0	0
exec_regwen_rd_A	341478629	4095	0	0
readback_rd_A	341478629	1669	0	0
readback_regwen_rd_A	341478629	1661	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341478629	204061	0	0
T5	41519	2691	0	0
T6	66604	0	0	0
T7	508162	0	0	0
T10	161751	0	0	0
T11	35530	0	0	0
T12	1879	0	0	0
T13	1056	0	0	0
T19	0	5376	0	0
T23	206015	0	0	0
T25	0	5343	0	0
T26	0	4225	0	0
T41	76278	0	0	0
T42	14813	0	0	0
T59	0	2421	0	0
T74	0	3330	0	0
T75	0	3727	0	0
T76	0	4775	0	0
T77	0	5884	0	0
T78	0	4858	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341478629	4209	0	0
T5	41519	193	0	0
T6	66604	0	0	0
T7	508162	0	0	0
T10	161751	0	0	0
T11	35530	0	0	0
T12	1879	0	0	0
T13	1056	0	0	0
T23	206015	0	0	0
T41	76278	0	0	0
T42	14813	0	0	0
T66	0	31	0	0
T76	0	183	0	0
T124	0	330	0	0
T125	0	106	0	0
T126	0	151	0	0
T127	0	135	0	0
T128	0	185	0	0
T129	0	259	0	0
T130	0	197	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341478629	4089	0	0
T5	41519	204	0	0
T6	66604	0	0	0
T7	508162	0	0	0
T10	161751	0	0	0
T11	35530	0	0	0
T12	1879	0	0	0
T13	1056	0	0	0
T23	206015	0	0	0
T41	76278	0	0	0
T42	14813	0	0	0
T66	0	32	0	0
T76	0	151	0	0
T124	0	286	0	0
T125	0	163	0	0
T126	0	140	0	0
T127	0	129	0	0
T128	0	111	0	0
T129	0	361	0	0
T130	0	182	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341478629	4095	0	0
T5	41519	149	0	0
T6	66604	0	0	0
T7	508162	0	0	0
T10	161751	0	0	0
T11	35530	0	0	0
T12	1879	0	0	0
T13	1056	0	0	0
T23	206015	0	0	0
T41	76278	0	0	0
T42	14813	0	0	0
T66	0	27	0	0
T76	0	125	0	0
T124	0	288	0	0
T125	0	146	0	0
T126	0	161	0	0
T127	0	116	0	0
T128	0	165	0	0
T129	0	315	0	0
T130	0	233	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341478629	1669	0	0
T5	41519	120	0	0
T6	66604	0	0	0
T7	508162	0	0	0
T10	161751	0	0	0
T11	35530	0	0	0
T12	1879	0	0	0
T13	1056	0	0	0
T23	206015	0	0	0
T41	76278	0	0	0
T42	14813	0	0	0
T76	0	172	0	0
T124	0	194	0	0
T125	0	128	0	0
T126	0	132	0	0
T127	0	132	0	0
T128	0	121	0	0
T129	0	300	0	0
T130	0	209	0	0
T131	0	20	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341478629	1661	0	0
T5	41519	155	0	0
T6	66604	0	0	0
T7	508162	0	0	0
T10	161751	0	0	0
T11	35530	0	0	0
T12	1879	0	0	0
T13	1056	0	0	0
T23	206015	0	0	0
T41	76278	0	0	0
T42	14813	0	0	0
T76	0	128	0	0
T124	0	226	0	0
T125	0	119	0	0
T126	0	147	0	0
T127	0	154	0	0
T128	0	152	0	0
T129	0	188	0	0
T130	0	167	0	0
T131	0	33	0	0