Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	148457272	1			T1	417064		T3	386786		T4	103003
instr_valid_dis	117270517	1			T1	417064		T3	98084		T4	774526
instr_en	21774935	1			T3	270928		T4	230524		T17	16862

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10038799	1			T3	48858		T4	38738		T17	33898
sram_ifetch_valid_disable	115678339	1			T1	417064		T3	189244		T4	812076
sram_ifetch_enable	22740134	1			T3	148684		T4	179224		T17	201042

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	148457272	1			T1	417064		T3	386786		T4	103003
hw_debug_en_valid_off	115544552	1			T1	417064		T3	132004		T4	643968
hw_debug_en_on	21574362	1			T3	243940		T4	303526		T17	25028

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	115678339	1			T1	417064		T3	189244		T4	812076
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	102807857	1			T1	417064		T3	26164		T4	712332
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9462014	1			T3	163080		T4	99744		T42	72644
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3403663	1			T3	14692		T4	4984		T17	17904
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1259282	1			T3	14692		T4	4984		T17	17904
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1287081	1			T42	26296		T24	11223		T20	16332
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4492874	1			T3	32708		T4	3674		T17	15994
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2174456	1			T17	15994		T42	37402		T145	207538
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1636290	1			T3	32708		T4	3674		T42	13796
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	7799092	1			T3	96612		T4	196840		T23	5052
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	2924898	1			T3	26164		T4	162578		T32	140
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3339326	1			T3	70448		T4	34262		T32	108408

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8631622	1			T3	75140		T4	127106		T17	16862
lc_exec_en	9282396	1			T3	114620		T4	103012		T17	9034
valid_exec_dis	113421515	1			T1	417064		T3	140476		T4	604346
invalid_exec_dis	32778933	1			T3	197542		T4	217962		T17	234940