Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44


Total tests in report: 1021
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
74.17 74.17 92.80 92.80 76.78 76.78 85.92 85.92 33.33 33.33 85.27 85.27 93.51 93.51 51.55 51.55 /workspace/coverage/default/18.sram_ctrl_stress_all.3189244035
89.64 15.47 97.20 4.41 87.68 10.90 97.09 11.17 71.43 38.10 91.79 6.52 95.43 1.92 86.84 35.28 /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3362973953
94.23 4.60 98.64 1.44 87.68 0.00 97.09 0.00 100.00 28.57 93.96 2.17 95.43 0.00 86.84 0.00 /workspace/coverage/default/40.sram_ctrl_mem_partial_access.1478159702
95.24 1.01 98.81 0.17 88.51 0.83 97.30 0.21 100.00 0.00 94.69 0.72 95.43 0.00 91.96 5.12 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.676667488
95.95 0.71 98.98 0.17 90.28 1.78 98.06 0.76 100.00 0.00 95.41 0.72 96.02 0.59 92.87 0.91 /workspace/coverage/default/1.sram_ctrl_sec_cm.67075591
96.28 0.33 98.98 0.00 90.28 0.00 98.58 0.52 100.00 0.00 95.41 0.00 96.17 0.15 94.52 1.65 /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3443302344
96.49 0.22 99.07 0.08 90.40 0.12 98.58 0.00 100.00 0.00 95.65 0.24 97.05 0.88 94.70 0.18 /workspace/coverage/default/27.sram_ctrl_mem_partial_access.2420537466
96.69 0.20 99.07 0.00 90.40 0.00 98.65 0.07 100.00 0.00 95.65 0.00 98.38 1.33 94.70 0.00 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.942873494
96.84 0.15 99.07 0.00 90.52 0.12 98.65 0.00 100.00 0.00 95.65 0.00 98.38 0.00 95.61 0.91 /workspace/coverage/default/27.sram_ctrl_stress_all.1005742933
96.97 0.13 99.15 0.08 90.52 0.00 99.48 0.83 100.00 0.00 95.65 0.00 98.38 0.00 95.61 0.00 /workspace/coverage/default/15.sram_ctrl_ram_cfg.3087558040
97.10 0.13 99.15 0.00 90.52 0.00 99.48 0.00 100.00 0.00 95.65 0.00 98.38 0.00 96.53 0.91 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.709036571
97.21 0.11 99.15 0.00 90.52 0.00 99.48 0.00 100.00 0.00 95.65 0.00 99.12 0.74 96.53 0.00 /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.273529894
97.30 0.09 99.15 0.00 90.52 0.00 99.58 0.10 100.00 0.00 95.65 0.00 99.12 0.00 97.07 0.55 /workspace/coverage/default/39.sram_ctrl_executable.456053671
97.39 0.09 99.15 0.00 90.64 0.12 99.58 0.00 100.00 0.00 96.14 0.48 99.12 0.00 97.07 0.00 /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.529775196
97.46 0.07 99.15 0.00 91.00 0.36 99.72 0.14 100.00 0.00 96.14 0.00 99.12 0.00 97.07 0.00 /workspace/coverage/default/1.sram_ctrl_alert_test.2100118366
97.48 0.03 99.15 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.14 0.00 99.12 0.00 97.26 0.18 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1374992885
97.51 0.03 99.15 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.14 0.00 99.12 0.00 97.44 0.18 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.956920199

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1324180984
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3396034828
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1731126448
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2703563269
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.4144791621
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1299906337
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3875177591
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1274780178
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.466285061
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1839518848
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3415006951
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1252631006
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1734429226
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.373449387
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1619588798
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3337487827
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.4285137331
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.331510422
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.557240549
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3716763192
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2723034318
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1659619577
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3439935258
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1225661931
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3396792313
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2312030921
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3265981845
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2685460261
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1225340897
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3498935475
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1542223546
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3177994114
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.531463595
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2635880234
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.733072929
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4055567093
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2658831238
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2172820589
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.812378025
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3206085288
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2188729453
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.472835438
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2083740893
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2735898992
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2507303378
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2116420249
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.344984067
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1432304239
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2717613776
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.476208335
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.883099705
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3106892873
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3822166725
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1454896196
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1125629524
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.558897095
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3470703704
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.202547152
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3471199949
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.4258530015
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3206299496
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.934981711
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2261251640
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3988276310
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1549590786
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3835920898
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2551874399
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1046475271
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.907104379
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.646847990
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.178420921
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3289969989
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3848412141
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3381431898
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2140283910
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2904941295
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1958218348
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.4180393270
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1592452176
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3285229642
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1230698029
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1977385403
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.506715228
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3471317145
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2884108890
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1059680343
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.80493057
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3422609036
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.778155762
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1795752754
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.771818430
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3166448304
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3665106719
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3138283411
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1805029357
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.910648914
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2428001136
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.488212658
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3557075062
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3849547616
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2342577016
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.377032073
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3431890463
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3983495654
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2994893509
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.197532114
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2723609138
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.294802743
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3734208420
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.824659572
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1262153675
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.4005294649
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2301469185
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3283594737
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.544141297
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3158354918
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2251120501
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3113626001
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2465050132
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1098768131
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.184575455
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1997006505
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3986800049
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.4071472732
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.282033805
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.823614664
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2734948253
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3999494599
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.243144750
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3113821972
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.3906239125
/workspace/coverage/default/0.sram_ctrl_alert_test.3685352190
/workspace/coverage/default/0.sram_ctrl_bijection.2891506617
/workspace/coverage/default/0.sram_ctrl_executable.119291472
/workspace/coverage/default/0.sram_ctrl_lc_escalation.3340373109
/workspace/coverage/default/0.sram_ctrl_max_throughput.2297318281
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1311076601
/workspace/coverage/default/0.sram_ctrl_mem_walk.1848998087
/workspace/coverage/default/0.sram_ctrl_multiple_keys.3622748455
/workspace/coverage/default/0.sram_ctrl_partial_access.462711904
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.3656993452
/workspace/coverage/default/0.sram_ctrl_ram_cfg.2026293332
/workspace/coverage/default/0.sram_ctrl_regwen.2053388511
/workspace/coverage/default/0.sram_ctrl_sec_cm.4246412769
/workspace/coverage/default/0.sram_ctrl_smoke.575919308
/workspace/coverage/default/0.sram_ctrl_stress_all.3990757805
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.2353612526
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2240548187
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.568939272
/workspace/coverage/default/1.sram_ctrl_bijection.1739161623
/workspace/coverage/default/1.sram_ctrl_executable.2614444107
/workspace/coverage/default/1.sram_ctrl_lc_escalation.2855233118
/workspace/coverage/default/1.sram_ctrl_max_throughput.3532898615
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.1461705216
/workspace/coverage/default/1.sram_ctrl_mem_walk.950127420
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2379360787
/workspace/coverage/default/1.sram_ctrl_partial_access.2051690820
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3524767801
/workspace/coverage/default/1.sram_ctrl_ram_cfg.4268893573
/workspace/coverage/default/1.sram_ctrl_regwen.4217641457
/workspace/coverage/default/1.sram_ctrl_smoke.3635966896
/workspace/coverage/default/1.sram_ctrl_stress_all.1251317594
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2844349900
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.2341601559
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1511378257
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.479285522
/workspace/coverage/default/10.sram_ctrl_alert_test.5654077
/workspace/coverage/default/10.sram_ctrl_bijection.2139358663
/workspace/coverage/default/10.sram_ctrl_executable.4063787396
/workspace/coverage/default/10.sram_ctrl_lc_escalation.2611979146
/workspace/coverage/default/10.sram_ctrl_max_throughput.1329839308
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.2030299532
/workspace/coverage/default/10.sram_ctrl_mem_walk.1403008163
/workspace/coverage/default/10.sram_ctrl_multiple_keys.3921040008
/workspace/coverage/default/10.sram_ctrl_partial_access.1275074358
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2567418785
/workspace/coverage/default/10.sram_ctrl_ram_cfg.3704931397
/workspace/coverage/default/10.sram_ctrl_regwen.554968112
/workspace/coverage/default/10.sram_ctrl_smoke.204949034
/workspace/coverage/default/10.sram_ctrl_stress_all.3436357623
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2504549210
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.1100434434
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.627926039
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.890337501
/workspace/coverage/default/11.sram_ctrl_alert_test.666683463
/workspace/coverage/default/11.sram_ctrl_bijection.4255685837
/workspace/coverage/default/11.sram_ctrl_executable.381914525
/workspace/coverage/default/11.sram_ctrl_lc_escalation.4026291519
/workspace/coverage/default/11.sram_ctrl_max_throughput.423519
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.24062917
/workspace/coverage/default/11.sram_ctrl_mem_walk.1628042529
/workspace/coverage/default/11.sram_ctrl_multiple_keys.2535311641
/workspace/coverage/default/11.sram_ctrl_partial_access.1991966112
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2734889169
/workspace/coverage/default/11.sram_ctrl_ram_cfg.684243984
/workspace/coverage/default/11.sram_ctrl_regwen.86590931
/workspace/coverage/default/11.sram_ctrl_smoke.1165345627
/workspace/coverage/default/11.sram_ctrl_stress_all.699854473
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.2971158938
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3991538410
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.3795203029
/workspace/coverage/default/12.sram_ctrl_alert_test.83950511
/workspace/coverage/default/12.sram_ctrl_bijection.1271419912
/workspace/coverage/default/12.sram_ctrl_executable.2130363946
/workspace/coverage/default/12.sram_ctrl_lc_escalation.3114353703
/workspace/coverage/default/12.sram_ctrl_max_throughput.3084930930
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.3421179963
/workspace/coverage/default/12.sram_ctrl_mem_walk.2865969660
/workspace/coverage/default/12.sram_ctrl_multiple_keys.934598814
/workspace/coverage/default/12.sram_ctrl_partial_access.2819545960
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.108141675
/workspace/coverage/default/12.sram_ctrl_ram_cfg.3060923535
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/workspace/coverage/default/43.sram_ctrl_stress_pipeline.1061459982
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1579471293
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.2609361638
/workspace/coverage/default/44.sram_ctrl_alert_test.653967212
/workspace/coverage/default/44.sram_ctrl_bijection.2888444023
/workspace/coverage/default/44.sram_ctrl_executable.4150494018
/workspace/coverage/default/44.sram_ctrl_lc_escalation.2060486595
/workspace/coverage/default/44.sram_ctrl_max_throughput.1442578784
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.1664541310
/workspace/coverage/default/44.sram_ctrl_mem_walk.204806686
/workspace/coverage/default/44.sram_ctrl_multiple_keys.2420980258
/workspace/coverage/default/44.sram_ctrl_partial_access.271437826
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.97604405
/workspace/coverage/default/44.sram_ctrl_ram_cfg.3273643518
/workspace/coverage/default/44.sram_ctrl_regwen.1004787719
/workspace/coverage/default/44.sram_ctrl_smoke.2822840708
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2821643235
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.2987961575
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2911074243
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3292968285
/workspace/coverage/default/45.sram_ctrl_alert_test.1767901315
/workspace/coverage/default/45.sram_ctrl_bijection.4250414341
/workspace/coverage/default/45.sram_ctrl_executable.2859555429
/workspace/coverage/default/45.sram_ctrl_lc_escalation.4027244832
/workspace/coverage/default/45.sram_ctrl_max_throughput.1515352438
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.1283571959
/workspace/coverage/default/45.sram_ctrl_mem_walk.2051181448
/workspace/coverage/default/45.sram_ctrl_multiple_keys.1891008002
/workspace/coverage/default/45.sram_ctrl_partial_access.3084552707
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.4017190935
/workspace/coverage/default/45.sram_ctrl_ram_cfg.3412461470
/workspace/coverage/default/45.sram_ctrl_regwen.2873466653
/workspace/coverage/default/45.sram_ctrl_smoke.3348569460
/workspace/coverage/default/45.sram_ctrl_stress_all.2293925940
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3361871390
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.937363391
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.565211241
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.1078183047
/workspace/coverage/default/46.sram_ctrl_alert_test.2567455332
/workspace/coverage/default/46.sram_ctrl_bijection.1426245482
/workspace/coverage/default/46.sram_ctrl_executable.1604655666
/workspace/coverage/default/46.sram_ctrl_lc_escalation.228737272
/workspace/coverage/default/46.sram_ctrl_max_throughput.2420884608
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.2068007702
/workspace/coverage/default/46.sram_ctrl_mem_walk.3069864065
/workspace/coverage/default/46.sram_ctrl_multiple_keys.381634190
/workspace/coverage/default/46.sram_ctrl_partial_access.863696194
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3219691428
/workspace/coverage/default/46.sram_ctrl_ram_cfg.1331042818
/workspace/coverage/default/46.sram_ctrl_regwen.1521338665
/workspace/coverage/default/46.sram_ctrl_smoke.948662646
/workspace/coverage/default/46.sram_ctrl_stress_all.1532443597
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3738002162
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.186095473
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1523743280
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.790948302
/workspace/coverage/default/47.sram_ctrl_alert_test.483850846
/workspace/coverage/default/47.sram_ctrl_bijection.735798901
/workspace/coverage/default/47.sram_ctrl_executable.473923703
/workspace/coverage/default/47.sram_ctrl_lc_escalation.2310081973
/workspace/coverage/default/47.sram_ctrl_max_throughput.576175511
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.1620941648
/workspace/coverage/default/47.sram_ctrl_mem_walk.3056263168
/workspace/coverage/default/47.sram_ctrl_multiple_keys.795511242
/workspace/coverage/default/47.sram_ctrl_partial_access.91823532
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3322743535
/workspace/coverage/default/47.sram_ctrl_ram_cfg.981126409
/workspace/coverage/default/47.sram_ctrl_regwen.978796854
/workspace/coverage/default/47.sram_ctrl_smoke.877450024
/workspace/coverage/default/47.sram_ctrl_stress_all.1696275470
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.4214976015
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3891043437
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3573595954
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.817166729
/workspace/coverage/default/48.sram_ctrl_alert_test.23694780
/workspace/coverage/default/48.sram_ctrl_bijection.3270160372
/workspace/coverage/default/48.sram_ctrl_executable.1359152515
/workspace/coverage/default/48.sram_ctrl_lc_escalation.384537773
/workspace/coverage/default/48.sram_ctrl_max_throughput.2759725975
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.2975750219
/workspace/coverage/default/48.sram_ctrl_mem_walk.1745834213
/workspace/coverage/default/48.sram_ctrl_multiple_keys.2397283964
/workspace/coverage/default/48.sram_ctrl_partial_access.407685619
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.134452115
/workspace/coverage/default/48.sram_ctrl_ram_cfg.4285063547
/workspace/coverage/default/48.sram_ctrl_regwen.2266048319
/workspace/coverage/default/48.sram_ctrl_smoke.925389379
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2826350206
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.2975919329
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2536978156
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.405414700
/workspace/coverage/default/49.sram_ctrl_alert_test.1014953272
/workspace/coverage/default/49.sram_ctrl_bijection.2416360166
/workspace/coverage/default/49.sram_ctrl_executable.4096405390
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2346632668
/workspace/coverage/default/49.sram_ctrl_max_throughput.1981132636
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.315049344
/workspace/coverage/default/49.sram_ctrl_mem_walk.117456100
/workspace/coverage/default/49.sram_ctrl_multiple_keys.2540259950
/workspace/coverage/default/49.sram_ctrl_partial_access.1895744762
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1266033991
/workspace/coverage/default/49.sram_ctrl_ram_cfg.3144569718
/workspace/coverage/default/49.sram_ctrl_regwen.2473715201
/workspace/coverage/default/49.sram_ctrl_smoke.3325563217
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2811365510
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.3547245698
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3871982809
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.121561249
/workspace/coverage/default/5.sram_ctrl_alert_test.3895256472
/workspace/coverage/default/5.sram_ctrl_bijection.1135996260
/workspace/coverage/default/5.sram_ctrl_executable.2521809086
/workspace/coverage/default/5.sram_ctrl_lc_escalation.4144266981
/workspace/coverage/default/5.sram_ctrl_max_throughput.2349897422
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.1932424193
/workspace/coverage/default/5.sram_ctrl_mem_walk.2848233160
/workspace/coverage/default/5.sram_ctrl_multiple_keys.552806893
/workspace/coverage/default/5.sram_ctrl_partial_access.2306749626
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3728016154
/workspace/coverage/default/5.sram_ctrl_ram_cfg.3980640003
/workspace/coverage/default/5.sram_ctrl_regwen.4181309750
/workspace/coverage/default/5.sram_ctrl_smoke.463055339
/workspace/coverage/default/5.sram_ctrl_stress_all.3558295716
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2483657765
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.3883441856
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3664934639
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.1735055476
/workspace/coverage/default/6.sram_ctrl_alert_test.1949035114
/workspace/coverage/default/6.sram_ctrl_bijection.4125877849
/workspace/coverage/default/6.sram_ctrl_executable.1452751603
/workspace/coverage/default/6.sram_ctrl_lc_escalation.2651003105
/workspace/coverage/default/6.sram_ctrl_max_throughput.3027198279
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.3947159301
/workspace/coverage/default/6.sram_ctrl_mem_walk.3377460650
/workspace/coverage/default/6.sram_ctrl_multiple_keys.1445986567
/workspace/coverage/default/6.sram_ctrl_partial_access.1217100476
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2470718972
/workspace/coverage/default/6.sram_ctrl_ram_cfg.4171102636
/workspace/coverage/default/6.sram_ctrl_regwen.544535888
/workspace/coverage/default/6.sram_ctrl_smoke.3087390850
/workspace/coverage/default/6.sram_ctrl_stress_all.4233016926
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2896295401
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.868620606
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1386799524
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.2200542139
/workspace/coverage/default/7.sram_ctrl_alert_test.764503037
/workspace/coverage/default/7.sram_ctrl_bijection.3292960039
/workspace/coverage/default/7.sram_ctrl_executable.2978015544
/workspace/coverage/default/7.sram_ctrl_lc_escalation.3136914643
/workspace/coverage/default/7.sram_ctrl_max_throughput.706485056
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.2416120518
/workspace/coverage/default/7.sram_ctrl_mem_walk.3302946532
/workspace/coverage/default/7.sram_ctrl_multiple_keys.3377386107
/workspace/coverage/default/7.sram_ctrl_partial_access.1941772290
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.178490749
/workspace/coverage/default/7.sram_ctrl_ram_cfg.2314562818
/workspace/coverage/default/7.sram_ctrl_regwen.3690725626
/workspace/coverage/default/7.sram_ctrl_smoke.1986434611
/workspace/coverage/default/7.sram_ctrl_stress_all.2947516837
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1476012523
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.3823948125
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.196457702
/workspace/coverage/default/8.sram_ctrl_alert_test.2176664169
/workspace/coverage/default/8.sram_ctrl_bijection.1291882744
/workspace/coverage/default/8.sram_ctrl_executable.1107687008
/workspace/coverage/default/8.sram_ctrl_lc_escalation.988796498
/workspace/coverage/default/8.sram_ctrl_max_throughput.318708622
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.2854555111
/workspace/coverage/default/8.sram_ctrl_mem_walk.2887361868
/workspace/coverage/default/8.sram_ctrl_multiple_keys.2861242280
/workspace/coverage/default/8.sram_ctrl_partial_access.357617807
/workspace/coverage/default/8.sram_ctrl_ram_cfg.927989444
/workspace/coverage/default/8.sram_ctrl_regwen.4070388269
/workspace/coverage/default/8.sram_ctrl_smoke.983962647
/workspace/coverage/default/8.sram_ctrl_stress_all.3689117510
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.2634780869
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1084650956
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.3527605796
/workspace/coverage/default/9.sram_ctrl_alert_test.3147146502
/workspace/coverage/default/9.sram_ctrl_bijection.3061913792
/workspace/coverage/default/9.sram_ctrl_executable.3051172065
/workspace/coverage/default/9.sram_ctrl_lc_escalation.2224895307
/workspace/coverage/default/9.sram_ctrl_max_throughput.4172054825
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.400562105
/workspace/coverage/default/9.sram_ctrl_mem_walk.3700680726
/workspace/coverage/default/9.sram_ctrl_multiple_keys.3504179113
/workspace/coverage/default/9.sram_ctrl_partial_access.2477143086
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3253310455
/workspace/coverage/default/9.sram_ctrl_ram_cfg.3677810769
/workspace/coverage/default/9.sram_ctrl_regwen.3522966993
/workspace/coverage/default/9.sram_ctrl_smoke.947386346
/workspace/coverage/default/9.sram_ctrl_stress_all.2294102152
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.621998149
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.2673636096
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2618098623



Total test records in report: 1021
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3443302344 Aug 15 04:36:09 PM PDT 24 Aug 15 04:42:38 PM PDT 24 33278622763 ps
T2 /workspace/coverage/default/48.sram_ctrl_alert_test.23694780 Aug 15 04:39:16 PM PDT 24 Aug 15 04:39:17 PM PDT 24 46588069 ps
T3 /workspace/coverage/default/11.sram_ctrl_executable.381914525 Aug 15 04:36:27 PM PDT 24 Aug 15 04:58:30 PM PDT 24 62222584914 ps
T4 /workspace/coverage/default/18.sram_ctrl_stress_all.3189244035 Aug 15 04:36:57 PM PDT 24 Aug 15 05:26:19 PM PDT 24 187805329881 ps
T8 /workspace/coverage/default/29.sram_ctrl_alert_test.2587605366 Aug 15 04:37:24 PM PDT 24 Aug 15 04:37:25 PM PDT 24 13719668 ps
T9 /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.798744460 Aug 15 04:38:00 PM PDT 24 Aug 15 04:45:00 PM PDT 24 44567804483 ps
T10 /workspace/coverage/default/6.sram_ctrl_mem_walk.3377460650 Aug 15 04:36:03 PM PDT 24 Aug 15 04:36:13 PM PDT 24 715507169 ps
T11 /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3691657765 Aug 15 04:37:33 PM PDT 24 Aug 15 04:38:06 PM PDT 24 700518979 ps
T12 /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2807859741 Aug 15 04:38:29 PM PDT 24 Aug 15 04:39:02 PM PDT 24 132950042 ps
T13 /workspace/coverage/default/18.sram_ctrl_bijection.4166013051 Aug 15 04:36:46 PM PDT 24 Aug 15 04:37:10 PM PDT 24 1404844541 ps
T14 /workspace/coverage/default/1.sram_ctrl_alert_test.2100118366 Aug 15 04:35:44 PM PDT 24 Aug 15 04:35:45 PM PDT 24 40932702 ps
T22 /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.536557617 Aug 15 04:38:01 PM PDT 24 Aug 15 04:40:39 PM PDT 24 2972338676 ps
T37 /workspace/coverage/default/43.sram_ctrl_max_throughput.1088847432 Aug 15 04:38:37 PM PDT 24 Aug 15 04:38:38 PM PDT 24 73209881 ps
T38 /workspace/coverage/default/29.sram_ctrl_partial_access.4075946807 Aug 15 04:37:26 PM PDT 24 Aug 15 04:37:53 PM PDT 24 298278980 ps
T17 /workspace/coverage/default/7.sram_ctrl_regwen.3690725626 Aug 15 04:36:06 PM PDT 24 Aug 15 04:48:43 PM PDT 24 2290711227 ps
T51 /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2911074243 Aug 15 04:38:46 PM PDT 24 Aug 15 04:38:48 PM PDT 24 46223649 ps
T59 /workspace/coverage/default/7.sram_ctrl_max_throughput.706485056 Aug 15 04:36:01 PM PDT 24 Aug 15 04:36:05 PM PDT 24 95063432 ps
T60 /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2240548187 Aug 15 04:35:51 PM PDT 24 Aug 15 04:36:37 PM PDT 24 136465200 ps
T61 /workspace/coverage/default/5.sram_ctrl_alert_test.3895256472 Aug 15 04:36:09 PM PDT 24 Aug 15 04:36:10 PM PDT 24 14368674 ps
T39 /workspace/coverage/default/36.sram_ctrl_access_during_key_req.649705735 Aug 15 04:38:00 PM PDT 24 Aug 15 04:41:58 PM PDT 24 6175039522 ps
T42 /workspace/coverage/default/39.sram_ctrl_executable.456053671 Aug 15 04:38:15 PM PDT 24 Aug 15 04:49:45 PM PDT 24 30611628655 ps
T84 /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.3597851435 Aug 15 04:36:31 PM PDT 24 Aug 15 04:36:38 PM PDT 24 63288298 ps
T23 /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3362973953 Aug 15 04:37:42 PM PDT 24 Aug 15 04:46:46 PM PDT 24 1322020461 ps
T7 /workspace/coverage/default/1.sram_ctrl_sec_cm.67075591 Aug 15 04:36:09 PM PDT 24 Aug 15 04:36:11 PM PDT 24 483672918 ps
T30 /workspace/coverage/default/27.sram_ctrl_multiple_keys.1215713989 Aug 15 04:37:20 PM PDT 24 Aug 15 04:48:42 PM PDT 24 13421397146 ps
T5 /workspace/coverage/default/26.sram_ctrl_lc_escalation.673414822 Aug 15 04:37:10 PM PDT 24 Aug 15 04:37:14 PM PDT 24 668390195 ps
T31 /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3573595954 Aug 15 04:38:59 PM PDT 24 Aug 15 04:41:18 PM PDT 24 545914874 ps
T32 /workspace/coverage/default/45.sram_ctrl_executable.2859555429 Aug 15 04:38:52 PM PDT 24 Aug 15 04:55:02 PM PDT 24 3494835415 ps
T24 /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2896295401 Aug 15 04:36:07 PM PDT 24 Aug 15 04:42:40 PM PDT 24 5904684134 ps
T33 /workspace/coverage/default/49.sram_ctrl_multiple_keys.2540259950 Aug 15 04:39:14 PM PDT 24 Aug 15 04:39:49 PM PDT 24 4097627219 ps
T34 /workspace/coverage/default/35.sram_ctrl_max_throughput.3698313747 Aug 15 04:37:49 PM PDT 24 Aug 15 04:39:16 PM PDT 24 162876710 ps
T35 /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.685005407 Aug 15 04:35:59 PM PDT 24 Aug 15 04:44:50 PM PDT 24 22421928505 ps
T36 /workspace/coverage/default/6.sram_ctrl_max_throughput.3027198279 Aug 15 04:36:04 PM PDT 24 Aug 15 04:38:34 PM PDT 24 611298297 ps
T153 /workspace/coverage/default/41.sram_ctrl_max_throughput.2258603289 Aug 15 04:38:21 PM PDT 24 Aug 15 04:39:25 PM PDT 24 637346330 ps
T40 /workspace/coverage/default/18.sram_ctrl_access_during_key_req.1373883946 Aug 15 04:36:50 PM PDT 24 Aug 15 04:47:40 PM PDT 24 2116504816 ps
T149 /workspace/coverage/default/36.sram_ctrl_bijection.723980228 Aug 15 04:37:48 PM PDT 24 Aug 15 04:39:11 PM PDT 24 20695161683 ps
T101 /workspace/coverage/default/38.sram_ctrl_stress_pipeline.1564208952 Aug 15 04:38:04 PM PDT 24 Aug 15 04:42:07 PM PDT 24 13718020586 ps
T148 /workspace/coverage/default/29.sram_ctrl_multiple_keys.1813473961 Aug 15 04:37:22 PM PDT 24 Aug 15 04:48:51 PM PDT 24 17668841236 ps
T25 /workspace/coverage/default/7.sram_ctrl_ram_cfg.2314562818 Aug 15 04:36:07 PM PDT 24 Aug 15 04:36:08 PM PDT 24 81221883 ps
T6 /workspace/coverage/default/49.sram_ctrl_lc_escalation.2346632668 Aug 15 04:39:13 PM PDT 24 Aug 15 04:39:20 PM PDT 24 551336829 ps
T152 /workspace/coverage/default/28.sram_ctrl_alert_test.3078962952 Aug 15 04:37:25 PM PDT 24 Aug 15 04:37:25 PM PDT 24 31484121 ps
T154 /workspace/coverage/default/1.sram_ctrl_smoke.3635966896 Aug 15 04:35:51 PM PDT 24 Aug 15 04:35:53 PM PDT 24 37166035 ps
T155 /workspace/coverage/default/45.sram_ctrl_partial_access.3084552707 Aug 15 04:38:51 PM PDT 24 Aug 15 04:38:58 PM PDT 24 136274680 ps
T68 /workspace/coverage/default/37.sram_ctrl_lc_escalation.3240142288 Aug 15 04:37:59 PM PDT 24 Aug 15 04:38:05 PM PDT 24 3046639580 ps
T69 /workspace/coverage/default/21.sram_ctrl_regwen.2085567497 Aug 15 04:37:06 PM PDT 24 Aug 15 04:56:19 PM PDT 24 55205056260 ps
T102 /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.1903161910 Aug 15 04:36:59 PM PDT 24 Aug 15 04:43:45 PM PDT 24 16205900449 ps
T156 /workspace/coverage/default/19.sram_ctrl_max_throughput.3646554328 Aug 15 04:36:39 PM PDT 24 Aug 15 04:36:40 PM PDT 24 36216103 ps
T46 /workspace/coverage/default/27.sram_ctrl_mem_partial_access.2420537466 Aug 15 04:37:17 PM PDT 24 Aug 15 04:37:22 PM PDT 24 169387593 ps
T52 /workspace/coverage/default/8.sram_ctrl_mem_walk.2887361868 Aug 15 04:36:09 PM PDT 24 Aug 15 04:36:20 PM PDT 24 2138579236 ps
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T41 /workspace/coverage/default/32.sram_ctrl_access_during_key_req.2251817706 Aug 15 04:37:32 PM PDT 24 Aug 15 04:50:07 PM PDT 24 4238572168 ps
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T19 /workspace/coverage/default/10.sram_ctrl_stress_all.3436357623 Aug 15 04:36:26 PM PDT 24 Aug 15 05:31:55 PM PDT 24 65308636452 ps
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T104 /workspace/coverage/default/29.sram_ctrl_stress_pipeline.2201795446 Aug 15 04:37:24 PM PDT 24 Aug 15 04:41:27 PM PDT 24 4027070107 ps
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T54 /workspace/coverage/default/32.sram_ctrl_mem_partial_access.2031289418 Aug 15 04:37:32 PM PDT 24 Aug 15 04:37:35 PM PDT 24 108763317 ps
T89 /workspace/coverage/default/9.sram_ctrl_access_during_key_req.3527605796 Aug 15 04:36:18 PM PDT 24 Aug 15 05:01:13 PM PDT 24 10163532940 ps
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T167 /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1511378257 Aug 15 04:35:58 PM PDT 24 Aug 15 04:36:04 PM PDT 24 980263829 ps
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T169 /workspace/coverage/default/32.sram_ctrl_max_throughput.3083362161 Aug 15 04:37:34 PM PDT 24 Aug 15 04:38:53 PM PDT 24 237274396 ps
T170 /workspace/coverage/default/3.sram_ctrl_bijection.2569847119 Aug 15 04:35:54 PM PDT 24 Aug 15 04:36:52 PM PDT 24 17526090992 ps
T90 /workspace/coverage/default/14.sram_ctrl_access_during_key_req.2904869894 Aug 15 04:36:32 PM PDT 24 Aug 15 04:52:20 PM PDT 24 2641363188 ps
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T173 /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.2424311349 Aug 15 04:36:47 PM PDT 24 Aug 15 04:37:19 PM PDT 24 392796013 ps
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T174 /workspace/coverage/default/49.sram_ctrl_bijection.2416360166 Aug 15 04:39:13 PM PDT 24 Aug 15 04:40:40 PM PDT 24 5352705350 ps
T175 /workspace/coverage/default/14.sram_ctrl_stress_pipeline.3242940038 Aug 15 04:36:40 PM PDT 24 Aug 15 04:41:28 PM PDT 24 11885936382 ps
T21 /workspace/coverage/default/30.sram_ctrl_lc_escalation.433980505 Aug 15 04:37:23 PM PDT 24 Aug 15 04:37:29 PM PDT 24 581497286 ps
T70 /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.273529894 Aug 15 04:35:54 PM PDT 24 Aug 15 04:36:01 PM PDT 24 451398177 ps
T118 /workspace/coverage/default/26.sram_ctrl_partial_access.1056646779 Aug 15 04:37:07 PM PDT 24 Aug 15 04:37:14 PM PDT 24 232338602 ps
T55 /workspace/coverage/default/49.sram_ctrl_mem_walk.117456100 Aug 15 04:39:15 PM PDT 24 Aug 15 04:39:26 PM PDT 24 642643373 ps
T119 /workspace/coverage/default/41.sram_ctrl_alert_test.1519523434 Aug 15 04:38:26 PM PDT 24 Aug 15 04:38:27 PM PDT 24 22692126 ps
T91 /workspace/coverage/default/8.sram_ctrl_access_during_key_req.196457702 Aug 15 04:36:26 PM PDT 24 Aug 15 04:52:44 PM PDT 24 2635398005 ps
T120 /workspace/coverage/default/7.sram_ctrl_lc_escalation.3136914643 Aug 15 04:36:06 PM PDT 24 Aug 15 04:36:13 PM PDT 24 2020229586 ps
T121 /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.2463292328 Aug 15 04:37:25 PM PDT 24 Aug 15 04:43:30 PM PDT 24 56253238319 ps
T122 /workspace/coverage/default/41.sram_ctrl_lc_escalation.3867779649 Aug 15 04:38:21 PM PDT 24 Aug 15 04:38:27 PM PDT 24 3585762536 ps
T92 /workspace/coverage/default/47.sram_ctrl_access_during_key_req.790948302 Aug 15 04:39:03 PM PDT 24 Aug 15 04:48:45 PM PDT 24 11580595260 ps
T123 /workspace/coverage/default/11.sram_ctrl_smoke.1165345627 Aug 15 04:36:21 PM PDT 24 Aug 15 04:37:57 PM PDT 24 377245500 ps
T176 /workspace/coverage/default/0.sram_ctrl_bijection.2891506617 Aug 15 04:36:00 PM PDT 24 Aug 15 04:36:57 PM PDT 24 6976191983 ps
T177 /workspace/coverage/default/28.sram_ctrl_smoke.35801760 Aug 15 04:37:19 PM PDT 24 Aug 15 04:37:31 PM PDT 24 715232221 ps
T178 /workspace/coverage/default/16.sram_ctrl_lc_escalation.2579299810 Aug 15 04:36:31 PM PDT 24 Aug 15 04:36:41 PM PDT 24 2818669460 ps
T179 /workspace/coverage/default/22.sram_ctrl_multiple_keys.3667440387 Aug 15 04:37:00 PM PDT 24 Aug 15 04:49:10 PM PDT 24 5332621965 ps
T180 /workspace/coverage/default/46.sram_ctrl_max_throughput.2420884608 Aug 15 04:38:53 PM PDT 24 Aug 15 04:39:07 PM PDT 24 254634255 ps
T181 /workspace/coverage/default/38.sram_ctrl_partial_access.1473382629 Aug 15 04:38:05 PM PDT 24 Aug 15 04:38:16 PM PDT 24 2194648696 ps
T182 /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.3532080033 Aug 15 04:37:35 PM PDT 24 Aug 15 04:39:51 PM PDT 24 175821530 ps
T183 /workspace/coverage/default/45.sram_ctrl_lc_escalation.4027244832 Aug 15 04:38:53 PM PDT 24 Aug 15 04:39:02 PM PDT 24 2624943274 ps
T56 /workspace/coverage/default/16.sram_ctrl_mem_partial_access.3268204370 Aug 15 04:36:33 PM PDT 24 Aug 15 04:36:38 PM PDT 24 107430803 ps
T184 /workspace/coverage/default/40.sram_ctrl_bijection.635746841 Aug 15 04:38:13 PM PDT 24 Aug 15 04:38:34 PM PDT 24 331517479 ps
T143 /workspace/coverage/default/0.sram_ctrl_executable.119291472 Aug 15 04:36:05 PM PDT 24 Aug 15 04:44:27 PM PDT 24 4995713123 ps
T185 /workspace/coverage/default/17.sram_ctrl_partial_access.2727197555 Aug 15 04:36:26 PM PDT 24 Aug 15 04:36:36 PM PDT 24 627374792 ps
T186 /workspace/coverage/default/1.sram_ctrl_multiple_keys.2379360787 Aug 15 04:35:46 PM PDT 24 Aug 15 04:48:04 PM PDT 24 9651167096 ps
T47 /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2790390664 Aug 15 04:36:31 PM PDT 24 Aug 15 04:37:02 PM PDT 24 1662346580 ps
T144 /workspace/coverage/default/44.sram_ctrl_executable.4150494018 Aug 15 04:38:45 PM PDT 24 Aug 15 04:48:43 PM PDT 24 2898128498 ps
T187 /workspace/coverage/default/35.sram_ctrl_access_during_key_req.1692719438 Aug 15 04:37:49 PM PDT 24 Aug 15 04:42:16 PM PDT 24 2496386381 ps
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T189 /workspace/coverage/default/14.sram_ctrl_bijection.1685736892 Aug 15 04:36:44 PM PDT 24 Aug 15 04:37:41 PM PDT 24 3591283730 ps
T190 /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.4220466051 Aug 15 04:37:05 PM PDT 24 Aug 15 04:44:11 PM PDT 24 5870403031 ps
T191 /workspace/coverage/default/20.sram_ctrl_mem_walk.849104590 Aug 15 04:36:58 PM PDT 24 Aug 15 04:37:09 PM PDT 24 1833983741 ps
T192 /workspace/coverage/default/13.sram_ctrl_partial_access.3570950784 Aug 15 04:36:22 PM PDT 24 Aug 15 04:36:40 PM PDT 24 929719435 ps
T193 /workspace/coverage/default/44.sram_ctrl_access_during_key_req.2609361638 Aug 15 04:38:45 PM PDT 24 Aug 15 04:42:32 PM PDT 24 1524147758 ps
T194 /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2536978156 Aug 15 04:39:07 PM PDT 24 Aug 15 04:39:40 PM PDT 24 200858006 ps
T195 /workspace/coverage/default/32.sram_ctrl_stress_pipeline.1893340516 Aug 15 04:37:34 PM PDT 24 Aug 15 04:40:56 PM PDT 24 2133010214 ps
T196 /workspace/coverage/default/39.sram_ctrl_lc_escalation.3121716240 Aug 15 04:38:14 PM PDT 24 Aug 15 04:38:19 PM PDT 24 371335411 ps
T197 /workspace/coverage/default/16.sram_ctrl_stress_pipeline.1257033424 Aug 15 04:36:31 PM PDT 24 Aug 15 04:40:30 PM PDT 24 4647548410 ps
T57 /workspace/coverage/default/11.sram_ctrl_mem_partial_access.24062917 Aug 15 04:36:33 PM PDT 24 Aug 15 04:36:36 PM PDT 24 383781734 ps
T198 /workspace/coverage/default/15.sram_ctrl_ram_cfg.3087558040 Aug 15 04:36:34 PM PDT 24 Aug 15 04:36:35 PM PDT 24 27538420 ps
T199 /workspace/coverage/default/0.sram_ctrl_mem_partial_access.1311076601 Aug 15 04:36:06 PM PDT 24 Aug 15 04:36:10 PM PDT 24 250631460 ps
T200 /workspace/coverage/default/13.sram_ctrl_stress_all.3060046160 Aug 15 04:36:33 PM PDT 24 Aug 15 05:00:04 PM PDT 24 80750364047 ps
T201 /workspace/coverage/default/41.sram_ctrl_stress_all.922217941 Aug 15 04:38:26 PM PDT 24 Aug 15 04:48:58 PM PDT 24 58204299735 ps
T202 /workspace/coverage/default/42.sram_ctrl_bijection.3254750334 Aug 15 04:38:29 PM PDT 24 Aug 15 04:38:55 PM PDT 24 1638872205 ps
T203 /workspace/coverage/default/31.sram_ctrl_alert_test.1653316690 Aug 15 04:37:35 PM PDT 24 Aug 15 04:37:36 PM PDT 24 42192985 ps
T204 /workspace/coverage/default/37.sram_ctrl_multiple_keys.3298883804 Aug 15 04:37:58 PM PDT 24 Aug 15 05:01:26 PM PDT 24 28159427713 ps
T58 /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3609438190 Aug 15 04:37:15 PM PDT 24 Aug 15 04:40:00 PM PDT 24 6396403363 ps
T205 /workspace/coverage/default/31.sram_ctrl_partial_access.563701810 Aug 15 04:37:34 PM PDT 24 Aug 15 04:37:56 PM PDT 24 1005264660 ps
T206 /workspace/coverage/default/34.sram_ctrl_ram_cfg.2653297121 Aug 15 04:37:41 PM PDT 24 Aug 15 04:37:42 PM PDT 24 44845016 ps
T207 /workspace/coverage/default/21.sram_ctrl_smoke.717030730 Aug 15 04:37:04 PM PDT 24 Aug 15 04:37:19 PM PDT 24 246998893 ps
T208 /workspace/coverage/default/14.sram_ctrl_max_throughput.3647145172 Aug 15 04:36:28 PM PDT 24 Aug 15 04:38:29 PM PDT 24 128190033 ps
T209 /workspace/coverage/default/47.sram_ctrl_smoke.877450024 Aug 15 04:39:01 PM PDT 24 Aug 15 04:39:14 PM PDT 24 2827013498 ps
T210 /workspace/coverage/default/47.sram_ctrl_executable.473923703 Aug 15 04:38:59 PM PDT 24 Aug 15 04:47:44 PM PDT 24 76958066535 ps
T211 /workspace/coverage/default/28.sram_ctrl_partial_access.3999760925 Aug 15 04:37:19 PM PDT 24 Aug 15 04:37:21 PM PDT 24 300936062 ps
T212 /workspace/coverage/default/24.sram_ctrl_ram_cfg.3082948965 Aug 15 04:37:01 PM PDT 24 Aug 15 04:37:02 PM PDT 24 86891941 ps
T213 /workspace/coverage/default/2.sram_ctrl_ram_cfg.1700567486 Aug 15 04:35:54 PM PDT 24 Aug 15 04:35:55 PM PDT 24 95018600 ps
T214 /workspace/coverage/default/15.sram_ctrl_multiple_keys.3230175681 Aug 15 04:36:28 PM PDT 24 Aug 15 04:58:13 PM PDT 24 12283835663 ps
T215 /workspace/coverage/default/17.sram_ctrl_mem_walk.1336450794 Aug 15 04:36:35 PM PDT 24 Aug 15 04:36:41 PM PDT 24 3165480048 ps
T216 /workspace/coverage/default/19.sram_ctrl_mem_partial_access.39661176 Aug 15 04:36:52 PM PDT 24 Aug 15 04:36:57 PM PDT 24 182407920 ps
T217 /workspace/coverage/default/2.sram_ctrl_max_throughput.3160306746 Aug 15 04:35:54 PM PDT 24 Aug 15 04:37:26 PM PDT 24 117143515 ps
T218 /workspace/coverage/default/19.sram_ctrl_stress_pipeline.3559409631 Aug 15 04:36:52 PM PDT 24 Aug 15 04:39:42 PM PDT 24 3539802520 ps
T219 /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.97604405 Aug 15 04:38:45 PM PDT 24 Aug 15 04:47:26 PM PDT 24 87934681327 ps
T220 /workspace/coverage/default/16.sram_ctrl_multiple_keys.231483374 Aug 15 04:36:39 PM PDT 24 Aug 15 04:47:29 PM PDT 24 37284946377 ps
T48 /workspace/coverage/default/14.sram_ctrl_mem_walk.1194794769 Aug 15 04:36:24 PM PDT 24 Aug 15 04:36:31 PM PDT 24 2784786146 ps
T145 /workspace/coverage/default/3.sram_ctrl_regwen.373530649 Aug 15 04:36:09 PM PDT 24 Aug 15 05:03:52 PM PDT 24 24788403045 ps
T221 /workspace/coverage/default/2.sram_ctrl_regwen.1521860322 Aug 15 04:35:58 PM PDT 24 Aug 15 04:55:17 PM PDT 24 11612184031 ps
T222 /workspace/coverage/default/49.sram_ctrl_mem_partial_access.315049344 Aug 15 04:39:22 PM PDT 24 Aug 15 04:39:25 PM PDT 24 85328479 ps
T223 /workspace/coverage/default/38.sram_ctrl_multiple_keys.4173245024 Aug 15 04:38:06 PM PDT 24 Aug 15 04:46:11 PM PDT 24 32166781560 ps
T224 /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.3182058204 Aug 15 04:37:03 PM PDT 24 Aug 15 04:37:38 PM PDT 24 1006961079 ps
T225 /workspace/coverage/default/41.sram_ctrl_ram_cfg.775729312 Aug 15 04:38:22 PM PDT 24 Aug 15 04:38:23 PM PDT 24 94070029 ps
T226 /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.3656993452 Aug 15 04:36:04 PM PDT 24 Aug 15 04:43:11 PM PDT 24 19258748782 ps
T71 /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2504549210 Aug 15 04:36:22 PM PDT 24 Aug 15 04:36:42 PM PDT 24 432755835 ps
T227 /workspace/coverage/default/5.sram_ctrl_stress_pipeline.3883441856 Aug 15 04:36:06 PM PDT 24 Aug 15 04:39:40 PM PDT 24 2313190385 ps
T141 /workspace/coverage/default/49.sram_ctrl_executable.4096405390 Aug 15 04:39:23 PM PDT 24 Aug 15 04:47:49 PM PDT 24 2126231463 ps
T228 /workspace/coverage/default/13.sram_ctrl_mem_partial_access.3828683 Aug 15 04:36:42 PM PDT 24 Aug 15 04:36:47 PM PDT 24 186781064 ps
T229 /workspace/coverage/default/8.sram_ctrl_bijection.1291882744 Aug 15 04:36:06 PM PDT 24 Aug 15 04:36:48 PM PDT 24 2588830500 ps
T72 /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.1103066953 Aug 15 04:37:26 PM PDT 24 Aug 15 04:41:43 PM PDT 24 5079386291 ps
T230 /workspace/coverage/default/48.sram_ctrl_partial_access.407685619 Aug 15 04:39:07 PM PDT 24 Aug 15 04:39:11 PM PDT 24 115534709 ps
T231 /workspace/coverage/default/27.sram_ctrl_ram_cfg.3103490164 Aug 15 04:37:18 PM PDT 24 Aug 15 04:37:19 PM PDT 24 46777598 ps
T232 /workspace/coverage/default/24.sram_ctrl_executable.3135540601 Aug 15 04:36:59 PM PDT 24 Aug 15 04:46:46 PM PDT 24 57469490088 ps
T233 /workspace/coverage/default/0.sram_ctrl_partial_access.462711904 Aug 15 04:35:55 PM PDT 24 Aug 15 04:38:07 PM PDT 24 2896702081 ps
T234 /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3253310455 Aug 15 04:36:10 PM PDT 24 Aug 15 04:42:11 PM PDT 24 13807689126 ps
T235 /workspace/coverage/default/18.sram_ctrl_lc_escalation.1486663725 Aug 15 04:36:48 PM PDT 24 Aug 15 04:36:51 PM PDT 24 931555114 ps
T49 /workspace/coverage/default/2.sram_ctrl_mem_walk.2103933594 Aug 15 04:35:59 PM PDT 24 Aug 15 04:36:05 PM PDT 24 396862939 ps
T236 /workspace/coverage/default/31.sram_ctrl_smoke.461559665 Aug 15 04:37:23 PM PDT 24 Aug 15 04:37:54 PM PDT 24 328940466 ps
T237 /workspace/coverage/default/40.sram_ctrl_ram_cfg.1673689450 Aug 15 04:38:13 PM PDT 24 Aug 15 04:38:13 PM PDT 24 77144429 ps
T238 /workspace/coverage/default/3.sram_ctrl_executable.1518894384 Aug 15 04:36:04 PM PDT 24 Aug 15 04:45:26 PM PDT 24 11176011247 ps
T239 /workspace/coverage/default/3.sram_ctrl_ram_cfg.4261259676 Aug 15 04:35:54 PM PDT 24 Aug 15 04:35:55 PM PDT 24 218117897 ps
T240 /workspace/coverage/default/42.sram_ctrl_alert_test.2893533421 Aug 15 04:38:30 PM PDT 24 Aug 15 04:38:30 PM PDT 24 167630374 ps
T241 /workspace/coverage/default/11.sram_ctrl_lc_escalation.4026291519 Aug 15 04:36:23 PM PDT 24 Aug 15 04:36:30 PM PDT 24 1572916767 ps
T242 /workspace/coverage/default/17.sram_ctrl_alert_test.249061423 Aug 15 04:36:37 PM PDT 24 Aug 15 04:36:38 PM PDT 24 137356547 ps
T243 /workspace/coverage/default/7.sram_ctrl_partial_access.1941772290 Aug 15 04:36:16 PM PDT 24 Aug 15 04:36:27 PM PDT 24 1265551124 ps
T244 /workspace/coverage/default/31.sram_ctrl_multiple_keys.3719752735 Aug 15 04:37:31 PM PDT 24 Aug 15 04:52:27 PM PDT 24 3728754626 ps
T245 /workspace/coverage/default/1.sram_ctrl_ram_cfg.4268893573 Aug 15 04:36:04 PM PDT 24 Aug 15 04:36:05 PM PDT 24 53226277 ps
T246 /workspace/coverage/default/46.sram_ctrl_bijection.1426245482 Aug 15 04:38:51 PM PDT 24 Aug 15 04:39:56 PM PDT 24 3718219984 ps
T247 /workspace/coverage/default/33.sram_ctrl_regwen.55363042 Aug 15 04:37:40 PM PDT 24 Aug 15 04:52:55 PM PDT 24 12156665628 ps
T248 /workspace/coverage/default/19.sram_ctrl_alert_test.935580846 Aug 15 04:37:19 PM PDT 24 Aug 15 04:37:20 PM PDT 24 65892785 ps
T249 /workspace/coverage/default/48.sram_ctrl_bijection.3270160372 Aug 15 04:39:06 PM PDT 24 Aug 15 04:39:30 PM PDT 24 1052269077 ps
T250 /workspace/coverage/default/20.sram_ctrl_smoke.2085191931 Aug 15 04:36:56 PM PDT 24 Aug 15 04:36:58 PM PDT 24 233769578 ps
T251 /workspace/coverage/default/32.sram_ctrl_executable.3606216702 Aug 15 04:37:34 PM PDT 24 Aug 15 04:49:14 PM PDT 24 15105341828 ps
T252 /workspace/coverage/default/23.sram_ctrl_regwen.4004488413 Aug 15 04:37:02 PM PDT 24 Aug 15 05:04:38 PM PDT 24 9937710166 ps
T253 /workspace/coverage/default/8.sram_ctrl_mem_partial_access.2854555111 Aug 15 04:36:12 PM PDT 24 Aug 15 04:36:17 PM PDT 24 182248094 ps
T73 /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.4214976015 Aug 15 04:39:06 PM PDT 24 Aug 15 04:48:21 PM PDT 24 1680100985 ps
T254 /workspace/coverage/default/32.sram_ctrl_regwen.1879774562 Aug 15 04:37:33 PM PDT 24 Aug 15 05:00:20 PM PDT 24 37596967124 ps
T255 /workspace/coverage/default/39.sram_ctrl_stress_pipeline.45250422 Aug 15 04:38:05 PM PDT 24 Aug 15 04:43:03 PM PDT 24 11090750207 ps
T256 /workspace/coverage/default/12.sram_ctrl_partial_access.2819545960 Aug 15 04:36:28 PM PDT 24 Aug 15 04:36:44 PM PDT 24 290124628 ps
T257 /workspace/coverage/default/24.sram_ctrl_bijection.2040603516 Aug 15 04:37:00 PM PDT 24 Aug 15 04:38:20 PM PDT 24 9511049381 ps
T258 /workspace/coverage/default/23.sram_ctrl_partial_access.2084077494 Aug 15 04:37:04 PM PDT 24 Aug 15 04:38:42 PM PDT 24 3084839581 ps
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