Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	45005634	1			T1	37900		T3	70331		T4	329784
triple_byte_access	2678930	1			T1	33878		T3	1441		T4	6140
halfword_access	4018423	1			T1	51313		T3	2091		T4	9032
byte_access	5371006	1			T1	68410		T3	2757		T4	12150
zero_access	1351254	1			T1	17031		T3	666		T4	3039

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29159486

1

T1

104098

T3

38409

T4

179946

auto[1]

29265761

1

T1

104434

T3

38877

T4

180199

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22454135	1			T1	18956		T3	34962		T4	164815
auto[0]	triple_byte_access	1336076	1			T1	17013		T3	714		T4	3044
auto[0]	halfword_access	2006455	1			T1	25717		T3	1062		T4	4560
auto[0]	byte_access	2683503	1			T1	33943		T3	1345		T4	5999
auto[0]	zero_access	679317	1			T1	8469		T3	326		T4	1528
auto[1]	word_access	22551499	1			T1	18944		T3	35369		T4	164969
auto[1]	triple_byte_access	1342854	1			T1	16865		T3	727		T4	3096
auto[1]	halfword_access	2011968	1			T1	25596		T3	1029		T4	4472
auto[1]	byte_access	2687503	1			T1	34467		T3	1412		T4	6151
auto[1]	zero_access	671937	1			T1	8562		T3	340		T4	1511