| T29 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.3195449277 |
|
|
Aug 15 04:36:03 PM PDT 24 |
Aug 15 04:36:05 PM PDT 24 |
868002367 ps |
| T800 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.3607807241 |
|
|
Aug 15 04:36:38 PM PDT 24 |
Aug 15 04:39:19 PM PDT 24 |
3810705054 ps |
| T801 |
/workspace/coverage/default/16.sram_ctrl_stress_all.4098131847 |
|
|
Aug 15 04:36:38 PM PDT 24 |
Aug 15 05:36:44 PM PDT 24 |
235671488588 ps |
| T802 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.2975919329 |
|
|
Aug 15 04:39:04 PM PDT 24 |
Aug 15 04:43:10 PM PDT 24 |
7134358036 ps |
| T803 |
/workspace/coverage/default/6.sram_ctrl_stress_all.4233016926 |
|
|
Aug 15 04:36:12 PM PDT 24 |
Aug 15 05:25:48 PM PDT 24 |
165931302989 ps |
| T804 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.680763629 |
|
|
Aug 15 04:38:03 PM PDT 24 |
Aug 15 04:38:10 PM PDT 24 |
1628002385 ps |
| T805 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.1628042529 |
|
|
Aug 15 04:36:25 PM PDT 24 |
Aug 15 04:36:34 PM PDT 24 |
567746245 ps |
| T806 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2448852887 |
|
|
Aug 15 04:37:33 PM PDT 24 |
Aug 15 04:47:01 PM PDT 24 |
44236681955 ps |
| T807 |
/workspace/coverage/default/45.sram_ctrl_stress_all.2293925940 |
|
|
Aug 15 04:38:53 PM PDT 24 |
Aug 15 05:19:23 PM PDT 24 |
32962379806 ps |
| T808 |
/workspace/coverage/default/2.sram_ctrl_alert_test.2100171084 |
|
|
Aug 15 04:36:04 PM PDT 24 |
Aug 15 04:36:05 PM PDT 24 |
29418026 ps |
| T809 |
/workspace/coverage/default/26.sram_ctrl_bijection.4276391759 |
|
|
Aug 15 04:37:04 PM PDT 24 |
Aug 15 04:38:08 PM PDT 24 |
6757780679 ps |
| T810 |
/workspace/coverage/default/10.sram_ctrl_alert_test.5654077 |
|
|
Aug 15 04:36:30 PM PDT 24 |
Aug 15 04:36:31 PM PDT 24 |
17497326 ps |
| T811 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3991538410 |
|
|
Aug 15 04:36:39 PM PDT 24 |
Aug 15 04:37:38 PM PDT 24 |
455859465 ps |
| T812 |
/workspace/coverage/default/43.sram_ctrl_executable.2364229125 |
|
|
Aug 15 04:38:35 PM PDT 24 |
Aug 15 04:49:35 PM PDT 24 |
7142812180 ps |
| T813 |
/workspace/coverage/default/29.sram_ctrl_lc_escalation.1554097697 |
|
|
Aug 15 04:37:24 PM PDT 24 |
Aug 15 04:37:30 PM PDT 24 |
3142007693 ps |
| T814 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.580999115 |
|
|
Aug 15 04:38:29 PM PDT 24 |
Aug 15 04:38:51 PM PDT 24 |
1048363140 ps |
| T815 |
/workspace/coverage/default/26.sram_ctrl_executable.677607204 |
|
|
Aug 15 04:37:07 PM PDT 24 |
Aug 15 04:59:27 PM PDT 24 |
34110889867 ps |
| T816 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.407366789 |
|
|
Aug 15 04:37:53 PM PDT 24 |
Aug 15 04:39:29 PM PDT 24 |
856241980 ps |
| T817 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1523743280 |
|
|
Aug 15 04:38:53 PM PDT 24 |
Aug 15 04:39:02 PM PDT 24 |
72486687 ps |
| T818 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.2855233118 |
|
|
Aug 15 04:36:04 PM PDT 24 |
Aug 15 04:36:06 PM PDT 24 |
146438914 ps |
| T819 |
/workspace/coverage/default/3.sram_ctrl_stress_all.1842347873 |
|
|
Aug 15 04:35:53 PM PDT 24 |
Aug 15 05:12:54 PM PDT 24 |
129022448284 ps |
| T820 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.2246045406 |
|
|
Aug 15 04:36:09 PM PDT 24 |
Aug 15 04:36:13 PM PDT 24 |
361431367 ps |
| T821 |
/workspace/coverage/default/12.sram_ctrl_smoke.1977951157 |
|
|
Aug 15 04:36:26 PM PDT 24 |
Aug 15 04:36:30 PM PDT 24 |
282980033 ps |
| T822 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.3244260504 |
|
|
Aug 15 04:37:03 PM PDT 24 |
Aug 15 04:42:13 PM PDT 24 |
887967991 ps |
| T823 |
/workspace/coverage/default/30.sram_ctrl_mem_walk.370810730 |
|
|
Aug 15 04:37:24 PM PDT 24 |
Aug 15 04:37:36 PM PDT 24 |
694569852 ps |
| T824 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.2971158938 |
|
|
Aug 15 04:36:22 PM PDT 24 |
Aug 15 04:40:49 PM PDT 24 |
5475683153 ps |
| T825 |
/workspace/coverage/default/2.sram_ctrl_bijection.2276437280 |
|
|
Aug 15 04:35:48 PM PDT 24 |
Aug 15 04:36:22 PM PDT 24 |
7648566252 ps |
| T826 |
/workspace/coverage/default/42.sram_ctrl_mem_walk.1386240769 |
|
|
Aug 15 04:38:32 PM PDT 24 |
Aug 15 04:38:37 PM PDT 24 |
419355764 ps |
| T827 |
/workspace/coverage/default/23.sram_ctrl_multiple_keys.654873918 |
|
|
Aug 15 04:36:59 PM PDT 24 |
Aug 15 04:41:34 PM PDT 24 |
2380818955 ps |
| T828 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.19203430 |
|
|
Aug 15 04:37:25 PM PDT 24 |
Aug 15 04:37:35 PM PDT 24 |
926825255 ps |
| T829 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.1457962487 |
|
|
Aug 15 04:37:41 PM PDT 24 |
Aug 15 04:43:39 PM PDT 24 |
30172238353 ps |
| T830 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.1828696475 |
|
|
Aug 15 04:37:06 PM PDT 24 |
Aug 15 04:51:10 PM PDT 24 |
2923953494 ps |
| T831 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.1620941648 |
|
|
Aug 15 04:39:07 PM PDT 24 |
Aug 15 04:39:13 PM PDT 24 |
383607869 ps |
| T832 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.2006288319 |
|
|
Aug 15 04:36:34 PM PDT 24 |
Aug 15 04:43:01 PM PDT 24 |
15227488134 ps |
| T833 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.2349897422 |
|
|
Aug 15 04:36:11 PM PDT 24 |
Aug 15 04:38:16 PM PDT 24 |
599663239 ps |
| T834 |
/workspace/coverage/default/23.sram_ctrl_alert_test.2280586371 |
|
|
Aug 15 04:36:57 PM PDT 24 |
Aug 15 04:36:58 PM PDT 24 |
13663515 ps |
| T835 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.754772600 |
|
|
Aug 15 04:37:19 PM PDT 24 |
Aug 15 04:37:25 PM PDT 24 |
418191423 ps |
| T836 |
/workspace/coverage/default/25.sram_ctrl_smoke.2037501674 |
|
|
Aug 15 04:37:01 PM PDT 24 |
Aug 15 04:37:05 PM PDT 24 |
410260702 ps |
| T837 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.435053398 |
|
|
Aug 15 04:36:37 PM PDT 24 |
Aug 15 04:47:29 PM PDT 24 |
10444952276 ps |
| T838 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.4190184295 |
|
|
Aug 15 04:36:49 PM PDT 24 |
Aug 15 04:36:55 PM PDT 24 |
640336270 ps |
| T839 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.2026293332 |
|
|
Aug 15 04:36:03 PM PDT 24 |
Aug 15 04:36:04 PM PDT 24 |
29877858 ps |
| T840 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.2489223323 |
|
|
Aug 15 04:37:05 PM PDT 24 |
Aug 15 04:37:14 PM PDT 24 |
2646465910 ps |
| T841 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.552806893 |
|
|
Aug 15 04:36:12 PM PDT 24 |
Aug 15 04:47:38 PM PDT 24 |
3535713760 ps |
| T842 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.2112729471 |
|
|
Aug 15 04:37:59 PM PDT 24 |
Aug 15 04:39:42 PM PDT 24 |
757617490 ps |
| T843 |
/workspace/coverage/default/2.sram_ctrl_mem_partial_access.3872755711 |
|
|
Aug 15 04:35:55 PM PDT 24 |
Aug 15 04:35:58 PM PDT 24 |
502306493 ps |
| T844 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.2826309614 |
|
|
Aug 15 04:38:30 PM PDT 24 |
Aug 15 04:38:34 PM PDT 24 |
340157020 ps |
| T845 |
/workspace/coverage/default/24.sram_ctrl_partial_access.1128951506 |
|
|
Aug 15 04:36:58 PM PDT 24 |
Aug 15 04:37:17 PM PDT 24 |
1102237127 ps |
| T846 |
/workspace/coverage/default/17.sram_ctrl_smoke.267309534 |
|
|
Aug 15 04:36:34 PM PDT 24 |
Aug 15 04:38:33 PM PDT 24 |
745069576 ps |
| T847 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.3465310491 |
|
|
Aug 15 04:37:43 PM PDT 24 |
Aug 15 04:37:53 PM PDT 24 |
991244028 ps |
| T848 |
/workspace/coverage/default/1.sram_ctrl_executable.2614444107 |
|
|
Aug 15 04:35:45 PM PDT 24 |
Aug 15 04:43:34 PM PDT 24 |
30691583511 ps |
| T849 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.3730198990 |
|
|
Aug 15 04:37:17 PM PDT 24 |
Aug 15 04:37:18 PM PDT 24 |
30562432 ps |
| T850 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.3973654306 |
|
|
Aug 15 04:37:07 PM PDT 24 |
Aug 15 04:37:12 PM PDT 24 |
931345420 ps |
| T851 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.2241156086 |
|
|
Aug 15 04:37:01 PM PDT 24 |
Aug 15 04:41:40 PM PDT 24 |
20173319116 ps |
| T852 |
/workspace/coverage/default/1.sram_ctrl_partial_access.2051690820 |
|
|
Aug 15 04:36:06 PM PDT 24 |
Aug 15 04:37:44 PM PDT 24 |
709332029 ps |
| T853 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.2909352926 |
|
|
Aug 15 04:36:05 PM PDT 24 |
Aug 15 04:36:50 PM PDT 24 |
957587030 ps |
| T854 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.3950782688 |
|
|
Aug 15 04:37:31 PM PDT 24 |
Aug 15 04:37:38 PM PDT 24 |
876742524 ps |
| T855 |
/workspace/coverage/default/6.sram_ctrl_partial_access.1217100476 |
|
|
Aug 15 04:36:10 PM PDT 24 |
Aug 15 04:36:12 PM PDT 24 |
43435858 ps |
| T856 |
/workspace/coverage/default/20.sram_ctrl_stress_all.1830487258 |
|
|
Aug 15 04:36:49 PM PDT 24 |
Aug 15 05:34:11 PM PDT 24 |
142269666432 ps |
| T857 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.2416120518 |
|
|
Aug 15 04:36:04 PM PDT 24 |
Aug 15 04:36:07 PM PDT 24 |
237211312 ps |
| T858 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.3906239125 |
|
|
Aug 15 04:36:06 PM PDT 24 |
Aug 15 04:58:19 PM PDT 24 |
13238255647 ps |
| T859 |
/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.1541100029 |
|
|
Aug 15 04:38:14 PM PDT 24 |
Aug 15 04:39:40 PM PDT 24 |
293186325 ps |
| T860 |
/workspace/coverage/default/47.sram_ctrl_partial_access.91823532 |
|
|
Aug 15 04:38:59 PM PDT 24 |
Aug 15 04:39:10 PM PDT 24 |
1380360222 ps |
| T861 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.1151931258 |
|
|
Aug 15 04:37:42 PM PDT 24 |
Aug 15 04:37:49 PM PDT 24 |
1910682873 ps |
| T862 |
/workspace/coverage/default/8.sram_ctrl_executable.1107687008 |
|
|
Aug 15 04:36:14 PM PDT 24 |
Aug 15 04:46:56 PM PDT 24 |
15686493977 ps |
| T863 |
/workspace/coverage/default/24.sram_ctrl_regwen.1728230040 |
|
|
Aug 15 04:36:58 PM PDT 24 |
Aug 15 05:08:53 PM PDT 24 |
26432333995 ps |
| T864 |
/workspace/coverage/default/34.sram_ctrl_executable.96776169 |
|
|
Aug 15 04:37:50 PM PDT 24 |
Aug 15 04:58:44 PM PDT 24 |
15994181324 ps |
| T865 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.381634190 |
|
|
Aug 15 04:38:53 PM PDT 24 |
Aug 15 04:53:34 PM PDT 24 |
141887473085 ps |
| T866 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.393009537 |
|
|
Aug 15 04:36:31 PM PDT 24 |
Aug 15 04:36:39 PM PDT 24 |
1448841581 ps |
| T867 |
/workspace/coverage/default/42.sram_ctrl_regwen.1203646940 |
|
|
Aug 15 04:38:27 PM PDT 24 |
Aug 15 04:53:36 PM PDT 24 |
7816056771 ps |
| T868 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.3795203029 |
|
|
Aug 15 04:36:27 PM PDT 24 |
Aug 15 04:47:49 PM PDT 24 |
3954331783 ps |
| T869 |
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3132020298 |
|
|
Aug 15 04:35:54 PM PDT 24 |
Aug 15 04:42:00 PM PDT 24 |
3272419129 ps |
| T870 |
/workspace/coverage/default/14.sram_ctrl_executable.3221396781 |
|
|
Aug 15 04:36:26 PM PDT 24 |
Aug 15 04:39:51 PM PDT 24 |
3109566780 ps |
| T871 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.2885830152 |
|
|
Aug 15 04:38:00 PM PDT 24 |
Aug 15 04:44:40 PM PDT 24 |
59461251149 ps |
| T872 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.3934104397 |
|
|
Aug 15 04:36:51 PM PDT 24 |
Aug 15 04:38:30 PM PDT 24 |
141932466 ps |
| T873 |
/workspace/coverage/default/36.sram_ctrl_lc_escalation.3582417005 |
|
|
Aug 15 04:37:59 PM PDT 24 |
Aug 15 04:38:07 PM PDT 24 |
1051119810 ps |
| T874 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.683288656 |
|
|
Aug 15 04:36:49 PM PDT 24 |
Aug 15 04:38:30 PM PDT 24 |
594153591 ps |
| T875 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.2159161793 |
|
|
Aug 15 04:37:26 PM PDT 24 |
Aug 15 04:38:21 PM PDT 24 |
1101420998 ps |
| T876 |
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.3119009974 |
|
|
Aug 15 04:37:23 PM PDT 24 |
Aug 15 04:47:10 PM PDT 24 |
143775954591 ps |
| T877 |
/workspace/coverage/default/48.sram_ctrl_smoke.925389379 |
|
|
Aug 15 04:39:07 PM PDT 24 |
Aug 15 04:39:11 PM PDT 24 |
79190598 ps |
| T878 |
/workspace/coverage/default/37.sram_ctrl_regwen.2178750126 |
|
|
Aug 15 04:37:59 PM PDT 24 |
Aug 15 04:43:04 PM PDT 24 |
9014565431 ps |
| T879 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.2601837716 |
|
|
Aug 15 04:37:43 PM PDT 24 |
Aug 15 04:37:49 PM PDT 24 |
101700124 ps |
| T880 |
/workspace/coverage/default/46.sram_ctrl_partial_access.863696194 |
|
|
Aug 15 04:38:53 PM PDT 24 |
Aug 15 04:39:05 PM PDT 24 |
255131232 ps |
| T881 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.279748811 |
|
|
Aug 15 04:38:30 PM PDT 24 |
Aug 15 04:53:04 PM PDT 24 |
8068291123 ps |
| T882 |
/workspace/coverage/default/33.sram_ctrl_mem_partial_access.859051625 |
|
|
Aug 15 04:37:42 PM PDT 24 |
Aug 15 04:37:48 PM PDT 24 |
187807064 ps |
| T883 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.1473273323 |
|
|
Aug 15 04:37:42 PM PDT 24 |
Aug 15 04:37:45 PM PDT 24 |
312705553 ps |
| T884 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3219691428 |
|
|
Aug 15 04:38:51 PM PDT 24 |
Aug 15 04:44:20 PM PDT 24 |
60838476446 ps |
| T885 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.2151699880 |
|
|
Aug 15 04:38:29 PM PDT 24 |
Aug 15 04:48:17 PM PDT 24 |
17815697633 ps |
| T886 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.3547245698 |
|
|
Aug 15 04:39:17 PM PDT 24 |
Aug 15 04:42:45 PM PDT 24 |
2118578691 ps |
| T887 |
/workspace/coverage/default/41.sram_ctrl_smoke.1982081005 |
|
|
Aug 15 04:38:22 PM PDT 24 |
Aug 15 04:40:03 PM PDT 24 |
144384979 ps |
| T888 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3738002162 |
|
|
Aug 15 04:38:59 PM PDT 24 |
Aug 15 04:45:52 PM PDT 24 |
2319288202 ps |
| T889 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.1266280059 |
|
|
Aug 15 04:37:41 PM PDT 24 |
Aug 15 04:37:42 PM PDT 24 |
26643183 ps |
| T890 |
/workspace/coverage/default/16.sram_ctrl_smoke.1744788174 |
|
|
Aug 15 04:36:43 PM PDT 24 |
Aug 15 04:36:52 PM PDT 24 |
797920102 ps |
| T891 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.722068853 |
|
|
Aug 15 04:37:04 PM PDT 24 |
Aug 15 04:41:36 PM PDT 24 |
10978776418 ps |
| T892 |
/workspace/coverage/default/0.sram_ctrl_regwen.2053388511 |
|
|
Aug 15 04:35:49 PM PDT 24 |
Aug 15 04:53:59 PM PDT 24 |
13369376197 ps |
| T893 |
/workspace/coverage/default/23.sram_ctrl_access_during_key_req.2489898815 |
|
|
Aug 15 04:37:02 PM PDT 24 |
Aug 15 04:38:47 PM PDT 24 |
857727058 ps |
| T894 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.4124955927 |
|
|
Aug 15 04:38:00 PM PDT 24 |
Aug 15 04:38:08 PM PDT 24 |
656014631 ps |
| T895 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.3634062203 |
|
|
Aug 15 04:38:37 PM PDT 24 |
Aug 15 04:38:38 PM PDT 24 |
279480992 ps |
| T896 |
/workspace/coverage/default/17.sram_ctrl_mem_partial_access.3912072906 |
|
|
Aug 15 04:36:51 PM PDT 24 |
Aug 15 04:36:55 PM PDT 24 |
88391834 ps |
| T897 |
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.1033009697 |
|
|
Aug 15 04:36:00 PM PDT 24 |
Aug 15 04:36:03 PM PDT 24 |
75711848 ps |
| T898 |
/workspace/coverage/default/15.sram_ctrl_stress_all.1925538648 |
|
|
Aug 15 04:36:38 PM PDT 24 |
Aug 15 04:56:30 PM PDT 24 |
5280254291 ps |
| T899 |
/workspace/coverage/default/0.sram_ctrl_stress_all.3990757805 |
|
|
Aug 15 04:35:50 PM PDT 24 |
Aug 15 05:08:30 PM PDT 24 |
20650313554 ps |
| T900 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.1445340947 |
|
|
Aug 15 04:37:27 PM PDT 24 |
Aug 15 04:53:43 PM PDT 24 |
3005262246 ps |
| T901 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.2651003105 |
|
|
Aug 15 04:36:09 PM PDT 24 |
Aug 15 04:36:15 PM PDT 24 |
950123241 ps |
| T902 |
/workspace/coverage/default/47.sram_ctrl_regwen.978796854 |
|
|
Aug 15 04:38:59 PM PDT 24 |
Aug 15 04:52:00 PM PDT 24 |
49064125925 ps |
| T903 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.134452115 |
|
|
Aug 15 04:39:09 PM PDT 24 |
Aug 15 04:48:43 PM PDT 24 |
23118873733 ps |
| T116 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1408059289 |
|
|
Aug 15 04:36:34 PM PDT 24 |
Aug 15 04:38:38 PM PDT 24 |
14844279399 ps |
| T904 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.2666806370 |
|
|
Aug 15 04:36:23 PM PDT 24 |
Aug 15 04:39:45 PM PDT 24 |
2898590362 ps |
| T905 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2618098623 |
|
|
Aug 15 04:36:25 PM PDT 24 |
Aug 15 04:38:21 PM PDT 24 |
144546665 ps |
| T906 |
/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.4242986694 |
|
|
Aug 15 04:36:36 PM PDT 24 |
Aug 15 04:39:23 PM PDT 24 |
1642425308 ps |
| T907 |
/workspace/coverage/default/6.sram_ctrl_executable.1452751603 |
|
|
Aug 15 04:36:01 PM PDT 24 |
Aug 15 04:41:31 PM PDT 24 |
8603525024 ps |
| T908 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.4285493623 |
|
|
Aug 15 04:37:01 PM PDT 24 |
Aug 15 04:43:43 PM PDT 24 |
5684780186 ps |
| T909 |
/workspace/coverage/default/34.sram_ctrl_stress_all.750392747 |
|
|
Aug 15 04:37:40 PM PDT 24 |
Aug 15 05:56:15 PM PDT 24 |
24576222158 ps |
| T910 |
/workspace/coverage/default/46.sram_ctrl_executable.1604655666 |
|
|
Aug 15 04:38:54 PM PDT 24 |
Aug 15 04:44:20 PM PDT 24 |
1437713624 ps |
| T911 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.3980640003 |
|
|
Aug 15 04:36:03 PM PDT 24 |
Aug 15 04:36:04 PM PDT 24 |
27636753 ps |
| T912 |
/workspace/coverage/default/29.sram_ctrl_executable.1368027996 |
|
|
Aug 15 04:37:30 PM PDT 24 |
Aug 15 04:59:25 PM PDT 24 |
5193716248 ps |
| T913 |
/workspace/coverage/default/15.sram_ctrl_partial_access.3763659515 |
|
|
Aug 15 04:36:33 PM PDT 24 |
Aug 15 04:37:53 PM PDT 24 |
1023085461 ps |
| T914 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.1647289069 |
|
|
Aug 15 04:36:28 PM PDT 24 |
Aug 15 04:42:23 PM PDT 24 |
19904162195 ps |
| T915 |
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.2336087967 |
|
|
Aug 15 04:37:01 PM PDT 24 |
Aug 15 04:38:17 PM PDT 24 |
13590260466 ps |
| T916 |
/workspace/coverage/default/3.sram_ctrl_alert_test.69454105 |
|
|
Aug 15 04:36:03 PM PDT 24 |
Aug 15 04:36:03 PM PDT 24 |
15277086 ps |
| T917 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.400562105 |
|
|
Aug 15 04:36:10 PM PDT 24 |
Aug 15 04:36:13 PM PDT 24 |
519754166 ps |
| T918 |
/workspace/coverage/default/13.sram_ctrl_executable.2793501917 |
|
|
Aug 15 04:36:53 PM PDT 24 |
Aug 15 04:46:21 PM PDT 24 |
49174055698 ps |
| T919 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.2495413821 |
|
|
Aug 15 04:37:17 PM PDT 24 |
Aug 15 05:05:45 PM PDT 24 |
103882551113 ps |
| T920 |
/workspace/coverage/default/5.sram_ctrl_executable.2521809086 |
|
|
Aug 15 04:36:10 PM PDT 24 |
Aug 15 04:58:31 PM PDT 24 |
18495644213 ps |
| T921 |
/workspace/coverage/default/14.sram_ctrl_partial_access.104457078 |
|
|
Aug 15 04:36:45 PM PDT 24 |
Aug 15 04:36:57 PM PDT 24 |
2581700489 ps |
| T922 |
/workspace/coverage/default/42.sram_ctrl_stress_all.3267000136 |
|
|
Aug 15 04:38:31 PM PDT 24 |
Aug 15 04:56:08 PM PDT 24 |
139334980752 ps |
| T923 |
/workspace/coverage/default/49.sram_ctrl_partial_access.1895744762 |
|
|
Aug 15 04:39:13 PM PDT 24 |
Aug 15 04:39:46 PM PDT 24 |
1451790710 ps |
| T924 |
/workspace/coverage/default/26.sram_ctrl_alert_test.4187220503 |
|
|
Aug 15 04:37:15 PM PDT 24 |
Aug 15 04:37:16 PM PDT 24 |
13479158 ps |
| T925 |
/workspace/coverage/default/40.sram_ctrl_smoke.1542342354 |
|
|
Aug 15 04:38:15 PM PDT 24 |
Aug 15 04:38:29 PM PDT 24 |
3423154999 ps |
| T926 |
/workspace/coverage/default/7.sram_ctrl_bijection.3292960039 |
|
|
Aug 15 04:36:14 PM PDT 24 |
Aug 15 04:36:35 PM PDT 24 |
4069054665 ps |
| T927 |
/workspace/coverage/default/5.sram_ctrl_regwen.4181309750 |
|
|
Aug 15 04:36:10 PM PDT 24 |
Aug 15 04:49:04 PM PDT 24 |
3750752200 ps |
| T928 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.2614432590 |
|
|
Aug 15 04:36:34 PM PDT 24 |
Aug 15 04:36:35 PM PDT 24 |
29659751 ps |
| T929 |
/workspace/coverage/default/24.sram_ctrl_smoke.998192605 |
|
|
Aug 15 04:37:08 PM PDT 24 |
Aug 15 04:37:38 PM PDT 24 |
2154560128 ps |
| T930 |
/workspace/coverage/default/11.sram_ctrl_regwen.86590931 |
|
|
Aug 15 04:36:18 PM PDT 24 |
Aug 15 04:40:47 PM PDT 24 |
29741659133 ps |
| T931 |
/workspace/coverage/default/24.sram_ctrl_alert_test.1030444807 |
|
|
Aug 15 04:36:59 PM PDT 24 |
Aug 15 04:37:00 PM PDT 24 |
46694322 ps |
| T932 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.969849084 |
|
|
Aug 15 04:36:59 PM PDT 24 |
Aug 15 04:37:12 PM PDT 24 |
132075190 ps |
| T933 |
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.2068007702 |
|
|
Aug 15 04:39:01 PM PDT 24 |
Aug 15 04:39:05 PM PDT 24 |
1003250096 ps |
| T934 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1734429226 |
|
|
Aug 15 04:34:31 PM PDT 24 |
Aug 15 04:34:32 PM PDT 24 |
49019900 ps |
| T935 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2188729453 |
|
|
Aug 15 04:34:49 PM PDT 24 |
Aug 15 04:34:51 PM PDT 24 |
28160609 ps |
| T65 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2723034318 |
|
|
Aug 15 04:34:34 PM PDT 24 |
Aug 15 04:34:35 PM PDT 24 |
165898690 ps |
| T66 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3875177591 |
|
|
Aug 15 04:34:30 PM PDT 24 |
Aug 15 04:34:31 PM PDT 24 |
116832236 ps |
| T117 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1592452176 |
|
|
Aug 15 04:34:28 PM PDT 24 |
Aug 15 04:34:29 PM PDT 24 |
97450932 ps |
| T67 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1731126448 |
|
|
Aug 15 04:34:27 PM PDT 24 |
Aug 15 04:34:28 PM PDT 24 |
25181708 ps |
| T936 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3283594737 |
|
|
Aug 15 04:34:39 PM PDT 24 |
Aug 15 04:34:41 PM PDT 24 |
37523179 ps |
| T75 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.824659572 |
|
|
Aug 15 04:34:44 PM PDT 24 |
Aug 15 04:34:46 PM PDT 24 |
902090549 ps |
| T107 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.778155762 |
|
|
Aug 15 04:34:29 PM PDT 24 |
Aug 15 04:34:29 PM PDT 24 |
64295297 ps |
| T62 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.676667488 |
|
|
Aug 15 04:34:44 PM PDT 24 |
Aug 15 04:34:47 PM PDT 24 |
2768977733 ps |
| T63 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1374992885 |
|
|
Aug 15 04:34:30 PM PDT 24 |
Aug 15 04:34:32 PM PDT 24 |
80250239 ps |
| T108 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.910648914 |
|
|
Aug 15 04:34:26 PM PDT 24 |
Aug 15 04:34:27 PM PDT 24 |
28346562 ps |
| T937 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1659619577 |
|
|
Aug 15 04:34:44 PM PDT 24 |
Aug 15 04:34:46 PM PDT 24 |
37040959 ps |
| T76 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3849547616 |
|
|
Aug 15 04:34:28 PM PDT 24 |
Aug 15 04:34:28 PM PDT 24 |
19602832 ps |
| T64 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.907104379 |
|
|
Aug 15 04:34:44 PM PDT 24 |
Aug 15 04:34:45 PM PDT 24 |
356118651 ps |
| T109 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3734208420 |
|
|
Aug 15 04:34:34 PM PDT 24 |
Aug 15 04:34:35 PM PDT 24 |
37241597 ps |
| T135 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3439935258 |
|
|
Aug 15 04:34:36 PM PDT 24 |
Aug 15 04:34:38 PM PDT 24 |
104187178 ps |
| T938 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3415006951 |
|
|
Aug 15 04:34:25 PM PDT 24 |
Aug 15 04:34:27 PM PDT 24 |
110276498 ps |
| T110 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.4180393270 |
|
|
Aug 15 04:34:30 PM PDT 24 |
Aug 15 04:34:31 PM PDT 24 |
47716055 ps |
| T128 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2261251640 |
|
|
Aug 15 04:34:39 PM PDT 24 |
Aug 15 04:34:41 PM PDT 24 |
102146489 ps |
| T77 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.942873494 |
|
|
Aug 15 04:34:33 PM PDT 24 |
Aug 15 04:34:37 PM PDT 24 |
847753368 ps |
| T939 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3822166725 |
|
|
Aug 15 04:34:45 PM PDT 24 |
Aug 15 04:34:48 PM PDT 24 |
50002729 ps |
| T940 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3431890463 |
|
|
Aug 15 04:34:31 PM PDT 24 |
Aug 15 04:34:32 PM PDT 24 |
42102395 ps |
| T941 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3396034828 |
|
|
Aug 15 04:34:30 PM PDT 24 |
Aug 15 04:34:31 PM PDT 24 |
246540044 ps |
| T78 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2884108890 |
|
|
Aug 15 04:34:30 PM PDT 24 |
Aug 15 04:34:31 PM PDT 24 |
43519612 ps |
| T124 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2342577016 |
|
|
Aug 15 04:34:26 PM PDT 24 |
Aug 15 04:34:29 PM PDT 24 |
76851864 ps |
| T129 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.956920199 |
|
|
Aug 15 04:34:46 PM PDT 24 |
Aug 15 04:34:49 PM PDT 24 |
1106920064 ps |
| T136 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3113821972 |
|
|
Aug 15 04:34:34 PM PDT 24 |
Aug 15 04:34:37 PM PDT 24 |
190092294 ps |
| T79 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.544141297 |
|
|
Aug 15 04:34:35 PM PDT 24 |
Aug 15 04:34:36 PM PDT 24 |
97709962 ps |
| T125 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3422609036 |
|
|
Aug 15 04:34:26 PM PDT 24 |
Aug 15 04:34:27 PM PDT 24 |
125709454 ps |
| T80 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3158354918 |
|
|
Aug 15 04:34:33 PM PDT 24 |
Aug 15 04:34:36 PM PDT 24 |
403380190 ps |
| T100 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.558897095 |
|
|
Aug 15 04:34:39 PM PDT 24 |
Aug 15 04:34:40 PM PDT 24 |
26914422 ps |
| T81 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3716763192 |
|
|
Aug 15 04:34:34 PM PDT 24 |
Aug 15 04:34:38 PM PDT 24 |
457683348 ps |
| T82 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1230698029 |
|
|
Aug 15 04:34:32 PM PDT 24 |
Aug 15 04:34:34 PM PDT 24 |
279467852 ps |
| T83 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.4144791621 |
|
|
Aug 15 04:34:25 PM PDT 24 |
Aug 15 04:34:26 PM PDT 24 |
16155616 ps |
| T942 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1225661931 |
|
|
Aug 15 04:34:40 PM PDT 24 |
Aug 15 04:34:41 PM PDT 24 |
35993405 ps |
| T85 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1125629524 |
|
|
Aug 15 04:34:39 PM PDT 24 |
Aug 15 04:34:42 PM PDT 24 |
227477977 ps |
| T86 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1619588798 |
|
|
Aug 15 04:34:31 PM PDT 24 |
Aug 15 04:34:35 PM PDT 24 |
1190763430 ps |
| T943 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.506715228 |
|
|
Aug 15 04:34:28 PM PDT 24 |
Aug 15 04:34:30 PM PDT 24 |
26800610 ps |
| T944 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2904941295 |
|
|
Aug 15 04:34:25 PM PDT 24 |
Aug 15 04:34:26 PM PDT 24 |
138986733 ps |
| T945 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1454896196 |
|
|
Aug 15 04:34:46 PM PDT 24 |
Aug 15 04:34:46 PM PDT 24 |
41326798 ps |
| T87 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1549590786 |
|
|
Aug 15 04:34:46 PM PDT 24 |
Aug 15 04:34:47 PM PDT 24 |
23079835 ps |
| T946 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3470703704 |
|
|
Aug 15 04:34:39 PM PDT 24 |
Aug 15 04:34:43 PM PDT 24 |
36826227 ps |
| T947 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4055567093 |
|
|
Aug 15 04:34:44 PM PDT 24 |
Aug 15 04:34:45 PM PDT 24 |
23941177 ps |
| T126 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3665106719 |
|
|
Aug 15 04:34:26 PM PDT 24 |
Aug 15 04:34:28 PM PDT 24 |
179501244 ps |
| T130 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3106892873 |
|
|
Aug 15 04:34:45 PM PDT 24 |
Aug 15 04:34:46 PM PDT 24 |
79694391 ps |
| T948 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3206299496 |
|
|
Aug 15 04:34:45 PM PDT 24 |
Aug 15 04:34:46 PM PDT 24 |
19921529 ps |
| T949 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3285229642 |
|
|
Aug 15 04:34:26 PM PDT 24 |
Aug 15 04:34:27 PM PDT 24 |
16209470 ps |
| T950 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.243144750 |
|
|
Aug 15 04:34:48 PM PDT 24 |
Aug 15 04:34:53 PM PDT 24 |
361519323 ps |
| T951 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2428001136 |
|
|
Aug 15 04:34:27 PM PDT 24 |
Aug 15 04:34:28 PM PDT 24 |
35922259 ps |
| T88 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1997006505 |
|
|
Aug 15 04:34:46 PM PDT 24 |
Aug 15 04:34:49 PM PDT 24 |
2552184644 ps |
| T952 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1542223546 |
|
|
Aug 15 04:34:46 PM PDT 24 |
Aug 15 04:34:49 PM PDT 24 |
420500363 ps |
| T953 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3113626001 |
|
|
Aug 15 04:34:48 PM PDT 24 |
Aug 15 04:34:51 PM PDT 24 |
47415980 ps |
| T954 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.331510422 |
|
|
Aug 15 04:34:43 PM PDT 24 |
Aug 15 04:34:49 PM PDT 24 |
296185046 ps |
| T94 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3835920898 |
|
|
Aug 15 04:34:44 PM PDT 24 |
Aug 15 04:34:47 PM PDT 24 |
307723487 ps |
| T955 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.934981711 |
|
|
Aug 15 04:34:46 PM PDT 24 |
Aug 15 04:34:50 PM PDT 24 |
202650350 ps |
| T956 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2703563269 |
|
|
Aug 15 04:34:26 PM PDT 24 |
Aug 15 04:34:28 PM PDT 24 |
267539434 ps |
| T957 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.4071472732 |
|
|
Aug 15 04:34:38 PM PDT 24 |
Aug 15 04:34:50 PM PDT 24 |
128412479 ps |
| T95 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1324180984 |
|
|
Aug 15 04:34:25 PM PDT 24 |
Aug 15 04:34:26 PM PDT 24 |
24994696 ps |
| T958 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1274780178 |
|
|
Aug 15 04:34:20 PM PDT 24 |
Aug 15 04:34:25 PM PDT 24 |
482218459 ps |
| T132 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.709036571 |
|
|
Aug 15 04:34:32 PM PDT 24 |
Aug 15 04:34:35 PM PDT 24 |
525579465 ps |
| T959 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2735898992 |
|
|
Aug 15 04:34:45 PM PDT 24 |
Aug 15 04:34:46 PM PDT 24 |
15413831 ps |
| T960 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.466285061 |
|
|
Aug 15 04:34:30 PM PDT 24 |
Aug 15 04:34:33 PM PDT 24 |
681993664 ps |
| T961 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1432304239 |
|
|
Aug 15 04:34:49 PM PDT 24 |
Aug 15 04:34:50 PM PDT 24 |
11422726 ps |
| T96 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2717613776 |
|
|
Aug 15 04:34:46 PM PDT 24 |
Aug 15 04:34:48 PM PDT 24 |
3990169997 ps |
| T127 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.812378025 |
|
|
Aug 15 04:34:35 PM PDT 24 |
Aug 15 04:34:38 PM PDT 24 |
65965341 ps |
| T962 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.472835438 |
|
|
Aug 15 04:34:41 PM PDT 24 |
Aug 15 04:34:42 PM PDT 24 |
17615484 ps |
| T963 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3206085288 |
|
|
Aug 15 04:34:33 PM PDT 24 |
Aug 15 04:34:36 PM PDT 24 |
286249448 ps |
| T964 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.202547152 |
|
|
Aug 15 04:34:49 PM PDT 24 |
Aug 15 04:34:51 PM PDT 24 |
62857514 ps |
| T965 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3498935475 |
|
|
Aug 15 04:34:35 PM PDT 24 |
Aug 15 04:34:36 PM PDT 24 |
15410916 ps |
| T966 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3138283411 |
|
|
Aug 15 04:34:24 PM PDT 24 |
Aug 15 04:34:25 PM PDT 24 |
16783526 ps |
| T967 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.4285137331 |
|
|
Aug 15 04:34:31 PM PDT 24 |
Aug 15 04:34:35 PM PDT 24 |
47654239 ps |
| T968 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3986800049 |
|
|
Aug 15 04:34:33 PM PDT 24 |
Aug 15 04:34:34 PM PDT 24 |
139345662 ps |
| T969 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3289969989 |
|
|
Aug 15 04:34:44 PM PDT 24 |
Aug 15 04:34:47 PM PDT 24 |
829864243 ps |
| T970 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1262153675 |
|
|
Aug 15 04:34:44 PM PDT 24 |
Aug 15 04:34:47 PM PDT 24 |
54435568 ps |
| T971 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.883099705 |
|
|
Aug 15 04:34:39 PM PDT 24 |
Aug 15 04:34:42 PM PDT 24 |
126301993 ps |
| T97 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2658831238 |
|
|
Aug 15 04:34:39 PM PDT 24 |
Aug 15 04:34:43 PM PDT 24 |
865142233 ps |
| T972 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2685460261 |
|
|
Aug 15 04:34:46 PM PDT 24 |
Aug 15 04:34:47 PM PDT 24 |
22035665 ps |
| T973 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3557075062 |
|
|
Aug 15 04:34:26 PM PDT 24 |
Aug 15 04:34:30 PM PDT 24 |
1530241369 ps |
| T974 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.197532114 |
|
|
Aug 15 04:34:25 PM PDT 24 |
Aug 15 04:34:27 PM PDT 24 |
56109789 ps |
| T975 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2301469185 |
|
|
Aug 15 04:34:41 PM PDT 24 |
Aug 15 04:34:43 PM PDT 24 |
145761215 ps |
| T976 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2172820589 |
|
|
Aug 15 04:34:48 PM PDT 24 |
Aug 15 04:34:49 PM PDT 24 |
24785189 ps |
| T977 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.377032073 |
|
|
Aug 15 04:34:32 PM PDT 24 |
Aug 15 04:34:34 PM PDT 24 |
33601800 ps |
| T978 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.771818430 |
|
|
Aug 15 04:34:27 PM PDT 24 |
Aug 15 04:34:28 PM PDT 24 |
32996321 ps |
| T979 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1805029357 |
|
|
Aug 15 04:34:25 PM PDT 24 |
Aug 15 04:34:27 PM PDT 24 |
90973505 ps |
| T980 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.178420921 |
|
|
Aug 15 04:34:41 PM PDT 24 |
Aug 15 04:34:42 PM PDT 24 |
33954837 ps |
| T98 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1252631006 |
|
|
Aug 15 04:34:31 PM PDT 24 |
Aug 15 04:34:32 PM PDT 24 |
43770047 ps |
| T981 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1795752754 |
|
|
Aug 15 04:34:30 PM PDT 24 |
Aug 15 04:34:32 PM PDT 24 |
1601814184 ps |
| T982 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2994893509 |
|
|
Aug 15 04:34:34 PM PDT 24 |
Aug 15 04:34:35 PM PDT 24 |
37825113 ps |
| T983 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3177994114 |
|
|
Aug 15 04:34:34 PM PDT 24 |
Aug 15 04:34:35 PM PDT 24 |
14906609 ps |
| T984 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3265981845 |
|
|
Aug 15 04:34:33 PM PDT 24 |
Aug 15 04:34:34 PM PDT 24 |
18309836 ps |
| T985 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.373449387 |
|
|
Aug 15 04:34:25 PM PDT 24 |
Aug 15 04:34:26 PM PDT 24 |
39801477 ps |
| T99 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3983495654 |
|
|
Aug 15 04:34:27 PM PDT 24 |
Aug 15 04:34:29 PM PDT 24 |
422234959 ps |
| T986 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3381431898 |
|
|
Aug 15 04:34:41 PM PDT 24 |
Aug 15 04:34:44 PM PDT 24 |
46460890 ps |
| T987 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1839518848 |
|
|
Aug 15 04:34:26 PM PDT 24 |
Aug 15 04:34:27 PM PDT 24 |
48446520 ps |
| T988 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3988276310 |
|
|
Aug 15 04:34:40 PM PDT 24 |
Aug 15 04:34:42 PM PDT 24 |
59425919 ps |
| T989 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2465050132 |
|
|
Aug 15 04:34:34 PM PDT 24 |
Aug 15 04:34:36 PM PDT 24 |
229526063 ps |
| T990 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2551874399 |
|
|
Aug 15 04:34:44 PM PDT 24 |
Aug 15 04:34:45 PM PDT 24 |
50187310 ps |
| T991 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1046475271 |
|
|
Aug 15 04:34:45 PM PDT 24 |
Aug 15 04:34:49 PM PDT 24 |
143936065 ps |
| T992 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.488212658 |
|
|
Aug 15 04:34:25 PM PDT 24 |
Aug 15 04:34:26 PM PDT 24 |
10937997 ps |
| T993 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.344984067 |
|
|
Aug 15 04:34:50 PM PDT 24 |
Aug 15 04:34:51 PM PDT 24 |
119314677 ps |
| T994 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2312030921 |
|
|
Aug 15 04:34:33 PM PDT 24 |
Aug 15 04:34:37 PM PDT 24 |
1469318365 ps |
| T995 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.4005294649 |
|
|
Aug 15 04:34:33 PM PDT 24 |
Aug 15 04:34:36 PM PDT 24 |
51328980 ps |
| T996 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.476208335 |
|
|
Aug 15 04:34:45 PM PDT 24 |
Aug 15 04:34:46 PM PDT 24 |
24011216 ps |
| T997 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3396792313 |
|
|
Aug 15 04:34:48 PM PDT 24 |
Aug 15 04:34:49 PM PDT 24 |
41641161 ps |
| T998 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3166448304 |
|
|
Aug 15 04:34:25 PM PDT 24 |
Aug 15 04:34:30 PM PDT 24 |
500158543 ps |
| T133 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3471317145 |
|
|
Aug 15 04:34:29 PM PDT 24 |
Aug 15 04:34:30 PM PDT 24 |
181853790 ps |
| T999 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1958218348 |
|
|
Aug 15 04:34:28 PM PDT 24 |
Aug 15 04:34:30 PM PDT 24 |
525932114 ps |
| T1000 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.184575455 |
|
|
Aug 15 04:34:34 PM PDT 24 |
Aug 15 04:34:34 PM PDT 24 |
21477738 ps |
| T1001 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1059680343 |
|
|
Aug 15 04:34:34 PM PDT 24 |
Aug 15 04:34:36 PM PDT 24 |
43851261 ps |
| T1002 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2251120501 |
|
|
Aug 15 04:34:35 PM PDT 24 |
Aug 15 04:34:36 PM PDT 24 |
52372747 ps |
| T1003 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1225340897 |
|
|
Aug 15 04:34:40 PM PDT 24 |
Aug 15 04:34:42 PM PDT 24 |
112926268 ps |
| T1004 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.646847990 |
|
|
Aug 15 04:34:45 PM PDT 24 |
Aug 15 04:34:48 PM PDT 24 |
48230620 ps |
| T138 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.282033805 |
|
|
Aug 15 04:34:41 PM PDT 24 |
Aug 15 04:34:43 PM PDT 24 |
921372974 ps |