Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	146897708	1			T1	48430		T2	48952		T3	385512
instr_valid_dis	112173630	1			T1	48430		T2	48952		T3	110834
instr_en	27487627	1			T3	197502		T13	178878		T27	6626

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10708155	1			T3	168504		T19	57760		T55	735064
sram_ifetch_valid_disable	113768323	1			T1	48430		T2	48952		T3	38832
sram_ifetch_enable	22421230	1			T3	178176		T13	161314		T19	49808

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	146897708	1			T1	48430		T2	48952		T3	385512
hw_debug_en_valid_off	112142285	1			T1	48430		T2	48952		T3	155372
hw_debug_en_on	22061623	1			T3	209698		T13	99572		T19	53858

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	113768323	1			T1	48430		T2	48952		T3	38832
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	99774242	1			T1	48430		T2	48952		T3	18476
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	10763967	1			T3	356		T13	46520		T55	152764
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3899111	1			T3	63748		T55	188432		T131	23974
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1329238	1			T55	134338		T22	20000		T61	63856
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1872700	1			T3	63748		T55	54094		T131	23974
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4496028	1			T3	104756		T19	5430		T55	427700
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2116484	1			T3	77774		T55	135282		T47	24146
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1922906	1			T3	26982		T55	292418		T138	1282
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9323413	1			T3	18390		T13	46520		T19	19118
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3868311	1			T3	18390		T19	19118		T55	269110
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4064718	1			T13	46520		T55	39938		T47	38740

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	11910808	1			T3	106416		T13	132358		T27	6626
lc_exec_en	8242182	1			T3	86552		T13	53052		T19	29310
valid_exec_dis	107611542	1			T1	48430		T2	48952		T3	14584
invalid_exec_dis	33129385	1			T3	346680		T13	161314		T19	107568