| T798 |
/workspace/coverage/default/26.sram_ctrl_max_throughput.2124314595 |
|
|
Aug 16 04:57:34 PM PDT 24 |
Aug 16 04:58:43 PM PDT 24 |
117837596 ps |
| T799 |
/workspace/coverage/default/3.sram_ctrl_stress_all.552028645 |
|
|
Aug 16 04:56:37 PM PDT 24 |
Aug 16 05:35:20 PM PDT 24 |
136742885251 ps |
| T800 |
/workspace/coverage/default/31.sram_ctrl_partial_access.368418963 |
|
|
Aug 16 04:57:56 PM PDT 24 |
Aug 16 04:58:00 PM PDT 24 |
201548239 ps |
| T801 |
/workspace/coverage/default/19.sram_ctrl_executable.548101181 |
|
|
Aug 16 04:57:13 PM PDT 24 |
Aug 16 05:11:31 PM PDT 24 |
10452225201 ps |
| T802 |
/workspace/coverage/default/5.sram_ctrl_regwen.704978940 |
|
|
Aug 16 04:56:32 PM PDT 24 |
Aug 16 05:05:52 PM PDT 24 |
75910307122 ps |
| T803 |
/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.2110741849 |
|
|
Aug 16 04:58:29 PM PDT 24 |
Aug 16 05:02:22 PM PDT 24 |
6245188430 ps |
| T804 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.2607646639 |
|
|
Aug 16 04:57:06 PM PDT 24 |
Aug 16 05:00:50 PM PDT 24 |
305724735 ps |
| T805 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.566887430 |
|
|
Aug 16 04:57:07 PM PDT 24 |
Aug 16 04:58:11 PM PDT 24 |
463441129 ps |
| T806 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.1698498663 |
|
|
Aug 16 04:57:02 PM PDT 24 |
Aug 16 04:57:03 PM PDT 24 |
114081426 ps |
| T807 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.1067298092 |
|
|
Aug 16 04:56:40 PM PDT 24 |
Aug 16 04:56:41 PM PDT 24 |
30477572 ps |
| T808 |
/workspace/coverage/default/12.sram_ctrl_bijection.1461092514 |
|
|
Aug 16 04:56:53 PM PDT 24 |
Aug 16 04:57:45 PM PDT 24 |
31215062414 ps |
| T809 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.272162736 |
|
|
Aug 16 04:56:35 PM PDT 24 |
Aug 16 05:00:42 PM PDT 24 |
13930254778 ps |
| T810 |
/workspace/coverage/default/23.sram_ctrl_executable.2984545981 |
|
|
Aug 16 04:57:26 PM PDT 24 |
Aug 16 05:10:01 PM PDT 24 |
14094743056 ps |
| T78 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.955196161 |
|
|
Aug 16 04:56:39 PM PDT 24 |
Aug 16 04:56:43 PM PDT 24 |
180322850 ps |
| T811 |
/workspace/coverage/default/29.sram_ctrl_access_during_key_req.2681650842 |
|
|
Aug 16 04:57:54 PM PDT 24 |
Aug 16 05:14:35 PM PDT 24 |
3024816389 ps |
| T812 |
/workspace/coverage/default/3.sram_ctrl_mem_walk.1389516335 |
|
|
Aug 16 04:56:37 PM PDT 24 |
Aug 16 04:56:49 PM PDT 24 |
442501370 ps |
| T813 |
/workspace/coverage/default/44.sram_ctrl_bijection.1398998187 |
|
|
Aug 16 04:59:05 PM PDT 24 |
Aug 16 05:00:27 PM PDT 24 |
3619217301 ps |
| T814 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.3305021080 |
|
|
Aug 16 04:56:54 PM PDT 24 |
Aug 16 04:57:53 PM PDT 24 |
3572283348 ps |
| T815 |
/workspace/coverage/default/4.sram_ctrl_smoke.4046814357 |
|
|
Aug 16 04:56:36 PM PDT 24 |
Aug 16 04:56:39 PM PDT 24 |
160375585 ps |
| T816 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.1936969299 |
|
|
Aug 16 04:58:04 PM PDT 24 |
Aug 16 05:23:50 PM PDT 24 |
8446063798 ps |
| T817 |
/workspace/coverage/default/32.sram_ctrl_max_throughput.3738638761 |
|
|
Aug 16 04:58:02 PM PDT 24 |
Aug 16 04:58:47 PM PDT 24 |
103838576 ps |
| T818 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1818739457 |
|
|
Aug 16 04:59:36 PM PDT 24 |
Aug 16 05:00:02 PM PDT 24 |
124939189 ps |
| T819 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.2759677980 |
|
|
Aug 16 04:56:44 PM PDT 24 |
Aug 16 04:56:44 PM PDT 24 |
86529150 ps |
| T820 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.3230756747 |
|
|
Aug 16 04:59:46 PM PDT 24 |
Aug 16 04:59:48 PM PDT 24 |
182012603 ps |
| T821 |
/workspace/coverage/default/1.sram_ctrl_stress_all.3339868970 |
|
|
Aug 16 04:56:20 PM PDT 24 |
Aug 16 05:45:04 PM PDT 24 |
39654364660 ps |
| T822 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.117312093 |
|
|
Aug 16 04:57:13 PM PDT 24 |
Aug 16 04:57:24 PM PDT 24 |
1286869594 ps |
| T823 |
/workspace/coverage/default/22.sram_ctrl_bijection.1506706707 |
|
|
Aug 16 04:57:20 PM PDT 24 |
Aug 16 04:57:55 PM PDT 24 |
2332534320 ps |
| T824 |
/workspace/coverage/default/46.sram_ctrl_regwen.2252088832 |
|
|
Aug 16 04:59:25 PM PDT 24 |
Aug 16 05:01:47 PM PDT 24 |
40632622159 ps |
| T825 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1537997692 |
|
|
Aug 16 04:56:43 PM PDT 24 |
Aug 16 04:57:16 PM PDT 24 |
1166809356 ps |
| T826 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.3436089415 |
|
|
Aug 16 04:59:04 PM PDT 24 |
Aug 16 04:59:10 PM PDT 24 |
2166498777 ps |
| T827 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3038680269 |
|
|
Aug 16 04:59:29 PM PDT 24 |
Aug 16 05:06:12 PM PDT 24 |
15473201966 ps |
| T828 |
/workspace/coverage/default/0.sram_ctrl_bijection.2802961053 |
|
|
Aug 16 04:56:09 PM PDT 24 |
Aug 16 04:57:09 PM PDT 24 |
6991145947 ps |
| T829 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.3349692457 |
|
|
Aug 16 04:58:33 PM PDT 24 |
Aug 16 04:59:07 PM PDT 24 |
775056401 ps |
| T830 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.968041338 |
|
|
Aug 16 04:58:12 PM PDT 24 |
Aug 16 04:59:44 PM PDT 24 |
116350414 ps |
| T831 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.2082637442 |
|
|
Aug 16 04:56:53 PM PDT 24 |
Aug 16 04:57:04 PM PDT 24 |
1850653280 ps |
| T832 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.1782879865 |
|
|
Aug 16 04:59:30 PM PDT 24 |
Aug 16 04:59:33 PM PDT 24 |
58305204 ps |
| T833 |
/workspace/coverage/default/14.sram_ctrl_partial_access.3335964790 |
|
|
Aug 16 04:56:47 PM PDT 24 |
Aug 16 04:57:03 PM PDT 24 |
319706338 ps |
| T834 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.1297131355 |
|
|
Aug 16 04:57:22 PM PDT 24 |
Aug 16 04:57:28 PM PDT 24 |
497408000 ps |
| T835 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.1575719811 |
|
|
Aug 16 04:56:37 PM PDT 24 |
Aug 16 05:05:05 PM PDT 24 |
10394646281 ps |
| T836 |
/workspace/coverage/default/2.sram_ctrl_stress_all.3891332766 |
|
|
Aug 16 04:56:27 PM PDT 24 |
Aug 16 05:10:05 PM PDT 24 |
13715992180 ps |
| T837 |
/workspace/coverage/default/49.sram_ctrl_partial_access.3452099200 |
|
|
Aug 16 04:59:43 PM PDT 24 |
Aug 16 05:01:16 PM PDT 24 |
3074303250 ps |
| T838 |
/workspace/coverage/default/6.sram_ctrl_bijection.905870345 |
|
|
Aug 16 04:56:37 PM PDT 24 |
Aug 16 04:57:55 PM PDT 24 |
3666711995 ps |
| T103 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.801936747 |
|
|
Aug 16 04:59:18 PM PDT 24 |
Aug 16 04:59:24 PM PDT 24 |
352636312 ps |
| T839 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.1791917345 |
|
|
Aug 16 04:56:37 PM PDT 24 |
Aug 16 04:56:42 PM PDT 24 |
1188643217 ps |
| T840 |
/workspace/coverage/default/44.sram_ctrl_alert_test.3746001100 |
|
|
Aug 16 04:59:12 PM PDT 24 |
Aug 16 04:59:13 PM PDT 24 |
47704326 ps |
| T841 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.1207518425 |
|
|
Aug 16 04:57:14 PM PDT 24 |
Aug 16 04:57:17 PM PDT 24 |
130695711 ps |
| T842 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.852994139 |
|
|
Aug 16 04:58:44 PM PDT 24 |
Aug 16 05:04:14 PM PDT 24 |
10641506087 ps |
| T843 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.2714784326 |
|
|
Aug 16 04:56:40 PM PDT 24 |
Aug 16 05:01:13 PM PDT 24 |
2899168899 ps |
| T844 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.583300073 |
|
|
Aug 16 04:58:28 PM PDT 24 |
Aug 16 05:02:16 PM PDT 24 |
10149561604 ps |
| T845 |
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.3068554810 |
|
|
Aug 16 04:59:35 PM PDT 24 |
Aug 16 05:04:36 PM PDT 24 |
4463545669 ps |
| T846 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.3420314291 |
|
|
Aug 16 04:58:57 PM PDT 24 |
Aug 16 05:09:04 PM PDT 24 |
23565500491 ps |
| T847 |
/workspace/coverage/default/16.sram_ctrl_max_throughput.2798843947 |
|
|
Aug 16 04:56:49 PM PDT 24 |
Aug 16 04:57:00 PM PDT 24 |
259000139 ps |
| T848 |
/workspace/coverage/default/31.sram_ctrl_stress_all.3011674882 |
|
|
Aug 16 04:58:01 PM PDT 24 |
Aug 16 05:20:31 PM PDT 24 |
17129591545 ps |
| T849 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.761194622 |
|
|
Aug 16 04:57:08 PM PDT 24 |
Aug 16 05:08:39 PM PDT 24 |
5706441692 ps |
| T850 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.1338489889 |
|
|
Aug 16 04:57:30 PM PDT 24 |
Aug 16 04:57:36 PM PDT 24 |
1267470739 ps |
| T851 |
/workspace/coverage/default/20.sram_ctrl_stress_all.2548968982 |
|
|
Aug 16 04:57:16 PM PDT 24 |
Aug 16 05:49:57 PM PDT 24 |
11444225843 ps |
| T852 |
/workspace/coverage/default/23.sram_ctrl_alert_test.1720463472 |
|
|
Aug 16 04:57:21 PM PDT 24 |
Aug 16 04:57:22 PM PDT 24 |
31264805 ps |
| T853 |
/workspace/coverage/default/5.sram_ctrl_partial_access.3772671096 |
|
|
Aug 16 04:56:35 PM PDT 24 |
Aug 16 04:56:46 PM PDT 24 |
607552020 ps |
| T854 |
/workspace/coverage/default/44.sram_ctrl_executable.1103462154 |
|
|
Aug 16 04:59:10 PM PDT 24 |
Aug 16 05:08:54 PM PDT 24 |
62909675389 ps |
| T855 |
/workspace/coverage/default/14.sram_ctrl_bijection.1637240816 |
|
|
Aug 16 04:57:00 PM PDT 24 |
Aug 16 04:57:28 PM PDT 24 |
3486954496 ps |
| T104 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3818576359 |
|
|
Aug 16 04:56:41 PM PDT 24 |
Aug 16 04:58:27 PM PDT 24 |
3152000079 ps |
| T856 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1638943537 |
|
|
Aug 16 04:56:21 PM PDT 24 |
Aug 16 04:57:11 PM PDT 24 |
108823969 ps |
| T857 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.2216807425 |
|
|
Aug 16 04:56:31 PM PDT 24 |
Aug 16 04:56:39 PM PDT 24 |
4112680695 ps |
| T858 |
/workspace/coverage/default/45.sram_ctrl_stress_all.1956108804 |
|
|
Aug 16 04:59:17 PM PDT 24 |
Aug 16 05:04:08 PM PDT 24 |
1989395090 ps |
| T859 |
/workspace/coverage/default/35.sram_ctrl_partial_access.3453604642 |
|
|
Aug 16 04:58:13 PM PDT 24 |
Aug 16 04:58:31 PM PDT 24 |
1085257583 ps |
| T860 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.3909764515 |
|
|
Aug 16 04:58:02 PM PDT 24 |
Aug 16 05:04:20 PM PDT 24 |
16816166835 ps |
| T861 |
/workspace/coverage/default/24.sram_ctrl_executable.1488283308 |
|
|
Aug 16 04:57:27 PM PDT 24 |
Aug 16 05:07:25 PM PDT 24 |
12266815780 ps |
| T862 |
/workspace/coverage/default/36.sram_ctrl_regwen.3336816569 |
|
|
Aug 16 04:58:20 PM PDT 24 |
Aug 16 05:23:56 PM PDT 24 |
42878458126 ps |
| T863 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.3765208247 |
|
|
Aug 16 04:59:35 PM PDT 24 |
Aug 16 04:59:36 PM PDT 24 |
33735582 ps |
| T864 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.972424419 |
|
|
Aug 16 04:57:26 PM PDT 24 |
Aug 16 05:19:36 PM PDT 24 |
9644538265 ps |
| T865 |
/workspace/coverage/default/26.sram_ctrl_executable.785231279 |
|
|
Aug 16 04:57:34 PM PDT 24 |
Aug 16 04:59:11 PM PDT 24 |
2464885767 ps |
| T866 |
/workspace/coverage/default/30.sram_ctrl_regwen.2000820090 |
|
|
Aug 16 04:57:55 PM PDT 24 |
Aug 16 05:04:11 PM PDT 24 |
5392475509 ps |
| T867 |
/workspace/coverage/default/33.sram_ctrl_bijection.406380062 |
|
|
Aug 16 04:58:09 PM PDT 24 |
Aug 16 04:58:43 PM PDT 24 |
20764108104 ps |
| T868 |
/workspace/coverage/default/24.sram_ctrl_smoke.2750064460 |
|
|
Aug 16 04:57:20 PM PDT 24 |
Aug 16 04:57:25 PM PDT 24 |
300379909 ps |
| T869 |
/workspace/coverage/default/28.sram_ctrl_regwen.1801374970 |
|
|
Aug 16 04:57:44 PM PDT 24 |
Aug 16 05:00:28 PM PDT 24 |
3494667700 ps |
| T870 |
/workspace/coverage/default/28.sram_ctrl_partial_access.3753374409 |
|
|
Aug 16 04:57:42 PM PDT 24 |
Aug 16 04:57:47 PM PDT 24 |
124523208 ps |
| T871 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.573228392 |
|
|
Aug 16 04:58:09 PM PDT 24 |
Aug 16 05:19:04 PM PDT 24 |
21953656335 ps |
| T872 |
/workspace/coverage/default/22.sram_ctrl_regwen.4164647973 |
|
|
Aug 16 04:57:21 PM PDT 24 |
Aug 16 05:13:03 PM PDT 24 |
9664978619 ps |
| T873 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.3086352930 |
|
|
Aug 16 04:56:43 PM PDT 24 |
Aug 16 04:56:51 PM PDT 24 |
641740623 ps |
| T874 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.709612010 |
|
|
Aug 16 04:57:24 PM PDT 24 |
Aug 16 05:07:40 PM PDT 24 |
38860829633 ps |
| T875 |
/workspace/coverage/default/28.sram_ctrl_mem_walk.970632835 |
|
|
Aug 16 04:57:42 PM PDT 24 |
Aug 16 04:57:47 PM PDT 24 |
293629889 ps |
| T876 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.4248900986 |
|
|
Aug 16 04:56:37 PM PDT 24 |
Aug 16 04:56:40 PM PDT 24 |
217331842 ps |
| T877 |
/workspace/coverage/default/5.sram_ctrl_smoke.4225992409 |
|
|
Aug 16 04:56:36 PM PDT 24 |
Aug 16 04:56:54 PM PDT 24 |
1028346306 ps |
| T878 |
/workspace/coverage/default/13.sram_ctrl_partial_access.1710434544 |
|
|
Aug 16 04:56:45 PM PDT 24 |
Aug 16 04:56:59 PM PDT 24 |
472724632 ps |
| T879 |
/workspace/coverage/default/48.sram_ctrl_alert_test.4081425791 |
|
|
Aug 16 04:59:36 PM PDT 24 |
Aug 16 04:59:37 PM PDT 24 |
17733732 ps |
| T880 |
/workspace/coverage/default/17.sram_ctrl_partial_access.856257406 |
|
|
Aug 16 04:57:04 PM PDT 24 |
Aug 16 04:57:18 PM PDT 24 |
2795094727 ps |
| T881 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.249459668 |
|
|
Aug 16 04:58:13 PM PDT 24 |
Aug 16 04:58:15 PM PDT 24 |
79785808 ps |
| T882 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.3433942258 |
|
|
Aug 16 04:58:14 PM PDT 24 |
Aug 16 04:58:17 PM PDT 24 |
171766666 ps |
| T883 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.88385337 |
|
|
Aug 16 04:56:40 PM PDT 24 |
Aug 16 04:58:06 PM PDT 24 |
5283701482 ps |
| T884 |
/workspace/coverage/default/43.sram_ctrl_partial_access.1486151794 |
|
|
Aug 16 04:59:05 PM PDT 24 |
Aug 16 04:59:44 PM PDT 24 |
434942002 ps |
| T885 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.2691067897 |
|
|
Aug 16 04:57:11 PM PDT 24 |
Aug 16 04:58:27 PM PDT 24 |
131798943 ps |
| T886 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.2888996419 |
|
|
Aug 16 04:59:12 PM PDT 24 |
Aug 16 05:01:07 PM PDT 24 |
245778647 ps |
| T887 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.1239047539 |
|
|
Aug 16 04:57:09 PM PDT 24 |
Aug 16 04:57:10 PM PDT 24 |
30146299 ps |
| T888 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.2268306848 |
|
|
Aug 16 04:58:19 PM PDT 24 |
Aug 16 04:58:25 PM PDT 24 |
182352970 ps |
| T79 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.2012617466 |
|
|
Aug 16 04:56:20 PM PDT 24 |
Aug 16 04:56:24 PM PDT 24 |
118253888 ps |
| T889 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.374805786 |
|
|
Aug 16 04:57:05 PM PDT 24 |
Aug 16 05:00:03 PM PDT 24 |
148865650 ps |
| T890 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.3838537625 |
|
|
Aug 16 04:59:11 PM PDT 24 |
Aug 16 05:03:29 PM PDT 24 |
9936922383 ps |
| T891 |
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.3610686724 |
|
|
Aug 16 04:57:53 PM PDT 24 |
Aug 16 04:58:00 PM PDT 24 |
650096014 ps |
| T892 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.2360959051 |
|
|
Aug 16 04:57:30 PM PDT 24 |
Aug 16 04:57:34 PM PDT 24 |
103079869 ps |
| T893 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.751733349 |
|
|
Aug 16 04:59:45 PM PDT 24 |
Aug 16 05:00:59 PM PDT 24 |
990345121 ps |
| T894 |
/workspace/coverage/default/36.sram_ctrl_stress_all.3923134271 |
|
|
Aug 16 04:58:20 PM PDT 24 |
Aug 16 05:35:47 PM PDT 24 |
88562904384 ps |
| T895 |
/workspace/coverage/default/27.sram_ctrl_alert_test.463010865 |
|
|
Aug 16 04:57:41 PM PDT 24 |
Aug 16 04:57:42 PM PDT 24 |
14873456 ps |
| T896 |
/workspace/coverage/default/48.sram_ctrl_partial_access.3303877897 |
|
|
Aug 16 04:59:30 PM PDT 24 |
Aug 16 04:59:45 PM PDT 24 |
3341194224 ps |
| T897 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.3781614760 |
|
|
Aug 16 04:57:29 PM PDT 24 |
Aug 16 05:00:34 PM PDT 24 |
12071880574 ps |
| T898 |
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.2876542746 |
|
|
Aug 16 04:57:48 PM PDT 24 |
Aug 16 05:06:10 PM PDT 24 |
21416020669 ps |
| T899 |
/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.4283972241 |
|
|
Aug 16 04:57:54 PM PDT 24 |
Aug 16 04:59:36 PM PDT 24 |
246923407 ps |
| T900 |
/workspace/coverage/default/21.sram_ctrl_ram_cfg.1531571313 |
|
|
Aug 16 04:57:17 PM PDT 24 |
Aug 16 04:57:18 PM PDT 24 |
28188523 ps |
| T901 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.1136547784 |
|
|
Aug 16 04:58:09 PM PDT 24 |
Aug 16 05:03:01 PM PDT 24 |
11662752179 ps |
| T902 |
/workspace/coverage/default/43.sram_ctrl_alert_test.503188849 |
|
|
Aug 16 04:59:03 PM PDT 24 |
Aug 16 04:59:04 PM PDT 24 |
12367898 ps |
| T903 |
/workspace/coverage/default/37.sram_ctrl_bijection.753732214 |
|
|
Aug 16 04:58:28 PM PDT 24 |
Aug 16 04:59:15 PM PDT 24 |
2714657724 ps |
| T904 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.2894233729 |
|
|
Aug 16 04:56:10 PM PDT 24 |
Aug 16 04:59:52 PM PDT 24 |
9117943075 ps |
| T905 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.2725415658 |
|
|
Aug 16 04:57:07 PM PDT 24 |
Aug 16 05:01:11 PM PDT 24 |
29966934421 ps |
| T906 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.119861108 |
|
|
Aug 16 04:58:20 PM PDT 24 |
Aug 16 04:58:31 PM PDT 24 |
1196707581 ps |
| T907 |
/workspace/coverage/default/22.sram_ctrl_executable.3562354860 |
|
|
Aug 16 04:57:25 PM PDT 24 |
Aug 16 05:13:20 PM PDT 24 |
22647251124 ps |
| T908 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.3275640602 |
|
|
Aug 16 04:59:44 PM PDT 24 |
Aug 16 04:59:53 PM PDT 24 |
570415451 ps |
| T909 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.3474118866 |
|
|
Aug 16 04:59:19 PM PDT 24 |
Aug 16 05:04:28 PM PDT 24 |
22743783204 ps |
| T910 |
/workspace/coverage/default/5.sram_ctrl_bijection.2910831824 |
|
|
Aug 16 04:56:37 PM PDT 24 |
Aug 16 04:57:52 PM PDT 24 |
18880634395 ps |
| T911 |
/workspace/coverage/default/40.sram_ctrl_partial_access.622387736 |
|
|
Aug 16 04:58:41 PM PDT 24 |
Aug 16 04:58:57 PM PDT 24 |
303071746 ps |
| T912 |
/workspace/coverage/default/6.sram_ctrl_executable.1313437743 |
|
|
Aug 16 04:56:41 PM PDT 24 |
Aug 16 05:01:42 PM PDT 24 |
4085668451 ps |
| T913 |
/workspace/coverage/default/2.sram_ctrl_alert_test.3329622626 |
|
|
Aug 16 04:56:20 PM PDT 24 |
Aug 16 04:56:21 PM PDT 24 |
22343773 ps |
| T914 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.3425065349 |
|
|
Aug 16 04:57:18 PM PDT 24 |
Aug 16 04:57:50 PM PDT 24 |
318469568 ps |
| T915 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3046968363 |
|
|
Aug 16 04:59:31 PM PDT 24 |
Aug 16 05:05:10 PM PDT 24 |
2507255401 ps |
| T916 |
/workspace/coverage/default/2.sram_ctrl_bijection.2394515971 |
|
|
Aug 16 04:56:26 PM PDT 24 |
Aug 16 04:57:37 PM PDT 24 |
15349168318 ps |
| T917 |
/workspace/coverage/default/37.sram_ctrl_stress_all.3368613028 |
|
|
Aug 16 04:58:27 PM PDT 24 |
Aug 16 05:57:15 PM PDT 24 |
129607496312 ps |
| T918 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3488371804 |
|
|
Aug 16 04:56:40 PM PDT 24 |
Aug 16 04:57:12 PM PDT 24 |
1233737385 ps |
| T919 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.827922941 |
|
|
Aug 16 04:57:28 PM PDT 24 |
Aug 16 05:20:31 PM PDT 24 |
99838116691 ps |
| T920 |
/workspace/coverage/default/8.sram_ctrl_stress_all.3992945277 |
|
|
Aug 16 04:56:40 PM PDT 24 |
Aug 16 05:08:57 PM PDT 24 |
14739935257 ps |
| T921 |
/workspace/coverage/default/46.sram_ctrl_smoke.1585059848 |
|
|
Aug 16 04:59:18 PM PDT 24 |
Aug 16 04:59:26 PM PDT 24 |
131660713 ps |
| T922 |
/workspace/coverage/default/32.sram_ctrl_executable.1704467179 |
|
|
Aug 16 04:58:01 PM PDT 24 |
Aug 16 05:03:13 PM PDT 24 |
3332143329 ps |
| T923 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.2131101001 |
|
|
Aug 16 04:57:20 PM PDT 24 |
Aug 16 05:05:18 PM PDT 24 |
53451699868 ps |
| T924 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.1467712377 |
|
|
Aug 16 04:59:02 PM PDT 24 |
Aug 16 04:59:03 PM PDT 24 |
85583055 ps |
| T925 |
/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.2489345701 |
|
|
Aug 16 04:57:14 PM PDT 24 |
Aug 16 04:57:19 PM PDT 24 |
50393596 ps |
| T926 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1109335894 |
|
|
Aug 16 04:59:26 PM PDT 24 |
Aug 16 04:59:28 PM PDT 24 |
155511259 ps |
| T927 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.3430044940 |
|
|
Aug 16 04:57:41 PM PDT 24 |
Aug 16 04:57:51 PM PDT 24 |
252784224 ps |
| T928 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.3143338968 |
|
|
Aug 16 04:56:26 PM PDT 24 |
Aug 16 04:57:00 PM PDT 24 |
392833711 ps |
| T929 |
/workspace/coverage/default/16.sram_ctrl_stress_all.2006833349 |
|
|
Aug 16 04:57:09 PM PDT 24 |
Aug 16 05:37:49 PM PDT 24 |
75408468025 ps |
| T930 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.3471196469 |
|
|
Aug 16 04:58:22 PM PDT 24 |
Aug 16 05:06:53 PM PDT 24 |
44309277399 ps |
| T931 |
/workspace/coverage/default/16.sram_ctrl_executable.1117868973 |
|
|
Aug 16 04:56:55 PM PDT 24 |
Aug 16 05:09:13 PM PDT 24 |
22020525735 ps |
| T56 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3740249401 |
|
|
Aug 16 04:55:33 PM PDT 24 |
Aug 16 04:55:35 PM PDT 24 |
196291513 ps |
| T57 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.793824005 |
|
|
Aug 16 04:55:38 PM PDT 24 |
Aug 16 04:55:39 PM PDT 24 |
21790397 ps |
| T58 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2430831995 |
|
|
Aug 16 04:55:40 PM PDT 24 |
Aug 16 04:55:41 PM PDT 24 |
21104638 ps |
| T52 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1751335509 |
|
|
Aug 16 04:55:43 PM PDT 24 |
Aug 16 04:55:45 PM PDT 24 |
748558710 ps |
| T932 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.591933325 |
|
|
Aug 16 04:55:29 PM PDT 24 |
Aug 16 04:55:32 PM PDT 24 |
87685162 ps |
| T933 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1299906532 |
|
|
Aug 16 04:55:42 PM PDT 24 |
Aug 16 04:55:43 PM PDT 24 |
31194204 ps |
| T63 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4093375935 |
|
|
Aug 16 04:55:34 PM PDT 24 |
Aug 16 04:55:35 PM PDT 24 |
58683747 ps |
| T96 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.334311009 |
|
|
Aug 16 04:55:29 PM PDT 24 |
Aug 16 04:55:30 PM PDT 24 |
65251128 ps |
| T64 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.127838666 |
|
|
Aug 16 04:55:35 PM PDT 24 |
Aug 16 04:55:37 PM PDT 24 |
515451111 ps |
| T85 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3351412801 |
|
|
Aug 16 04:55:34 PM PDT 24 |
Aug 16 04:55:36 PM PDT 24 |
107616328 ps |
| T934 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.577128564 |
|
|
Aug 16 04:55:34 PM PDT 24 |
Aug 16 04:55:36 PM PDT 24 |
33950913 ps |
| T86 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.651224932 |
|
|
Aug 16 04:55:41 PM PDT 24 |
Aug 16 04:55:42 PM PDT 24 |
23547399 ps |
| T97 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2994082396 |
|
|
Aug 16 04:55:34 PM PDT 24 |
Aug 16 04:55:35 PM PDT 24 |
58499792 ps |
| T935 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1327952023 |
|
|
Aug 16 04:55:39 PM PDT 24 |
Aug 16 04:55:42 PM PDT 24 |
365894791 ps |
| T53 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.512301386 |
|
|
Aug 16 04:55:42 PM PDT 24 |
Aug 16 04:55:44 PM PDT 24 |
172919182 ps |
| T87 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1162222094 |
|
|
Aug 16 04:55:41 PM PDT 24 |
Aug 16 04:55:42 PM PDT 24 |
37153507 ps |
| T65 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.261339448 |
|
|
Aug 16 04:55:42 PM PDT 24 |
Aug 16 04:55:44 PM PDT 24 |
682495602 ps |
| T54 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3309386199 |
|
|
Aug 16 04:55:40 PM PDT 24 |
Aug 16 04:55:42 PM PDT 24 |
172785559 ps |
| T936 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.922097118 |
|
|
Aug 16 04:55:39 PM PDT 24 |
Aug 16 04:55:39 PM PDT 24 |
21230463 ps |
| T937 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.608920192 |
|
|
Aug 16 04:55:47 PM PDT 24 |
Aug 16 04:55:48 PM PDT 24 |
39026650 ps |
| T938 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3342732138 |
|
|
Aug 16 04:55:42 PM PDT 24 |
Aug 16 04:55:43 PM PDT 24 |
44955456 ps |
| T88 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1768363658 |
|
|
Aug 16 04:55:42 PM PDT 24 |
Aug 16 04:55:46 PM PDT 24 |
1793561901 ps |
| T939 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1181219121 |
|
|
Aug 16 04:55:26 PM PDT 24 |
Aug 16 04:55:27 PM PDT 24 |
45240932 ps |
| T66 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1765024957 |
|
|
Aug 16 04:55:35 PM PDT 24 |
Aug 16 04:55:39 PM PDT 24 |
818716966 ps |
| T67 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3939249437 |
|
|
Aug 16 04:55:40 PM PDT 24 |
Aug 16 04:55:41 PM PDT 24 |
15435757 ps |
| T940 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.69659041 |
|
|
Aug 16 04:55:45 PM PDT 24 |
Aug 16 04:55:49 PM PDT 24 |
129691108 ps |
| T121 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2651640083 |
|
|
Aug 16 04:55:43 PM PDT 24 |
Aug 16 04:55:45 PM PDT 24 |
190679349 ps |
| T68 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4038947038 |
|
|
Aug 16 04:55:32 PM PDT 24 |
Aug 16 04:55:33 PM PDT 24 |
105966517 ps |
| T941 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2424308161 |
|
|
Aug 16 04:55:34 PM PDT 24 |
Aug 16 04:55:36 PM PDT 24 |
27503886 ps |
| T942 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3227072655 |
|
|
Aug 16 04:55:42 PM PDT 24 |
Aug 16 04:55:47 PM PDT 24 |
635054974 ps |
| T943 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3781322429 |
|
|
Aug 16 04:55:41 PM PDT 24 |
Aug 16 04:55:42 PM PDT 24 |
42447884 ps |
| T117 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2827040619 |
|
|
Aug 16 04:55:44 PM PDT 24 |
Aug 16 04:55:46 PM PDT 24 |
389539231 ps |
| T126 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3319679039 |
|
|
Aug 16 04:55:46 PM PDT 24 |
Aug 16 04:55:48 PM PDT 24 |
147833474 ps |
| T69 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.4258196179 |
|
|
Aug 16 04:55:28 PM PDT 24 |
Aug 16 04:55:29 PM PDT 24 |
37134397 ps |
| T70 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3801557357 |
|
|
Aug 16 04:55:35 PM PDT 24 |
Aug 16 04:55:36 PM PDT 24 |
52340393 ps |
| T944 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3334826479 |
|
|
Aug 16 04:55:35 PM PDT 24 |
Aug 16 04:55:36 PM PDT 24 |
39854154 ps |
| T71 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3153671889 |
|
|
Aug 16 04:55:38 PM PDT 24 |
Aug 16 04:55:42 PM PDT 24 |
2347293516 ps |
| T72 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.644487331 |
|
|
Aug 16 04:55:45 PM PDT 24 |
Aug 16 04:55:47 PM PDT 24 |
211948877 ps |
| T945 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2677451846 |
|
|
Aug 16 04:55:46 PM PDT 24 |
Aug 16 04:55:47 PM PDT 24 |
26783499 ps |
| T946 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3145492286 |
|
|
Aug 16 04:55:35 PM PDT 24 |
Aug 16 04:55:37 PM PDT 24 |
352353055 ps |
| T947 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1698037480 |
|
|
Aug 16 04:55:33 PM PDT 24 |
Aug 16 04:55:34 PM PDT 24 |
14516845 ps |
| T948 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3859836304 |
|
|
Aug 16 04:55:44 PM PDT 24 |
Aug 16 04:55:47 PM PDT 24 |
26289996 ps |
| T949 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2477401886 |
|
|
Aug 16 04:55:26 PM PDT 24 |
Aug 16 04:55:28 PM PDT 24 |
220841072 ps |
| T950 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.650950054 |
|
|
Aug 16 04:55:33 PM PDT 24 |
Aug 16 04:55:34 PM PDT 24 |
40773564 ps |
| T951 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2139569661 |
|
|
Aug 16 04:55:44 PM PDT 24 |
Aug 16 04:55:49 PM PDT 24 |
41440180 ps |
| T952 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1018841313 |
|
|
Aug 16 04:55:44 PM PDT 24 |
Aug 16 04:55:48 PM PDT 24 |
177940295 ps |
| T953 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.296093821 |
|
|
Aug 16 04:55:44 PM PDT 24 |
Aug 16 04:55:45 PM PDT 24 |
47030689 ps |
| T118 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2636470032 |
|
|
Aug 16 04:55:46 PM PDT 24 |
Aug 16 04:55:48 PM PDT 24 |
288080643 ps |
| T954 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1116504689 |
|
|
Aug 16 04:55:37 PM PDT 24 |
Aug 16 04:55:39 PM PDT 24 |
44276062 ps |
| T73 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.4218129178 |
|
|
Aug 16 04:55:33 PM PDT 24 |
Aug 16 04:55:35 PM PDT 24 |
1572772847 ps |
| T955 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.98720926 |
|
|
Aug 16 04:55:49 PM PDT 24 |
Aug 16 04:55:49 PM PDT 24 |
36065346 ps |
| T119 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3281996597 |
|
|
Aug 16 04:55:50 PM PDT 24 |
Aug 16 04:55:52 PM PDT 24 |
709174208 ps |
| T956 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2033454531 |
|
|
Aug 16 04:55:42 PM PDT 24 |
Aug 16 04:55:43 PM PDT 24 |
151322112 ps |
| T957 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3909308382 |
|
|
Aug 16 04:55:41 PM PDT 24 |
Aug 16 04:55:42 PM PDT 24 |
38037564 ps |
| T74 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.4009884723 |
|
|
Aug 16 04:55:42 PM PDT 24 |
Aug 16 04:55:47 PM PDT 24 |
5203212357 ps |
| T958 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1329784830 |
|
|
Aug 16 04:55:41 PM PDT 24 |
Aug 16 04:55:42 PM PDT 24 |
93348261 ps |
| T959 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2393609510 |
|
|
Aug 16 04:55:43 PM PDT 24 |
Aug 16 04:55:45 PM PDT 24 |
381355449 ps |
| T960 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2040149624 |
|
|
Aug 16 04:55:39 PM PDT 24 |
Aug 16 04:55:40 PM PDT 24 |
120004347 ps |
| T961 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3960687892 |
|
|
Aug 16 04:55:34 PM PDT 24 |
Aug 16 04:55:36 PM PDT 24 |
253692226 ps |
| T128 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4016280695 |
|
|
Aug 16 04:55:41 PM PDT 24 |
Aug 16 04:55:44 PM PDT 24 |
298953434 ps |
| T962 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.4054955353 |
|
|
Aug 16 04:55:34 PM PDT 24 |
Aug 16 04:55:35 PM PDT 24 |
43128653 ps |
| T963 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2814566446 |
|
|
Aug 16 04:55:26 PM PDT 24 |
Aug 16 04:55:27 PM PDT 24 |
22708166 ps |
| T81 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.51004981 |
|
|
Aug 16 04:55:47 PM PDT 24 |
Aug 16 04:55:48 PM PDT 24 |
30198587 ps |
| T82 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.558158399 |
|
|
Aug 16 04:55:44 PM PDT 24 |
Aug 16 04:55:47 PM PDT 24 |
452230430 ps |
| T964 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3873388600 |
|
|
Aug 16 04:55:33 PM PDT 24 |
Aug 16 04:55:34 PM PDT 24 |
48375539 ps |
| T965 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1256658777 |
|
|
Aug 16 04:55:34 PM PDT 24 |
Aug 16 04:55:36 PM PDT 24 |
120192318 ps |
| T84 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.306517219 |
|
|
Aug 16 04:55:34 PM PDT 24 |
Aug 16 04:55:35 PM PDT 24 |
32149201 ps |
| T966 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.352809026 |
|
|
Aug 16 04:55:39 PM PDT 24 |
Aug 16 04:55:40 PM PDT 24 |
74730998 ps |
| T967 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3806051562 |
|
|
Aug 16 04:55:32 PM PDT 24 |
Aug 16 04:55:34 PM PDT 24 |
33364845 ps |
| T968 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3533580108 |
|
|
Aug 16 04:55:46 PM PDT 24 |
Aug 16 04:55:48 PM PDT 24 |
591331618 ps |
| T969 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2805538184 |
|
|
Aug 16 04:55:39 PM PDT 24 |
Aug 16 04:55:40 PM PDT 24 |
40110192 ps |
| T970 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2396002572 |
|
|
Aug 16 04:55:35 PM PDT 24 |
Aug 16 04:55:37 PM PDT 24 |
151529893 ps |
| T971 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3507545574 |
|
|
Aug 16 04:55:43 PM PDT 24 |
Aug 16 04:55:44 PM PDT 24 |
24963969 ps |
| T972 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2627927061 |
|
|
Aug 16 04:55:31 PM PDT 24 |
Aug 16 04:55:33 PM PDT 24 |
54956886 ps |
| T973 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.238146347 |
|
|
Aug 16 04:55:45 PM PDT 24 |
Aug 16 04:55:50 PM PDT 24 |
858662506 ps |
| T974 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1111051451 |
|
|
Aug 16 04:55:47 PM PDT 24 |
Aug 16 04:55:50 PM PDT 24 |
323599017 ps |
| T975 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1989901538 |
|
|
Aug 16 04:55:44 PM PDT 24 |
Aug 16 04:55:45 PM PDT 24 |
44729187 ps |
| T976 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.576116492 |
|
|
Aug 16 04:55:43 PM PDT 24 |
Aug 16 04:55:47 PM PDT 24 |
119046459 ps |
| T977 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.694088432 |
|
|
Aug 16 04:55:43 PM PDT 24 |
Aug 16 04:55:45 PM PDT 24 |
774273049 ps |
| T978 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1218730894 |
|
|
Aug 16 04:55:33 PM PDT 24 |
Aug 16 04:55:34 PM PDT 24 |
22838444 ps |
| T979 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2480575205 |
|
|
Aug 16 04:55:34 PM PDT 24 |
Aug 16 04:55:38 PM PDT 24 |
368667811 ps |
| T980 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2530671913 |
|
|
Aug 16 04:55:41 PM PDT 24 |
Aug 16 04:55:42 PM PDT 24 |
34005096 ps |
| T981 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.297141677 |
|
|
Aug 16 04:55:40 PM PDT 24 |
Aug 16 04:55:41 PM PDT 24 |
24968420 ps |
| T122 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1926081723 |
|
|
Aug 16 04:55:34 PM PDT 24 |
Aug 16 04:55:36 PM PDT 24 |
492594378 ps |
| T982 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3690234744 |
|
|
Aug 16 04:55:47 PM PDT 24 |
Aug 16 04:55:48 PM PDT 24 |
40910923 ps |
| T983 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3607414115 |
|
|
Aug 16 04:55:42 PM PDT 24 |
Aug 16 04:55:43 PM PDT 24 |
17430881 ps |
| T120 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3284954936 |
|
|
Aug 16 04:55:32 PM PDT 24 |
Aug 16 04:55:35 PM PDT 24 |
591417464 ps |
| T984 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2322151365 |
|
|
Aug 16 04:55:43 PM PDT 24 |
Aug 16 04:55:44 PM PDT 24 |
28848614 ps |
| T985 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2288348386 |
|
|
Aug 16 04:55:40 PM PDT 24 |
Aug 16 04:55:45 PM PDT 24 |
325794764 ps |
| T986 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3791199423 |
|
|
Aug 16 04:55:34 PM PDT 24 |
Aug 16 04:55:39 PM PDT 24 |
191907499 ps |
| T987 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.825053868 |
|
|
Aug 16 04:55:33 PM PDT 24 |
Aug 16 04:55:34 PM PDT 24 |
94672694 ps |
| T988 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1271747101 |
|
|
Aug 16 04:55:42 PM PDT 24 |
Aug 16 04:55:44 PM PDT 24 |
45882752 ps |
| T989 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2694020228 |
|
|
Aug 16 04:55:45 PM PDT 24 |
Aug 16 04:55:49 PM PDT 24 |
99557327 ps |
| T990 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2025894597 |
|
|
Aug 16 04:55:47 PM PDT 24 |
Aug 16 04:55:48 PM PDT 24 |
38717692 ps |
| T991 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3092701905 |
|
|
Aug 16 04:55:45 PM PDT 24 |
Aug 16 04:55:46 PM PDT 24 |
99425740 ps |
| T83 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2790562722 |
|
|
Aug 16 04:55:43 PM PDT 24 |
Aug 16 04:55:45 PM PDT 24 |
412295438 ps |
| T129 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1969529523 |
|
|
Aug 16 04:55:42 PM PDT 24 |
Aug 16 04:55:44 PM PDT 24 |
411624063 ps |
| T992 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1276945699 |
|
|
Aug 16 04:55:40 PM PDT 24 |
Aug 16 04:55:41 PM PDT 24 |
30285000 ps |
| T993 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.915330065 |
|
|
Aug 16 04:55:44 PM PDT 24 |
Aug 16 04:55:45 PM PDT 24 |
23539643 ps |
| T994 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3696769691 |
|
|
Aug 16 04:55:40 PM PDT 24 |
Aug 16 04:55:40 PM PDT 24 |
49073519 ps |
| T127 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2810351816 |
|
|
Aug 16 04:55:30 PM PDT 24 |
Aug 16 04:55:32 PM PDT 24 |
350786122 ps |
| T995 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3306693331 |
|
|
Aug 16 04:55:48 PM PDT 24 |
Aug 16 04:55:53 PM PDT 24 |
236111302 ps |
| T996 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.5223189 |
|
|
Aug 16 04:55:41 PM PDT 24 |
Aug 16 04:55:45 PM PDT 24 |
5558387911 ps |
| T997 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.4039283682 |
|
|
Aug 16 04:55:39 PM PDT 24 |
Aug 16 04:55:41 PM PDT 24 |
124935611 ps |
| T998 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.4020463561 |
|
|
Aug 16 04:55:40 PM PDT 24 |
Aug 16 04:55:42 PM PDT 24 |
215680739 ps |
| T999 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3182221957 |
|
|
Aug 16 04:55:41 PM PDT 24 |
Aug 16 04:55:44 PM PDT 24 |
736079986 ps |
| T123 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.493744439 |
|
|
Aug 16 04:55:46 PM PDT 24 |
Aug 16 04:55:49 PM PDT 24 |
181320511 ps |
| T1000 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1980686021 |
|
|
Aug 16 04:55:36 PM PDT 24 |
Aug 16 04:55:38 PM PDT 24 |
90632589 ps |
| T1001 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.657914297 |
|
|
Aug 16 04:55:43 PM PDT 24 |
Aug 16 04:55:44 PM PDT 24 |
50787669 ps |
| T80 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1212653717 |
|
|
Aug 16 04:55:33 PM PDT 24 |
Aug 16 04:55:34 PM PDT 24 |
22370696 ps |
| T1002 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.733362905 |
|
|
Aug 16 04:55:41 PM PDT 24 |
Aug 16 04:55:45 PM PDT 24 |
1481928086 ps |
| T1003 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4007481152 |
|
|
Aug 16 04:55:44 PM PDT 24 |
Aug 16 04:55:45 PM PDT 24 |
15815743 ps |