Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	146928814	1			T1	13780		T3	4076		T4	201260
instr_valid_dis	113477748	1			T1	13780		T3	4076		T4	63742
instr_en	24208075	1			T4	113760		T5	890582		T7	360432

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10802266	1			T4	34638		T5	230822		T7	20000
sram_ifetch_valid_disable	112989966	1			T1	13780		T3	4076		T4	29184
sram_ifetch_enable	23136582	1			T4	137438		T5	303410		T7	90000

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	146928814	1			T1	13780		T3	4076		T4	201260
hw_debug_en_valid_off	111219076	1			T1	13780		T3	4076		T4	39200
hw_debug_en_on	25019683	1			T4	140066		T5	549340		T7	222334

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	112989966	1			T1	13780		T3	4076		T4	29184
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	97842396	1			T1	13780		T3	4076		T4	29104
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	11115765	1			T4	80		T5	356350		T7	250432
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4581975	1			T5	132682		T7	20000		T41	62638
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2221705	1			T41	20004		T17	67812		T131	17932
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1701818	1			T5	132682		T7	20000		T41	42634
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4461116	1			T4	27836		T5	98140		T45	22906
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2129174	1			T4	27836		T131	49038		T136	20000
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1817418	1			T5	98140		T17	1778		T133	27194
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	11426831	1			T4	29184		T5	297842		T7	217708
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4253317	1			T4	29104		T17	57320		T131	30374
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	5148424	1			T4	80		T5	297842		T7	217708

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8987466	1			T4	113680		T5	303410		T7	90000
lc_exec_en	9131736	1			T4	83046		T5	153358		T7	4626
valid_exec_dis	107463657	1			T1	13780		T3	4076		T5	145884
invalid_exec_dis	33938848	1			T4	172076		T5	534232		T7	110000