Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	42753536	1			T1	6890		T3	111		T4	36581
triple_byte_access	2480716	1			T3	233		T4	726		T5	3225
halfword_access	3722125	1			T3	471		T4	1106		T5	4874
byte_access	4971716	1			T3	787		T4	1504		T5	6568
zero_access	1250475	1			T3	436		T4	353		T5	1608

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27537948

1

T1

3498

T3

896

T4

20098

auto[1]

27640620

1

T1

3392

T3

1142

T4

20172

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21331578	1			T1	3498		T3	7		T4	18272
auto[0]	triple_byte_access	1235840	1			T3	35		T4	357		T5	1634
auto[0]	halfword_access	1856690	1			T3	138		T4	561		T5	2385
auto[0]	byte_access	2484262	1			T3	378		T4	732		T5	3278
auto[0]	zero_access	629578	1			T3	338		T4	176		T5	764
auto[1]	word_access	21421958	1			T1	3392		T3	104		T4	18309
auto[1]	triple_byte_access	1244876	1			T3	198		T4	369		T5	1591
auto[1]	halfword_access	1865435	1			T3	333		T4	545		T5	2489
auto[1]	byte_access	2487454	1			T3	409		T4	772		T5	3290
auto[1]	zero_access	620897	1			T3	98		T4	177		T5	844