Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14819620	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

62961185

1

T1

123102

T2

54

T4

30217

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	38786015	1			T1	67575		T2	339		T4	83047
values[0x0]	18010917	1			T1	33037		T2	183		T4	27859
values[0x1]	20983873	1			T1	35024		T2	400		T4	54976

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7382166	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

70398639

1

T1

129342

T2

428

T4

98283

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	321527	1			T1	755		T4	624		T5	799
valid_sources[0x01]	267105	1			T2	1		T4	626		T5	843
valid_sources[0x02]	293639	1			T2	6		T4	650		T5	791
valid_sources[0x03]	293534	1			T2	3		T4	632		T5	908
valid_sources[0x04]	327512	1			T4	694		T5	771		T6	16
valid_sources[0x05]	344086	1			T2	5		T4	700		T5	841
valid_sources[0x06]	279934	1			T4	624		T5	913		T6	8
valid_sources[0x07]	382401	1			T2	28		T4	649		T5	882
valid_sources[0x08]	284702	1			T4	617		T5	860		T6	12
valid_sources[0x09]	264978	1			T2	14		T4	670		T5	697
valid_sources[0x0a]	324406	1			T4	617		T5	865		T7	8
valid_sources[0x0b]	316578	1			T2	10		T4	739		T5	747
valid_sources[0x0c]	347096	1			T4	656		T5	924		T6	4
valid_sources[0x0d]	334137	1			T4	645		T5	988		T7	60
valid_sources[0x0e]	265142	1			T2	22		T4	621		T5	736
valid_sources[0x0f]	258045	1			T4	642		T5	722		T6	17
valid_sources[0x10]	284769	1			T4	644		T5	858		T6	7
valid_sources[0x11]	350081	1			T4	682		T5	783		T7	11
valid_sources[0x12]	318976	1			T2	3		T4	601		T5	767
valid_sources[0x13]	281924	1			T2	14		T4	640		T5	795
valid_sources[0x14]	348687	1			T1	83		T4	624		T5	798
valid_sources[0x15]	360606	1			T4	617		T5	888		T6	9
valid_sources[0x16]	306282	1			T2	16		T4	641		T5	714
valid_sources[0x17]	295167	1			T4	628		T5	895		T7	106
valid_sources[0x18]	313612	1			T4	624		T5	718		T6	6
valid_sources[0x19]	312959	1			T4	638		T5	635		T6	2
valid_sources[0x1a]	299352	1			T4	651		T5	847		T6	7
valid_sources[0x1b]	299407	1			T2	2		T4	666		T5	1011
valid_sources[0x1c]	290791	1			T4	618		T5	935		T6	8
valid_sources[0x1d]	291758	1			T2	9		T4	677		T5	841
valid_sources[0x1e]	303912	1			T1	1162		T2	10		T4	669
valid_sources[0x1f]	308151	1			T2	5		T4	640		T5	729
valid_sources[0x20]	378793	1			T1	80		T2	12		T4	684
valid_sources[0x21]	306159	1			T2	4		T4	639		T5	862
valid_sources[0x22]	259552	1			T2	19		T4	645		T5	873
valid_sources[0x23]	270935	1			T2	2		T4	629		T5	1014
valid_sources[0x24]	300133	1			T4	644		T5	813		T6	9
valid_sources[0x25]	271149	1			T4	637		T5	698		T6	4
valid_sources[0x26]	337534	1			T2	16		T4	688		T5	842
valid_sources[0x27]	295540	1			T2	7		T4	644		T5	898
valid_sources[0x28]	312233	1			T4	734		T5	779		T6	11
valid_sources[0x29]	299684	1			T4	700		T5	817		T6	6
valid_sources[0x2a]	281241	1			T2	1		T4	636		T5	870
valid_sources[0x2b]	286868	1			T1	59		T2	3		T4	649
valid_sources[0x2c]	270508	1			T2	12		T4	668		T5	695
valid_sources[0x2d]	374467	1			T4	645		T5	760		T6	12
valid_sources[0x2e]	283682	1			T2	9		T4	666		T5	676
valid_sources[0x2f]	263719	1			T4	670		T5	873		T6	9
valid_sources[0x30]	303128	1			T4	605		T5	886		T6	5
valid_sources[0x31]	288533	1			T4	666		T5	778		T6	11
valid_sources[0x32]	336585	1			T4	616		T5	803		T6	6
valid_sources[0x33]	331717	1			T2	1		T4	663		T5	887
valid_sources[0x34]	382134	1			T1	229		T4	668		T5	926
valid_sources[0x35]	274216	1			T1	8		T2	1		T4	680
valid_sources[0x36]	296943	1			T2	1		T4	660		T5	781
valid_sources[0x37]	301860	1			T2	17		T4	680		T5	871
valid_sources[0x38]	290414	1			T1	91		T2	4		T4	624
valid_sources[0x39]	290964	1			T1	11		T4	669		T5	883
valid_sources[0x3a]	318812	1			T4	677		T5	699		T6	7
valid_sources[0x3b]	297454	1			T1	47		T4	631		T5	757
valid_sources[0x3c]	341685	1			T4	692		T5	788		T6	4
valid_sources[0x3d]	259388	1			T1	88		T4	668		T5	831
valid_sources[0x3e]	282516	1			T2	18		T4	695		T5	859
valid_sources[0x3f]	308541	1			T2	13		T4	654		T5	876
valid_sources[0x40]	298160	1			T2	7		T4	639		T5	945
valid_sources[0x41]	270568	1			T1	124		T2	4		T4	637
valid_sources[0x42]	364681	1			T4	641		T5	920		T7	80
valid_sources[0x43]	319340	1			T4	588		T5	826		T7	18
valid_sources[0x44]	282255	1			T4	631		T5	902		T6	2
valid_sources[0x45]	261587	1			T4	626		T5	728		T6	8
valid_sources[0x46]	279525	1			T4	652		T5	698		T6	8
valid_sources[0x47]	285305	1			T1	16		T4	657		T5	956
valid_sources[0x48]	286341	1			T4	639		T5	856		T6	15
valid_sources[0x49]	340044	1			T4	638		T5	809		T6	4
valid_sources[0x4a]	293961	1			T4	634		T5	769		T6	7
valid_sources[0x4b]	309430	1			T1	69		T4	662		T5	758
valid_sources[0x4c]	284328	1			T2	12		T4	641		T5	908
valid_sources[0x4d]	299431	1			T4	631		T5	862		T6	11
valid_sources[0x4e]	272955	1			T1	30		T2	5		T4	631
valid_sources[0x4f]	258802	1			T4	628		T5	1023		T7	14
valid_sources[0x50]	275701	1			T4	667		T5	682		T6	6
valid_sources[0x51]	322279	1			T1	38		T4	657		T5	883
valid_sources[0x52]	346652	1			T4	633		T5	791		T6	10
valid_sources[0x53]	275896	1			T4	609		T5	905		T6	5
valid_sources[0x54]	336146	1			T2	5		T4	692		T5	891
valid_sources[0x55]	266674	1			T1	1491		T4	657		T5	798
valid_sources[0x56]	275155	1			T4	685		T5	788		T6	11
valid_sources[0x57]	291702	1			T4	626		T5	821		T7	26
valid_sources[0x58]	296883	1			T4	679		T5	644		T7	38
valid_sources[0x59]	293967	1			T4	645		T5	823		T6	13
valid_sources[0x5a]	291922	1			T2	3		T4	654		T5	911
valid_sources[0x5b]	346186	1			T4	657		T5	889		T6	6
valid_sources[0x5c]	363211	1			T4	626		T5	826		T6	8
valid_sources[0x5d]	271429	1			T4	656		T5	927		T7	35
valid_sources[0x5e]	255881	1			T2	9		T4	696		T5	773
valid_sources[0x5f]	328103	1			T2	1		T4	601		T5	901
valid_sources[0x60]	331143	1			T4	634		T5	718		T6	10
valid_sources[0x61]	286330	1			T2	13		T4	651		T5	889
valid_sources[0x62]	282271	1			T1	67		T2	3		T4	614
valid_sources[0x63]	353510	1			T2	10		T4	654		T5	1006
valid_sources[0x64]	369166	1			T2	7		T4	560		T5	881
valid_sources[0x65]	271725	1			T4	636		T5	780		T6	14
valid_sources[0x66]	290106	1			T4	664		T5	861		T6	4
valid_sources[0x67]	288975	1			T4	651		T5	896		T6	18
valid_sources[0x68]	287195	1			T4	670		T5	698		T6	12
valid_sources[0x69]	259722	1			T4	615		T5	766		T6	13
valid_sources[0x6a]	266407	1			T4	668		T5	920		T6	9
valid_sources[0x6b]	312924	1			T4	649		T5	905		T6	6
valid_sources[0x6c]	260496	1			T4	677		T5	926		T6	8
valid_sources[0x6d]	279940	1			T4	654		T5	775		T6	11
valid_sources[0x6e]	378774	1			T4	639		T5	737		T6	6
valid_sources[0x6f]	319938	1			T1	154		T4	628		T5	946
valid_sources[0x70]	320057	1			T4	664		T5	990		T7	37
valid_sources[0x71]	288508	1			T4	619		T5	784		T6	6
valid_sources[0x72]	268205	1			T2	2		T4	644		T5	845
valid_sources[0x73]	315905	1			T4	673		T5	816		T6	5
valid_sources[0x74]	299216	1			T2	5		T4	643		T5	763
valid_sources[0x75]	356874	1			T4	668		T5	917		T6	4
valid_sources[0x76]	355025	1			T1	1775		T4	629		T5	918
valid_sources[0x77]	324925	1			T4	663		T5	875		T7	43
valid_sources[0x78]	306338	1			T4	668		T5	789		T7	116
valid_sources[0x79]	321518	1			T2	7		T4	651		T5	840
valid_sources[0x7a]	344299	1			T2	1		T4	653		T5	884
valid_sources[0x7b]	274699	1			T4	627		T5	1020		T6	6
valid_sources[0x7c]	371278	1			T4	666		T5	725		T6	7
valid_sources[0x7d]	378993	1			T4	651		T5	1010		T6	7
valid_sources[0x7e]	324395	1			T1	47		T4	664		T5	835
valid_sources[0x7f]	281273	1			T1	245		T2	30		T4	673
valid_sources[0x80]	299336	1			T4	706		T5	966		T6	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

31381008

1

T1

61345

T2

2

T4

15178

values[0x0]

all_enables

biggest_size

15787428

1

T1

31151

T2

28

T4

7519

values[0x1]

all_enables

biggest_size

15792749

1

T1

30606

T2

24

T4

7520

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36989	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

127784

1

T1

22

T3

3

T7

28

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	48151	1			T1	17		T7	30		T6	21
values[0x0]	56330	1			T1	24		T2	2		T3	8
values[0x1]	60292	1			T1	20		T3	5		T4	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28183	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

136590

1

T1

25

T3

4

T7

35

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	771	1			T7	5		T15	2		T150	1
valid_sources[0x01]	558	1			T7	1		T68	1		T21	7
valid_sources[0x02]	633	1			T1	61		T15	1		T21	7
valid_sources[0x03]	679	1			T15	3		T11	3		T20	17
valid_sources[0x04]	525	1			T45	2		T21	4		T23	10
valid_sources[0x05]	560	1			T7	4		T15	5		T68	1
valid_sources[0x06]	537	1			T45	2		T21	26		T73	1
valid_sources[0x07]	649	1			T7	1		T150	1		T21	2
valid_sources[0x08]	607	1			T64	2		T21	11		T93	3
valid_sources[0x09]	550	1			T68	2		T78	2		T155	1
valid_sources[0x0a]	561	1			T18	1		T40	8		T150	1
valid_sources[0x0b]	888	1			T9	2		T15	1		T43	1
valid_sources[0x0c]	553	1			T40	3		T45	1		T21	1
valid_sources[0x0d]	730	1			T15	1		T45	1		T21	2
valid_sources[0x0e]	594	1			T43	2		T46	3		T23	9
valid_sources[0x0f]	777	1			T19	1		T43	3		T20	4
valid_sources[0x10]	817	1			T42	6		T18	1		T150	1
valid_sources[0x11]	730	1			T68	1		T21	9		T78	1
valid_sources[0x12]	650	1			T15	4		T43	2		T45	1
valid_sources[0x13]	750	1			T15	1		T40	6		T68	1
valid_sources[0x14]	655	1			T89	2		T20	13		T45	3
valid_sources[0x15]	539	1			T7	2		T40	6		T21	7
valid_sources[0x16]	845	1			T15	1		T68	1		T78	1
valid_sources[0x17]	693	1			T15	1		T19	1		T43	1
valid_sources[0x18]	731	1			T16	71		T45	1		T22	13
valid_sources[0x19]	665	1			T45	2		T17	8		T73	1
valid_sources[0x1a]	506	1			T18	2		T45	1		T21	4
valid_sources[0x1b]	747	1			T41	1		T150	1		T21	10
valid_sources[0x1c]	946	1			T39	44		T150	1		T21	9
valid_sources[0x1d]	638	1			T8	5		T68	1		T150	5
valid_sources[0x1e]	607	1			T151	1		T21	8		T156	1
valid_sources[0x1f]	509	1			T21	12		T44	1		T156	2
valid_sources[0x20]	647	1			T150	1		T21	11		T77	1
valid_sources[0x21]	616	1			T21	4		T157	1		T23	2
valid_sources[0x22]	498	1			T150	1		T21	2		T77	1
valid_sources[0x23]	525	1			T150	1		T21	1		T158	8
valid_sources[0x24]	552	1			T159	1		T23	2		T128	3
valid_sources[0x25]	603	1			T21	4		T160	1		T23	1
valid_sources[0x26]	557	1			T45	1		T150	3		T21	14
valid_sources[0x27]	510	1			T15	1		T43	5		T150	1
valid_sources[0x28]	654	1			T9	1		T15	1		T45	1
valid_sources[0x29]	540	1			T68	1		T21	1		T161	1
valid_sources[0x2a]	489	1			T150	4		T21	4		T78	1
valid_sources[0x2b]	457	1			T15	4		T18	1		T40	2
valid_sources[0x2c]	540	1			T15	2		T45	1		T148	3
valid_sources[0x2d]	597	1			T45	1		T21	12		T78	1
valid_sources[0x2e]	495	1			T7	1		T45	1		T17	14
valid_sources[0x2f]	587	1			T7	1		T21	2		T156	7
valid_sources[0x30]	711	1			T7	1		T43	1		T112	4
valid_sources[0x31]	598	1			T15	1		T68	1		T150	1
valid_sources[0x32]	571	1			T21	21		T155	1		T23	2
valid_sources[0x33]	772	1			T23	1		T69	13		T154	2
valid_sources[0x34]	541	1			T150	1		T21	3		T77	3
valid_sources[0x35]	463	1			T7	1		T15	6		T18	4
valid_sources[0x36]	726	1			T41	4		T20	24		T45	2
valid_sources[0x37]	497	1			T68	1		T21	8		T157	1
valid_sources[0x38]	567	1			T7	1		T17	7		T21	4
valid_sources[0x39]	511	1			T20	11		T150	1		T115	1
valid_sources[0x3a]	517	1			T21	11		T162	2		T23	1
valid_sources[0x3b]	813	1			T9	1		T15	2		T19	1
valid_sources[0x3c]	620	1			T40	10		T17	1		T21	6
valid_sources[0x3d]	562	1			T9	1		T150	2		T21	3
valid_sources[0x3e]	699	1			T15	1		T68	1		T21	10
valid_sources[0x3f]	550	1			T15	1		T68	1		T45	1
valid_sources[0x40]	732	1			T19	1		T150	1		T21	11
valid_sources[0x41]	627	1			T18	1		T68	2		T45	2
valid_sources[0x42]	415	1			T45	1		T21	13		T159	2
valid_sources[0x43]	572	1			T21	4		T161	1		T163	1
valid_sources[0x44]	500	1			T113	1		T150	1		T21	2
valid_sources[0x45]	900	1			T68	1		T20	17		T45	1
valid_sources[0x46]	921	1			T21	1		T78	1		T164	3
valid_sources[0x47]	697	1			T18	1		T157	1		T23	8
valid_sources[0x48]	768	1			T40	19		T45	1		T21	8
valid_sources[0x49]	592	1			T21	1		T164	1		T23	6
valid_sources[0x4a]	779	1			T8	3		T21	5		T22	74
valid_sources[0x4b]	724	1			T21	14		T23	6		T165	1
valid_sources[0x4c]	578	1			T15	4		T150	2		T151	1
valid_sources[0x4d]	612	1			T7	1		T19	1		T21	5
valid_sources[0x4e]	642	1			T15	2		T40	1		T45	2
valid_sources[0x4f]	590	1			T7	2		T15	1		T68	1
valid_sources[0x50]	650	1			T45	1		T151	4		T79	28
valid_sources[0x51]	630	1			T2	1		T17	3		T21	18
valid_sources[0x52]	562	1			T19	1		T45	1		T23	1
valid_sources[0x53]	661	1			T15	1		T45	1		T73	3
valid_sources[0x54]	733	1			T150	1		T21	27		T78	1
valid_sources[0x55]	807	1			T7	1		T15	2		T20	1
valid_sources[0x56]	834	1			T3	4		T21	1		T23	7
valid_sources[0x57]	660	1			T68	1		T45	1		T21	7
valid_sources[0x58]	863	1			T9	1		T15	1		T166	7
valid_sources[0x59]	649	1			T150	1		T151	1		T21	8
valid_sources[0x5a]	728	1			T68	3		T150	1		T21	8
valid_sources[0x5b]	775	1			T68	1		T17	4		T21	22
valid_sources[0x5c]	581	1			T6	41		T20	10		T150	1
valid_sources[0x5d]	477	1			T18	1		T21	16		T78	1
valid_sources[0x5e]	519	1			T164	1		T161	1		T23	1
valid_sources[0x5f]	657	1			T43	4		T21	10		T23	5
valid_sources[0x60]	541	1			T15	2		T21	6		T157	1
valid_sources[0x61]	750	1			T45	1		T151	4		T17	7
valid_sources[0x62]	480	1			T7	5		T150	1		T21	7
valid_sources[0x63]	458	1			T7	1		T15	5		T21	4
valid_sources[0x64]	577	1			T19	1		T45	1		T150	1
valid_sources[0x65]	620	1			T9	1		T150	3		T21	1
valid_sources[0x66]	527	1			T10	2		T150	2		T21	7
valid_sources[0x67]	622	1			T7	1		T68	1		T45	1
valid_sources[0x68]	596	1			T111	1		T45	1		T151	2
valid_sources[0x69]	691	1			T7	1		T18	2		T40	4
valid_sources[0x6a]	1081	1			T15	6		T68	1		T150	1
valid_sources[0x6b]	531	1			T19	1		T77	1		T167	2
valid_sources[0x6c]	815	1			T63	4		T166	2		T21	5
valid_sources[0x6d]	499	1			T15	1		T151	6		T161	1
valid_sources[0x6e]	428	1			T168	1		T21	7		T94	1
valid_sources[0x6f]	599	1			T8	2		T15	2		T68	1
valid_sources[0x70]	558	1			T19	1		T20	3		T21	5
valid_sources[0x71]	628	1			T7	1		T169	2		T170	2
valid_sources[0x72]	967	1			T7	1		T45	1		T21	11
valid_sources[0x73]	519	1			T116	1		T21	12		T126	1
valid_sources[0x74]	619	1			T68	3		T150	1		T21	23
valid_sources[0x75]	683	1			T15	2		T150	1		T21	5
valid_sources[0x76]	697	1			T15	1		T23	8		T131	2
valid_sources[0x77]	709	1			T40	1		T45	3		T171	2
valid_sources[0x78]	485	1			T43	1		T21	3		T78	1
valid_sources[0x79]	627	1			T45	1		T150	1		T21	11
valid_sources[0x7a]	796	1			T15	2		T161	1		T157	2
valid_sources[0x7b]	886	1			T68	1		T21	20		T155	1
valid_sources[0x7c]	680	1			T3	2		T150	1		T21	13
valid_sources[0x7d]	645	1			T45	1		T150	1		T21	1
valid_sources[0x7e]	1029	1			T15	2		T20	4		T161	1
valid_sources[0x7f]	534	1			T7	1		T21	1		T23	10
valid_sources[0x80]	500	1			T4	4		T15	6		T45	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

35376

1

T1

10

T7

18

T6

6

values[0x0]

all_enables

biggest_size

47504

1

T1

8

T3

3

T7

7

values[0x1]

all_enables

biggest_size

44904

1

T1

4

T7

3

T8

2