Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14453999

1

T1

10287

T2

868

T4

135665

full_word

57468655

1

T1

101501

T2

54

T4

30217

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	71922344	1			T1	111788		T2	922		T4	165882
auto[TlIntgErrCmd]	94	1			T60	6		T61	3		T62	2
auto[TlIntgErrData]	99	1			T60	4		T61	4		T62	4
auto[TlIntgErrBoth]	117	1			T61	3		T62	14		T137	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32873778

1

T1

44396

T2

339

T4

83047

auto[1]

39048876

1

T1

67392

T2

583

T4

82835

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6900292	1			T1	4054		T2	337		T4	67869
auto[TlIntgErrNone]	partial	auto[1]	7553412	1			T1	6233		T2	531		T4	67796
auto[TlIntgErrNone]	full_word	auto[0]	25973348	1			T1	40342		T2	2		T4	15178
auto[TlIntgErrNone]	full_word	auto[1]	31495292	1			T1	61159		T2	52		T4	15039
auto[TlIntgErrCmd]	partial	auto[0]	30	1			T60	3		T140	2		T137	2
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T60	3		T61	3		T62	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T141	1		T142	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T135	1		T143	1		-	-
auto[TlIntgErrData]	partial	auto[0]	44	1			T60	2		T61	1		T62	1
auto[TlIntgErrData]	partial	auto[1]	48	1			T60	2		T61	2		T62	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T61	1		T136	1		T144	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T134	1		T145	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	55	1			T61	2		T62	7		T137	1
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T61	1		T62	6		T137	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T146	1		T138	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T62	1		T135	1		-	-