Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	741483	1			T5	4299		T15	10043		T39	18
auto[1]	11144582	1			T1	9134		T4	70048		T5	13849
auto[2]	625686	1			T5	3149		T15	6554		T39	8
auto[3]	11036776	1			T1	9218		T4	69643		T5	12526

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	15105243	1			T1	15294		T4	4655		T5	504
auto[1]	2260077	1			T1	1455		T4	20796		T5	3481
auto[2]	2280435	1			T1	1462		T4	20987		T5	4571
auto[3]	3902772	1			T1	141		T4	93253		T5	25267

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9390392

1

T1

18341

T4

38

T7

853

auto[1]

14158135

1

T1

11

T4

139653

T5

33823

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	290323	1			T15	8295		T39	14		T18	1
auto[0]	auto[0]	auto[1]	30366	1			T15	816		T39	2		T40	2
auto[0]	auto[0]	auto[2]	30197	1			T15	830		T39	2		T40	3
auto[0]	auto[0]	auto[3]	9140	1			T15	88		T40	1		T16	13
auto[0]	auto[1]	auto[0]	3580977	1			T1	7597		T7	333		T6	3
auto[0]	auto[1]	auto[1]	371329	1			T1	716		T4	3		T7	39
auto[0]	auto[1]	auto[2]	361436	1			T1	743		T4	2		T7	32
auto[0]	auto[1]	auto[3]	73372	1			T1	71		T4	14		T7	9
auto[0]	auto[2]	auto[0]	244746	1			T15	5135		T39	7		T40	9
auto[0]	auto[2]	auto[1]	25237	1			T15	501		T16	109		T45	160
auto[0]	auto[2]	auto[2]	26883	1			T15	830		T39	1		T40	1
auto[0]	auto[2]	auto[3]	7747	1			T15	83		T16	13		T45	20
auto[0]	auto[3]	auto[0]	3536027	1			T1	7686		T4	2		T7	361
auto[0]	auto[3]	auto[1]	358144	1			T1	739		T4	4		T7	40
auto[0]	auto[3]	auto[2]	369596	1			T1	719		T4	4		T7	34
auto[0]	auto[3]	auto[3]	74872	1			T1	70		T4	9		T7	5
auto[1]	auto[0]	auto[0]	12862	1			T5	115		T15	12		T16	1
auto[1]	auto[0]	auto[1]	56820	1			T5	646		T15	1		T40	1
auto[1]	auto[0]	auto[2]	56666	1			T5	650		T15	1		T63	1
auto[1]	auto[0]	auto[3]	255109	1			T5	2888		T116	7750		T93	2
auto[1]	auto[1]	auto[0]	3717226	1			T1	7		T4	2346		T5	276
auto[1]	auto[1]	auto[1]	707133	1			T4	10462		T5	2297		T15	3
auto[1]	auto[1]	auto[2]	686909	1			T4	10672		T5	1255		T38	2
auto[1]	auto[1]	auto[3]	1646200	1			T4	46549		T5	10021		T15	2
auto[1]	auto[2]	auto[0]	9348	1			T15	5		T16	1		T45	4
auto[1]	auto[2]	auto[1]	40683	1			T116	989		T153	864		T154	1
auto[1]	auto[2]	auto[2]	49485	1			T5	572		T116	1871		T78	1
auto[1]	auto[2]	auto[3]	221557	1			T5	2577		T116	8460		T153	6809
auto[1]	auto[3]	auto[0]	3713734	1			T1	4		T4	2307		T5	113
auto[1]	auto[3]	auto[1]	670365	1			T4	10327		T5	538		T38	2
auto[1]	auto[3]	auto[2]	699263	1			T4	10309		T5	2094		T6	1
auto[1]	auto[3]	auto[3]	1614775	1			T4	46681		T5	9781		T41	66908