Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	328626537	187652	0	0
ctrl_regwen_rd_A	328626537	3898	0	0
exec_rd_A	328626537	3753	0	0
exec_regwen_rd_A	328626537	4286	0	0
readback_rd_A	328626537	2415	0	0
readback_regwen_rd_A	328626537	2344	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328626537	187652	0	0
T21	29271	2250	0	0
T22	93596	3495	0	0
T23	0	1274	0	0
T46	9812	0	0	0
T47	0	3434	0	0
T51	0	3292	0	0
T59	0	7468	0	0
T69	0	6672	0	0
T70	0	10197	0	0
T71	0	4021	0	0
T72	0	2270	0	0
T73	540403	0	0	0
T74	73888	0	0	0
T75	8691	0	0	0
T76	175586	0	0	0
T77	295826	0	0	0
T78	239749	0	0	0
T79	119785	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328626537	3898	0	0
T23	28345	77	0	0
T47	0	179	0	0
T71	0	249	0	0
T95	80265	0	0	0
T119	0	357	0	0
T120	0	92	0	0
T121	0	223	0	0
T122	0	171	0	0
T123	0	279	0	0
T124	0	225	0	0
T125	0	241	0	0
T126	469608	0	0	0
T127	408759	0	0	0
T128	540882	0	0	0
T129	228730	0	0	0
T130	104769	0	0	0
T131	1352	0	0	0
T132	699008	0	0	0
T133	141558	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328626537	3753	0	0
T23	28345	91	0	0
T47	0	133	0	0
T71	0	275	0	0
T95	80265	0	0	0
T119	0	448	0	0
T120	0	88	0	0
T121	0	129	0	0
T122	0	148	0	0
T123	0	206	0	0
T124	0	187	0	0
T125	0	244	0	0
T126	469608	0	0	0
T127	408759	0	0	0
T128	540882	0	0	0
T129	228730	0	0	0
T130	104769	0	0	0
T131	1352	0	0	0
T132	699008	0	0	0
T133	141558	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328626537	4286	0	0
T23	28345	130	0	0
T47	0	195	0	0
T71	0	307	0	0
T95	80265	0	0	0
T119	0	467	0	0
T120	0	128	0	0
T121	0	175	0	0
T122	0	106	0	0
T123	0	253	0	0
T124	0	192	0	0
T125	0	287	0	0
T126	469608	0	0	0
T127	408759	0	0	0
T128	540882	0	0	0
T129	228730	0	0	0
T130	104769	0	0	0
T131	1352	0	0	0
T132	699008	0	0	0
T133	141558	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328626537	2415	0	0
T23	28345	95	0	0
T47	0	134	0	0
T71	0	230	0	0
T95	80265	0	0	0
T119	0	361	0	0
T120	0	51	0	0
T121	0	153	0	0
T122	0	152	0	0
T123	0	190	0	0
T124	0	218	0	0
T125	0	236	0	0
T126	469608	0	0	0
T127	408759	0	0	0
T128	540882	0	0	0
T129	228730	0	0	0
T130	104769	0	0	0
T131	1352	0	0	0
T132	699008	0	0	0
T133	141558	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328626537	2344	0	0
T23	28345	113	0	0
T47	0	121	0	0
T71	0	175	0	0
T95	80265	0	0	0
T119	0	364	0	0
T120	0	91	0	0
T121	0	142	0	0
T122	0	119	0	0
T123	0	212	0	0
T124	0	181	0	0
T125	0	157	0	0
T126	469608	0	0	0
T127	408759	0	0	0
T128	540882	0	0	0
T129	228730	0	0	0
T130	104769	0	0	0
T131	1352	0	0	0
T132	699008	0	0	0
T133	141558	0	0	0