Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14166174	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

59531743

1

T1

4945

T2

113658

T3

151

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36735803	1			T1	2657		T2	62603		T3	75
values[0x0]	17063818	1			T1	1299		T2	29961		T3	42
values[0x1]	19898296	1			T1	1459		T2	32395		T3	54

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7057483	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

66640434

1

T1

5190

T2

119366

T3

157

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	275273	1			T1	21		T2	528		T11	11
valid_sources[0x01]	352988	1			T1	31		T2	437		T11	8
valid_sources[0x02]	267148	1			T1	28		T2	508		T11	2
valid_sources[0x03]	287731	1			T1	38		T2	481		T11	1
valid_sources[0x04]	309416	1			T1	17		T2	517		T11	2
valid_sources[0x05]	294038	1			T1	19		T2	459		T11	9
valid_sources[0x06]	272603	1			T1	32		T2	472		T11	6
valid_sources[0x07]	266270	1			T1	19		T2	520		T4	292
valid_sources[0x08]	296212	1			T1	20		T2	495		T11	10
valid_sources[0x09]	275719	1			T1	22		T2	484		T11	7
valid_sources[0x0a]	294020	1			T1	21		T2	534		T11	5
valid_sources[0x0b]	256249	1			T1	24		T2	522		T11	22
valid_sources[0x0c]	325706	1			T1	18		T2	485		T11	23
valid_sources[0x0d]	339339	1			T1	7		T2	448		T11	21
valid_sources[0x0e]	282315	1			T1	15		T2	534		T11	2
valid_sources[0x0f]	290114	1			T1	14		T2	449		T11	18
valid_sources[0x10]	282946	1			T1	5		T2	489		T4	599
valid_sources[0x11]	260383	1			T1	30		T2	471		T11	13
valid_sources[0x12]	274098	1			T1	25		T2	481		T11	17
valid_sources[0x13]	264929	1			T1	25		T2	509		T11	8
valid_sources[0x14]	291833	1			T1	13		T2	516		T11	19
valid_sources[0x15]	276732	1			T1	39		T2	473		T11	13
valid_sources[0x16]	332928	1			T1	8		T2	465		T11	19
valid_sources[0x17]	262425	1			T1	10		T2	482		T11	11
valid_sources[0x18]	255415	1			T1	20		T2	502		T11	33
valid_sources[0x19]	258441	1			T1	24		T2	500		T11	2
valid_sources[0x1a]	288859	1			T1	22		T2	463		T11	17
valid_sources[0x1b]	256821	1			T1	4		T2	503		T11	2
valid_sources[0x1c]	362023	1			T1	19		T2	529		T4	359
valid_sources[0x1d]	280116	1			T1	9		T2	522		T11	25
valid_sources[0x1e]	261955	1			T1	13		T2	471		T11	8
valid_sources[0x1f]	303384	1			T1	15		T2	502		T4	253
valid_sources[0x20]	352234	1			T1	14		T2	479		T11	7
valid_sources[0x21]	247989	1			T1	32		T2	483		T11	19
valid_sources[0x22]	251606	1			T1	13		T2	499		T11	42
valid_sources[0x23]	263962	1			T1	18		T2	488		T4	447
valid_sources[0x24]	259903	1			T1	31		T2	495		T11	15
valid_sources[0x25]	249205	1			T1	32		T2	501		T11	1
valid_sources[0x26]	307971	1			T1	9		T2	458		T11	14
valid_sources[0x27]	291609	1			T1	26		T2	519		T11	18
valid_sources[0x28]	279513	1			T1	39		T2	485		T11	5
valid_sources[0x29]	267954	1			T1	30		T2	552		T11	9
valid_sources[0x2a]	292241	1			T1	32		T2	469		T11	18
valid_sources[0x2b]	262329	1			T1	14		T2	483		T11	49
valid_sources[0x2c]	252942	1			T1	12		T2	505		T11	5
valid_sources[0x2d]	274978	1			T1	31		T2	475		T11	5
valid_sources[0x2e]	325599	1			T1	10		T2	489		T11	7
valid_sources[0x2f]	282699	1			T1	10		T2	476		T11	6
valid_sources[0x30]	282322	1			T1	33		T2	464		T4	534
valid_sources[0x31]	270729	1			T1	17		T2	476		T4	388
valid_sources[0x32]	287641	1			T1	9		T2	521		T11	17
valid_sources[0x33]	288150	1			T1	23		T2	500		T11	13
valid_sources[0x34]	290566	1			T1	25		T2	488		T4	384
valid_sources[0x35]	345735	1			T1	14		T2	500		T11	4
valid_sources[0x36]	440197	1			T1	28		T2	518		T11	7
valid_sources[0x37]	251506	1			T1	25		T2	487		T11	2
valid_sources[0x38]	284172	1			T1	20		T2	481		T4	552
valid_sources[0x39]	271369	1			T1	28		T2	514		T11	11
valid_sources[0x3a]	361555	1			T1	16		T2	508		T11	11
valid_sources[0x3b]	273006	1			T1	13		T2	502		T11	3
valid_sources[0x3c]	272850	1			T1	22		T2	540		T11	4
valid_sources[0x3d]	285986	1			T1	14		T2	453		T11	39
valid_sources[0x3e]	298936	1			T1	20		T2	475		T11	10
valid_sources[0x3f]	283753	1			T1	21		T2	457		T11	2
valid_sources[0x40]	283802	1			T1	12		T2	461		T11	23
valid_sources[0x41]	273884	1			T1	2		T2	515		T11	18
valid_sources[0x42]	307207	1			T1	40		T2	502		T11	21
valid_sources[0x43]	292278	1			T1	12		T2	466		T11	42
valid_sources[0x44]	290110	1			T1	24		T2	460		T11	25
valid_sources[0x45]	294949	1			T1	31		T2	498		T4	492
valid_sources[0x46]	304543	1			T1	20		T2	514		T11	34
valid_sources[0x47]	311960	1			T1	27		T2	487		T11	2
valid_sources[0x48]	278991	1			T1	50		T2	487		T11	21
valid_sources[0x49]	267194	1			T1	18		T2	484		T11	4
valid_sources[0x4a]	312695	1			T1	10		T2	526		T4	321
valid_sources[0x4b]	257136	1			T1	9		T2	477		T11	5
valid_sources[0x4c]	269094	1			T1	23		T2	467		T11	9
valid_sources[0x4d]	268199	1			T1	12		T2	498		T11	45
valid_sources[0x4e]	257704	1			T1	59		T2	507		T11	24
valid_sources[0x4f]	320307	1			T1	12		T2	479		T4	483
valid_sources[0x50]	314155	1			T1	10		T2	505		T4	332
valid_sources[0x51]	272014	1			T1	6		T2	483		T11	10
valid_sources[0x52]	253740	1			T1	21		T2	460		T11	4
valid_sources[0x53]	291293	1			T1	28		T2	515		T11	20
valid_sources[0x54]	269289	1			T1	27		T2	472		T11	17
valid_sources[0x55]	252781	1			T1	9		T2	494		T11	6
valid_sources[0x56]	252833	1			T1	6		T2	477		T11	8
valid_sources[0x57]	275872	1			T1	21		T2	478		T11	16
valid_sources[0x58]	335717	1			T1	25		T2	464		T11	1
valid_sources[0x59]	313662	1			T1	26		T2	469		T11	2
valid_sources[0x5a]	300876	1			T1	6		T2	436		T11	2
valid_sources[0x5b]	279235	1			T1	48		T2	493		T11	9
valid_sources[0x5c]	404947	1			T1	32		T2	465		T11	3
valid_sources[0x5d]	268615	1			T1	22		T2	483		T11	31
valid_sources[0x5e]	302907	1			T1	22		T2	503		T11	21
valid_sources[0x5f]	278058	1			T1	28		T2	509		T11	2
valid_sources[0x60]	294109	1			T1	4		T2	503		T4	401
valid_sources[0x61]	257768	1			T1	40		T2	510		T4	506
valid_sources[0x62]	261583	1			T1	21		T2	483		T11	2
valid_sources[0x63]	322154	1			T1	18		T2	492		T11	31
valid_sources[0x64]	263288	1			T1	34		T2	508		T11	41
valid_sources[0x65]	261477	1			T1	30		T2	475		T11	5
valid_sources[0x66]	267578	1			T1	7		T2	503		T11	32
valid_sources[0x67]	306038	1			T1	30		T2	495		T11	12
valid_sources[0x68]	261943	1			T1	25		T2	463		T11	4
valid_sources[0x69]	320832	1			T1	22		T2	449		T11	28
valid_sources[0x6a]	319416	1			T1	9		T2	485		T11	11
valid_sources[0x6b]	322405	1			T1	19		T2	469		T4	377
valid_sources[0x6c]	313744	1			T1	19		T2	482		T11	14
valid_sources[0x6d]	297052	1			T1	36		T2	511		T4	740
valid_sources[0x6e]	290133	1			T1	25		T2	461		T11	5
valid_sources[0x6f]	279387	1			T1	31		T2	491		T11	14
valid_sources[0x70]	293981	1			T1	44		T2	506		T11	22
valid_sources[0x71]	262505	1			T1	16		T2	517		T11	9
valid_sources[0x72]	275609	1			T1	21		T2	494		T11	3
valid_sources[0x73]	277078	1			T1	35		T2	506		T4	527
valid_sources[0x74]	271124	1			T1	30		T2	498		T11	14
valid_sources[0x75]	252943	1			T1	26		T2	474		T11	15
valid_sources[0x76]	271134	1			T1	24		T2	458		T11	46
valid_sources[0x77]	259454	1			T1	16		T2	469		T11	10
valid_sources[0x78]	278255	1			T1	45		T2	454		T11	18
valid_sources[0x79]	292221	1			T1	8		T2	508		T11	2
valid_sources[0x7a]	297519	1			T1	15		T2	469		T11	4
valid_sources[0x7b]	307140	1			T1	19		T2	519		T11	12
valid_sources[0x7c]	295113	1			T1	20		T2	511		T11	6
valid_sources[0x7d]	269882	1			T1	3		T2	468		T11	2
valid_sources[0x7e]	269067	1			T1	24		T2	462		T11	9
valid_sources[0x7f]	259723	1			T1	13		T2	469		T11	3
valid_sources[0x80]	260762	1			T1	28		T2	493		T11	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29660101

1

T1

2426

T2

56908

T3

66

values[0x0]

all_enables

biggest_size

14937047

1

T1

1231

T2

28290

T3

37

values[0x1]

all_enables

biggest_size

14934595

1

T1

1288

T2

28460

T3

48

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	37468	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

149139

1

T2

2

T11

1

T4

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	53288	1			T25	16		T19	41		T7	127
values[0x0]	64396	1			T1	1		T2	5		T11	1
values[0x1]	68923	1			T2	5		T3	1		T10	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28083	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

158524

1

T2

2

T11

1

T4

5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	703	1			T23	1		T21	1		T26	10
valid_sources[0x01]	526	1			T19	3		T7	3		T23	5
valid_sources[0x02]	892	1			T12	4		T7	3		T23	1
valid_sources[0x03]	708	1			T25	4		T7	3		T23	2
valid_sources[0x04]	556	1			T19	1		T7	5		T60	3
valid_sources[0x05]	808	1			T4	1		T19	1		T23	3
valid_sources[0x06]	699	1			T7	1		T23	5		T26	21
valid_sources[0x07]	737	1			T7	2		T23	2		T9	2
valid_sources[0x08]	695	1			T7	4		T45	2		T23	5
valid_sources[0x09]	712	1			T25	1		T19	2		T7	11
valid_sources[0x0a]	704	1			T25	3		T23	3		T26	12
valid_sources[0x0b]	808	1			T19	1		T7	4		T23	4
valid_sources[0x0c]	593	1			T7	2		T21	1		T63	9
valid_sources[0x0d]	596	1			T19	2		T23	10		T61	1
valid_sources[0x0e]	745	1			T4	1		T23	4		T42	2
valid_sources[0x0f]	761	1			T19	5		T23	2		T65	1
valid_sources[0x10]	1025	1			T7	10		T23	10		T65	1
valid_sources[0x11]	1276	1			T7	1		T45	2		T23	1
valid_sources[0x12]	457	1			T7	4		T23	6		T26	9
valid_sources[0x13]	858	1			T19	1		T23	7		T42	1
valid_sources[0x14]	722	1			T25	1		T19	2		T7	1
valid_sources[0x15]	547	1			T19	1		T7	2		T23	4
valid_sources[0x16]	831	1			T19	1		T7	2		T23	2
valid_sources[0x17]	677	1			T19	1		T7	1		T23	2
valid_sources[0x18]	1408	1			T7	2		T23	6		T8	1
valid_sources[0x19]	676	1			T19	2		T23	2		T26	17
valid_sources[0x1a]	545	1			T23	3		T43	1		T26	13
valid_sources[0x1b]	1052	1			T19	2		T23	5		T26	9
valid_sources[0x1c]	612	1			T23	5		T21	1		T26	13
valid_sources[0x1d]	812	1			T25	1		T7	3		T23	10
valid_sources[0x1e]	672	1			T19	1		T23	1		T26	12
valid_sources[0x1f]	622	1			T23	4		T42	1		T26	13
valid_sources[0x20]	809	1			T73	1		T7	2		T23	6
valid_sources[0x21]	603	1			T23	8		T26	10		T148	2
valid_sources[0x22]	753	1			T7	2		T23	4		T65	5
valid_sources[0x23]	839	1			T19	1		T23	3		T8	1
valid_sources[0x24]	965	1			T25	4		T19	2		T23	5
valid_sources[0x25]	538	1			T7	2		T23	8		T42	1
valid_sources[0x26]	508	1			T19	2		T7	3		T23	5
valid_sources[0x27]	700	1			T4	1		T19	1		T7	1
valid_sources[0x28]	657	1			T19	1		T7	1		T23	3
valid_sources[0x29]	665	1			T25	1		T19	2		T23	1
valid_sources[0x2a]	670	1			T7	6		T23	7		T8	1
valid_sources[0x2b]	657	1			T7	1		T23	5		T43	1
valid_sources[0x2c]	651	1			T3	1		T19	1		T23	1
valid_sources[0x2d]	543	1			T25	2		T19	2		T7	4
valid_sources[0x2e]	882	1			T23	4		T26	23		T99	4
valid_sources[0x2f]	574	1			T23	15		T8	2		T90	17
valid_sources[0x30]	857	1			T19	1		T7	6		T23	4
valid_sources[0x31]	887	1			T7	2		T23	3		T65	1
valid_sources[0x32]	579	1			T7	5		T23	2		T8	1
valid_sources[0x33]	506	1			T19	1		T7	2		T23	5
valid_sources[0x34]	963	1			T23	5		T26	19		T16	2
valid_sources[0x35]	671	1			T11	1		T25	9		T19	1
valid_sources[0x36]	662	1			T23	3		T26	10		T49	1
valid_sources[0x37]	693	1			T19	2		T7	1		T23	9
valid_sources[0x38]	613	1			T25	2		T19	2		T7	1
valid_sources[0x39]	593	1			T23	10		T65	12		T26	6
valid_sources[0x3a]	1018	1			T7	1		T23	3		T26	16
valid_sources[0x3b]	568	1			T19	2		T23	2		T43	1
valid_sources[0x3c]	772	1			T23	11		T65	3		T26	13
valid_sources[0x3d]	722	1			T25	2		T19	1		T7	7
valid_sources[0x3e]	590	1			T23	4		T43	2		T21	1
valid_sources[0x3f]	589	1			T2	1		T5	1		T13	3
valid_sources[0x40]	635	1			T7	2		T23	4		T26	6
valid_sources[0x41]	557	1			T19	1		T7	1		T23	2
valid_sources[0x42]	572	1			T4	1		T25	1		T19	1
valid_sources[0x43]	970	1			T19	1		T7	3		T23	2
valid_sources[0x44]	792	1			T25	1		T19	1		T7	1
valid_sources[0x45]	747	1			T2	1		T7	2		T23	3
valid_sources[0x46]	556	1			T19	1		T7	1		T23	2
valid_sources[0x47]	645	1			T19	2		T23	3		T60	2
valid_sources[0x48]	589	1			T19	2		T74	2		T23	4
valid_sources[0x49]	835	1			T4	1		T19	2		T7	4
valid_sources[0x4a]	672	1			T19	1		T23	2		T65	1
valid_sources[0x4b]	913	1			T7	3		T23	3		T26	12
valid_sources[0x4c]	940	1			T19	1		T23	2		T21	1
valid_sources[0x4d]	914	1			T19	1		T23	6		T26	11
valid_sources[0x4e]	550	1			T19	1		T23	1		T26	10
valid_sources[0x4f]	690	1			T19	4		T23	5		T26	9
valid_sources[0x50]	895	1			T7	1		T23	1		T8	2
valid_sources[0x51]	562	1			T7	7		T23	3		T21	1
valid_sources[0x52]	787	1			T19	2		T7	3		T23	5
valid_sources[0x53]	632	1			T19	1		T7	1		T23	4
valid_sources[0x54]	807	1			T19	1		T23	7		T26	11
valid_sources[0x55]	888	1			T7	1		T23	5		T42	1
valid_sources[0x56]	785	1			T2	1		T19	1		T23	8
valid_sources[0x57]	768	1			T19	1		T7	1		T23	3
valid_sources[0x58]	742	1			T7	1		T23	3		T8	1
valid_sources[0x59]	595	1			T19	3		T7	4		T23	6
valid_sources[0x5a]	773	1			T19	2		T7	1		T23	1
valid_sources[0x5b]	666	1			T19	2		T7	3		T23	3
valid_sources[0x5c]	771	1			T19	1		T23	7		T65	2
valid_sources[0x5d]	941	1			T19	1		T23	4		T42	1
valid_sources[0x5e]	554	1			T7	1		T23	3		T42	1
valid_sources[0x5f]	627	1			T13	3		T7	9		T23	4
valid_sources[0x60]	971	1			T6	2		T19	1		T23	7
valid_sources[0x61]	639	1			T1	1		T19	1		T23	5
valid_sources[0x62]	902	1			T25	3		T23	2		T8	1
valid_sources[0x63]	549	1			T7	1		T23	2		T26	13
valid_sources[0x64]	633	1			T19	3		T23	4		T43	1
valid_sources[0x65]	1124	1			T7	1		T23	2		T26	23
valid_sources[0x66]	640	1			T19	1		T7	1		T23	8
valid_sources[0x67]	562	1			T19	1		T7	2		T23	2
valid_sources[0x68]	699	1			T23	7		T14	1		T26	13
valid_sources[0x69]	626	1			T23	4		T26	18		T149	1
valid_sources[0x6a]	931	1			T23	1		T42	1		T21	1
valid_sources[0x6b]	946	1			T23	6		T22	1		T26	12
valid_sources[0x6c]	641	1			T7	1		T23	7		T42	1
valid_sources[0x6d]	769	1			T23	5		T42	1		T21	1
valid_sources[0x6e]	816	1			T2	1		T19	1		T23	4
valid_sources[0x6f]	642	1			T19	1		T23	2		T60	1
valid_sources[0x70]	548	1			T19	5		T7	1		T43	1
valid_sources[0x71]	616	1			T4	1		T7	6		T23	6
valid_sources[0x72]	1200	1			T7	4		T23	8		T65	1
valid_sources[0x73]	585	1			T23	1		T26	10		T148	2
valid_sources[0x74]	763	1			T19	1		T7	3		T23	5
valid_sources[0x75]	767	1			T19	1		T7	2		T21	1
valid_sources[0x76]	781	1			T7	1		T23	8		T65	2
valid_sources[0x77]	650	1			T25	2		T19	3		T23	5
valid_sources[0x78]	710	1			T4	1		T19	1		T7	4
valid_sources[0x79]	734	1			T19	1		T7	4		T23	5
valid_sources[0x7a]	922	1			T4	1		T19	1		T23	2
valid_sources[0x7b]	639	1			T19	2		T7	1		T23	1
valid_sources[0x7c]	1020	1			T19	2		T7	1		T23	6
valid_sources[0x7d]	614	1			T19	2		T7	3		T23	2
valid_sources[0x7e]	716	1			T5	1		T19	2		T23	7
valid_sources[0x7f]	640	1			T7	1		T23	9		T26	13
valid_sources[0x80]	684	1			T19	1		T7	8		T23	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

40473

1

T25

6

T19

16

T7

66

values[0x0]

all_enables

biggest_size

55677

1

T2

1

T4

2

T5

1

values[0x1]

all_enables

biggest_size

52989

1

T2

1

T11

1

T4

1