Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13846079

1

T1

470

T2

9056

T3

20

full_word

54213737

1

T1

4945

T2

90856

T3

151

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	68059516	1			T1	5415		T2	99912		T3	171
auto[TlIntgErrCmd]	96	1			T67	4		T68	7		T69	2
auto[TlIntgErrData]	98	1			T67	4		T68	8		T69	3
auto[TlIntgErrBoth]	106	1			T67	2		T68	5		T69	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31004902

1

T1

2657

T2

37556

T3

75

auto[1]

37054914

1

T1

2758

T2

62356

T3

96

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6593681	1			T1	231		T2	3450		T3	9
auto[TlIntgErrNone]	partial	auto[1]	7252118	1			T1	239		T2	5606		T3	11
auto[TlIntgErrNone]	full_word	auto[0]	24411083	1			T1	2426		T2	34106		T3	66
auto[TlIntgErrNone]	full_word	auto[1]	29802634	1			T1	2519		T2	56750		T3	85
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T67	3		T68	3		T132	3
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T67	1		T68	3		T69	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T139	1		T140	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T68	1		T133	1		T141	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T67	2		T68	3		T69	1
auto[TlIntgErrData]	partial	auto[1]	48	1			T67	2		T68	3		T69	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T68	2		T137	1		T142	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T143	1		T135	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T67	1		T68	2		T69	1
auto[TlIntgErrBoth]	partial	auto[1]	61	1			T67	1		T68	3		T69	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T132	1		T134	1		T144	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T69	1		T132	1		-	-