Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	643979	1			T2	16		T4	212		T5	732
auto[1]	10037029	1			T2	226		T4	1616		T6	53305
auto[2]	531092	1			T2	16		T4	94		T5	547
auto[3]	9935104	1			T2	237		T4	1452		T6	53063

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13666838	1			T2	350		T4	2398		T6	88587
auto[1]	2016632	1			T2	46		T4	373		T6	8466
auto[2]	2046263	1			T2	88		T4	539		T6	8498
auto[3]	3417471	1			T2	11		T4	64		T6	817

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8227021

1

T2

495

T4

3370

T6

41

auto[1]

12920183

1

T4

4

T6

106327

T5

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	247533	1			T2	11		T4	168		T5	25
auto[0]	auto[0]	auto[1]	25488	1			T2	1		T4	22		T5	121
auto[0]	auto[0]	auto[2]	25345	1			T2	4		T4	20		T5	108
auto[0]	auto[0]	auto[3]	7184	1			T4	2		T5	478		T20	4
auto[0]	auto[1]	auto[0]	3142249	1			T2	171		T4	1235		T6	16
auto[0]	auto[1]	auto[1]	327762	1			T2	33		T4	225		T6	1
auto[0]	auto[1]	auto[2]	318962	1			T2	19		T4	132		T6	3
auto[0]	auto[1]	auto[3]	68474	1			T2	3		T4	22		T5	508
auto[0]	auto[2]	auto[0]	202569	1			T5	30		T20	838		T8	4
auto[0]	auto[2]	auto[1]	20878	1			T5	114		T20	76		T60	2
auto[0]	auto[2]	auto[2]	24668	1			T2	13		T4	82		T5	77
auto[0]	auto[2]	auto[3]	5799	1			T2	3		T4	12		T5	326
auto[0]	auto[3]	auto[0]	3097500	1			T2	168		T4	992		T6	18
auto[0]	auto[3]	auto[1]	315129	1			T2	12		T4	126		T6	2
auto[0]	auto[3]	auto[2]	328491	1			T2	52		T4	304		T6	1
auto[0]	auto[3]	auto[3]	68990	1			T2	5		T4	28		T5	292
auto[1]	auto[0]	auto[0]	11475	1			T28	412		T73	116		T20	1
auto[1]	auto[0]	auto[1]	50740	1			T28	1657		T73	521		T20	1
auto[1]	auto[0]	auto[2]	49994	1			T28	1629		T73	488		T40	2338
auto[1]	auto[0]	auto[3]	226220	1			T28	7213		T73	2341		T40	10663
auto[1]	auto[1]	auto[0]	3479094	1			T4	2		T6	44393		T12	79091
auto[1]	auto[1]	auto[1]	640244	1			T6	4034		T12	7199		T28	1801
auto[1]	auto[1]	auto[2]	622721	1			T6	4459		T12	7903		T28	1046
auto[1]	auto[1]	auto[3]	1437523	1			T6	399		T12	674		T28	8433
auto[1]	auto[2]	auto[0]	7257	1			T28	222		T20	1		T40	308
auto[1]	auto[2]	auto[1]	32193	1			T28	1031		T40	1466		T147	1
auto[1]	auto[2]	auto[2]	43280	1			T28	1537		T73	466		T20	1
auto[1]	auto[2]	auto[3]	194448	1			T28	6854		T73	2119		T40	10227
auto[1]	auto[3]	auto[0]	3479161	1			T4	1		T6	44160		T12	79328
auto[1]	auto[3]	auto[1]	604198	1			T6	4429		T12	7915		T24	1
auto[1]	auto[3]	auto[2]	632802	1			T4	1		T6	4035		T12	7055
auto[1]	auto[3]	auto[3]	1408833	1			T6	418		T5	1		T12	676