Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	328401995	228924	0	0
ctrl_regwen_rd_A	328401995	3014	0	0
exec_rd_A	328401995	3099	0	0
exec_regwen_rd_A	328401995	3268	0	0
readback_rd_A	328401995	1908	0	0
readback_regwen_rd_A	328401995	1534	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328401995	228924	0	0
T8	38774	0	0	0
T9	33281	0	0	0
T14	1051	0	0	0
T23	21566	1395	0	0
T26	0	5493	0	0
T27	0	3340	0	0
T29	2137	0	0	0
T30	2204	0	0	0
T42	548940	0	0	0
T43	350537	0	0	0
T48	0	4045	0	0
T53	0	4403	0	0
T64	0	11076	0	0
T65	894537	0	0	0
T66	276228	0	0	0
T76	0	1580	0	0
T77	0	1566	0	0
T78	0	13663	0	0
T79	0	11417	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328401995	3014	0	0
T48	0	284	0	0
T76	75619	103	0	0
T77	0	147	0	0
T116	0	156	0	0
T117	0	364	0	0
T118	0	81	0	0
T119	0	94	0	0
T120	0	116	0	0
T121	0	304	0	0
T122	0	110	0	0
T123	28886	0	0	0
T124	23297	0	0	0
T125	217959	0	0	0
T126	1996	0	0	0
T127	1083	0	0	0
T128	114303	0	0	0
T129	131843	0	0	0
T130	280078	0	0	0
T131	263208	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328401995	3099	0	0
T48	0	291	0	0
T76	75619	106	0	0
T77	0	108	0	0
T116	0	163	0	0
T117	0	485	0	0
T118	0	55	0	0
T119	0	56	0	0
T120	0	91	0	0
T121	0	201	0	0
T122	0	90	0	0
T123	28886	0	0	0
T124	23297	0	0	0
T125	217959	0	0	0
T126	1996	0	0	0
T127	1083	0	0	0
T128	114303	0	0	0
T129	131843	0	0	0
T130	280078	0	0	0
T131	263208	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328401995	3268	0	0
T48	0	239	0	0
T76	75619	102	0	0
T77	0	106	0	0
T116	0	165	0	0
T117	0	590	0	0
T118	0	55	0	0
T119	0	90	0	0
T120	0	132	0	0
T121	0	299	0	0
T122	0	116	0	0
T123	28886	0	0	0
T124	23297	0	0	0
T125	217959	0	0	0
T126	1996	0	0	0
T127	1083	0	0	0
T128	114303	0	0	0
T129	131843	0	0	0
T130	280078	0	0	0
T131	263208	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328401995	1908	0	0
T48	0	311	0	0
T76	75619	114	0	0
T77	0	123	0	0
T116	0	122	0	0
T117	0	512	0	0
T118	0	28	0	0
T119	0	55	0	0
T120	0	74	0	0
T121	0	232	0	0
T122	0	165	0	0
T123	28886	0	0	0
T124	23297	0	0	0
T125	217959	0	0	0
T126	1996	0	0	0
T127	1083	0	0	0
T128	114303	0	0	0
T129	131843	0	0	0
T130	280078	0	0	0
T131	263208	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328401995	1534	0	0
T48	0	236	0	0
T76	75619	108	0	0
T77	0	103	0	0
T116	0	93	0	0
T117	0	377	0	0
T118	0	45	0	0
T119	0	49	0	0
T120	0	77	0	0
T121	0	217	0	0
T122	0	90	0	0
T123	28886	0	0	0
T124	23297	0	0	0
T125	217959	0	0	0
T126	1996	0	0	0
T127	1083	0	0	0
T128	114303	0	0	0
T129	131843	0	0	0
T130	280078	0	0	0
T131	263208	0	0	0