Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	151424526	1			T2	2826		T3	1276		T4	1876
instr_valid_dis	116039940	1			T2	2826		T3	1276		T4	1876
instr_en	24512110	1			T21	2626		T17	6066		T18	5054

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	13045850	1			T18	524		T19	16188		T36	83230
sram_ifetch_valid_disable	114951248	1			T2	2826		T3	1276		T4	1876
sram_ifetch_enable	23427428	1			T17	452		T22	1320		T19	10484

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	151424526	1			T2	2826		T3	1276		T4	1876
hw_debug_en_valid_off	115074614	1			T2	2826		T3	1276		T4	1876
hw_debug_en_on	24830023	1			T17	5614		T18	524		T19	10484

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	114951248	1			T2	2826		T3	1276		T4	1876
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	101218657	1			T2	2826		T3	1276		T4	1876
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9890491	1			T21	2626		T17	5614		T18	4530
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5238328	1			T19	16188		T36	60		T129	18922
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1554956	1			T19	16188		T124	1298		T125	15452
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2663964	1			T36	60		T130	4290		T59	10272
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4988028	1			T18	524		T52	20000		T129	3430
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2473040	1			T52	20000		T129	3430		T58	16616
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1750698	1			T18	524		T48	18420		T126	3762
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	10593067	1			T17	5614		T52	42582		T129	7088
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4077107	1			T129	7088		T59	2876		T37	25826
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4823660	1			T17	5614		T59	9982		T125	109650

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9120385	1			T17	452		T19	10484		T129	62236
lc_exec_en	9248928	1			T19	10484		T36	22124		T130	119530
valid_exec_dis	109562923	1			T2	2826		T3	1276		T4	1876
invalid_exec_dis	36473278	1			T17	452		T18	524		T22	1320