Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	146233026	1			T2	2652		T4	6142		T5	1846
instr_valid_dis	110205087	1			T2	2652		T4	6142		T5	1846
instr_en	25888655	1			T19	24452		T20	7898		T57	39190

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10865876	1			T57	68		T21	20000		T35	20000
sram_ifetch_valid_disable	111422194	1			T2	2652		T4	6142		T5	1846
sram_ifetch_enable	23944956	1			T19	24452		T20	440		T57	4640

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	146233026	1			T2	2652		T4	6142		T5	1846
hw_debug_en_valid_off	110608155	1			T2	2652		T4	6142		T5	1846
hw_debug_en_on	23577315	1			T20	440		T57	39190		T21	20000

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	111422194	1			T2	2652		T4	6142		T5	1846
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	96028311	1			T2	2652		T4	6142		T5	1846
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	11197851	1			T20	7458		T57	39190		T129	15532
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4182272	1			T126	22762		T55	116802		T133	13876
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1447760	1			T133	13876		T51	48338		T64	9918
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1847812	1			T126	22762		T127	42		T128	92
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4755486	1			T21	20000		T134	25250		T55	37056
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1935104	1			T127	14216		T136	29434		T130	25510
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2185982	1			T21	20000		T134	40		T133	27496
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9723096	1			T57	39190		T35	25886		T125	115970
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3429228	1			T125	115176		T126	13818		T134	36238
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4536886	1			T57	39190		T125	794		T134	36086

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10090268	1			T19	24452		T20	440		T125	52644
lc_exec_en	9098733	1			T20	440		T35	94386		T48	16372
valid_exec_dis	107423873	1			T2	2652		T4	6142		T5	1846
invalid_exec_dis	34810832	1			T19	24452		T20	440		T57	4708