Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44


Total tests in report: 1028
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
85.75 85.75 96.69 96.69 81.87 81.87 95.80 95.80 90.48 90.48 88.89 88.89 94.40 94.40 52.10 52.10 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.460230221
89.55 3.80 98.05 1.36 84.83 2.96 97.05 1.25 100.00 9.52 92.27 3.38 95.58 1.18 59.05 6.95 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.1891284539
92.57 3.02 98.56 0.51 86.97 2.13 97.05 0.00 100.00 0.00 93.24 0.97 95.58 0.00 76.60 17.55 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1131693882
93.92 1.35 98.81 0.25 89.22 2.25 97.33 0.28 100.00 0.00 95.17 1.93 95.58 0.00 81.35 4.75 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all.3994413149
94.71 0.79 98.81 0.00 89.81 0.59 97.33 0.00 100.00 0.00 95.17 0.00 95.58 0.00 86.29 4.94 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1174462701
95.35 0.64 98.81 0.00 89.93 0.12 97.33 0.00 100.00 0.00 95.41 0.24 96.76 1.18 89.21 2.93 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.3861085608
95.79 0.44 98.81 0.00 89.93 0.00 97.33 0.00 100.00 0.00 95.41 0.00 96.90 0.15 92.14 2.93 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.4203442905
96.10 0.31 98.81 0.00 90.17 0.24 97.33 0.00 100.00 0.00 95.89 0.48 97.64 0.74 92.87 0.73 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2359371630
96.39 0.28 98.81 0.00 90.40 0.24 98.75 1.42 100.00 0.00 95.89 0.00 97.79 0.15 93.05 0.18 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.3686905992
96.60 0.22 98.81 0.00 90.64 0.24 98.75 0.00 100.00 0.00 95.89 0.00 97.79 0.00 94.33 1.28 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all.3236354995
96.80 0.20 98.81 0.00 90.64 0.00 98.82 0.07 100.00 0.00 95.89 0.00 99.12 1.33 94.33 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.704155627
96.96 0.16 98.81 0.00 90.64 0.00 98.82 0.00 100.00 0.00 95.89 0.00 99.12 0.00 95.43 1.10 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all.316439834
97.09 0.13 98.90 0.08 90.64 0.00 99.65 0.83 100.00 0.00 95.89 0.00 99.12 0.00 95.43 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.4294941924
97.21 0.12 99.15 0.25 90.64 0.00 99.65 0.00 100.00 0.00 96.14 0.24 99.12 0.00 95.80 0.37 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.3371433626
97.32 0.10 99.15 0.00 90.64 0.00 99.65 0.00 100.00 0.00 96.14 0.00 99.12 0.00 96.53 0.73 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1432366525
97.38 0.06 99.15 0.00 91.00 0.36 99.72 0.07 100.00 0.00 96.14 0.00 99.12 0.00 96.53 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.2754611455
97.43 0.05 99.15 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.14 0.00 99.12 0.00 96.89 0.37 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.418379695
97.48 0.05 99.15 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.14 0.00 99.12 0.00 97.26 0.37 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2543018267
97.51 0.03 99.15 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.14 0.00 99.12 0.00 97.44 0.18 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_executable.1381975035

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1710386232
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2423655591
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1631003656
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.125236559
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3676292565
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.554628380
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2347356766
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1707072861
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.305243577
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2612251350
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2082994015
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1758043431
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.296669578
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.120790297
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3676304888
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.326270968
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1577650008
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.580509248
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1379281770
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3806292403
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.473372957
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2763297310
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.262183101
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1125136653
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1965880951
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3739677577
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2631184906
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3905685626
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1660364232
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2573048973
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3774018054
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3380131904
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3285399026
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1836309596
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3064852802
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2198835679
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2756949383
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2073938765
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2674828523
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.687593685
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3112022659
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3370523210
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1323460101
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1845678171
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1288802654
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.349841993
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.4173970399
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3181112496
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2597803817
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1635923909
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.330586772
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2932680076
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2085909295
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.771391306
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.201812658
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3108859171
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1875239769
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3063732473
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2242488794
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2037546835
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1207308685
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2642609708
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1014752311
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3141232693
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1817373671
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3567247327
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1419728298
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.877198126
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.817524132
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3937341099
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.503474511
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1352989718
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3242692251
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2209294631
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2971224202
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1920553183
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1831289701
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3635515156
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2817475664
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2167756
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2309474740
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2797204904
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3973880392
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1565572280
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2941310994
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1504272991
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1703509261
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3851072169
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2196961692
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1569248239
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.920224254
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1655578684
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/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.3075404615
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.804229587
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_regwen.1062691432
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_smoke.4137981266
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all.3240098889
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3663085508
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.4035496078
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.4182374364
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.2053500957
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.2806329548
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.118924250
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.339162692
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.877035457
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.130199061
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.2630287605
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.2367455101
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.3767301577
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.1197388644
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.127472231
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.346585093
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.818830166
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.2891220911
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.1330750254
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3553319128
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.4266800307
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.1247543774
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.1447348231
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.412569332
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.663006147
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.516759165
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.1540384509
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.4009751211
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.254412920
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.384504311
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.1576048917
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.1165018104
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.3015331733
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.2769467407
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.21850883
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.3221993881
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all.2820709100
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.176533045
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.3624831119
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.571436457
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.549619720
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.2919075135
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.3792819353
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.4283239333
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.855284999
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.125737544
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.2161885770
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.108223443
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.3773958308
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.812613421
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.713457556
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3376445365
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.1770057229
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.2849342048
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.2169560893
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.1667903063
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.2454301177



Total test records in report: 1028
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.4294941924 Aug 23 06:18:21 AM UTC 24 Aug 23 06:18:23 AM UTC 24 47526600 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.723086753 Aug 23 06:18:21 AM UTC 24 Aug 23 06:18:25 AM UTC 24 105016457 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.2754611455 Aug 23 06:18:25 AM UTC 24 Aug 23 06:18:26 AM UTC 24 40389896 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.2405507472 Aug 23 06:18:22 AM UTC 24 Aug 23 06:18:27 AM UTC 24 295110883 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.1891284539 Aug 23 06:18:25 AM UTC 24 Aug 23 06:18:29 AM UTC 24 990774726 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.1373172961 Aug 23 06:18:23 AM UTC 24 Aug 23 06:18:29 AM UTC 24 725825016 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.3648318948 Aug 23 06:18:21 AM UTC 24 Aug 23 06:18:30 AM UTC 24 709676811 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_smoke.2376508237 Aug 23 06:18:21 AM UTC 24 Aug 23 06:18:32 AM UTC 24 324795058 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.565452236 Aug 23 06:18:29 AM UTC 24 Aug 23 06:18:32 AM UTC 24 202716401 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.460230221 Aug 23 06:18:23 AM UTC 24 Aug 23 06:18:32 AM UTC 24 1765397438 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_smoke.815281663 Aug 23 06:18:26 AM UTC 24 Aug 23 06:18:33 AM UTC 24 566655724 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.66733943 Aug 23 06:18:34 AM UTC 24 Aug 23 06:18:35 AM UTC 24 31700748 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.3686905992 Aug 23 06:18:29 AM UTC 24 Aug 23 06:18:37 AM UTC 24 536451237 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.828820927 Aug 23 06:18:29 AM UTC 24 Aug 23 06:18:39 AM UTC 24 774621556 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_alert_test.1702586960 Aug 23 06:18:38 AM UTC 24 Aug 23 06:18:39 AM UTC 24 22447254 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.92870481 Aug 23 06:18:37 AM UTC 24 Aug 23 06:18:40 AM UTC 24 190257389 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.3861085608 Aug 23 06:18:37 AM UTC 24 Aug 23 06:18:42 AM UTC 24 300738914 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.2143605714 Aug 23 06:18:35 AM UTC 24 Aug 23 06:18:46 AM UTC 24 2181304220 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_smoke.2751281068 Aug 23 06:18:40 AM UTC 24 Aug 23 06:18:48 AM UTC 24 425482200 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.1012550836 Aug 23 06:18:21 AM UTC 24 Aug 23 06:18:49 AM UTC 24 452189227 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access.2454346589 Aug 23 06:18:28 AM UTC 24 Aug 23 06:18:54 AM UTC 24 522406048 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access.575230575 Aug 23 06:18:43 AM UTC 24 Aug 23 06:18:55 AM UTC 24 222777256 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_bijection.1310900773 Aug 23 06:18:40 AM UTC 24 Aug 23 06:18:55 AM UTC 24 3157044222 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.2168471892 Aug 23 06:18:50 AM UTC 24 Aug 23 06:18:56 AM UTC 24 417582602 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.4277859079 Aug 23 06:18:55 AM UTC 24 Aug 23 06:18:57 AM UTC 24 124829668 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.2110271760 Aug 23 06:18:47 AM UTC 24 Aug 23 06:18:57 AM UTC 24 346570161 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.2831926742 Aug 23 06:18:50 AM UTC 24 Aug 23 06:18:57 AM UTC 24 115372594 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.3371433626 Aug 23 06:18:21 AM UTC 24 Aug 23 06:18:58 AM UTC 24 526602176 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_alert_test.2559416951 Aug 23 06:18:58 AM UTC 24 Aug 23 06:18:59 AM UTC 24 22668011 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.1890576996 Aug 23 06:18:56 AM UTC 24 Aug 23 06:19:00 AM UTC 24 334288353 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.4280831866 Aug 23 06:18:58 AM UTC 24 Aug 23 06:19:02 AM UTC 24 645852810 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.2808795623 Aug 23 06:18:48 AM UTC 24 Aug 23 06:19:06 AM UTC 24 429794096 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_bijection.4180401924 Aug 23 06:18:28 AM UTC 24 Aug 23 06:19:07 AM UTC 24 2668801353 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.1211210919 Aug 23 06:18:56 AM UTC 24 Aug 23 06:19:07 AM UTC 24 1766899566 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_smoke.3991887126 Aug 23 06:18:59 AM UTC 24 Aug 23 06:19:11 AM UTC 24 1007572185 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access.4285560262 Aug 23 06:18:21 AM UTC 24 Aug 23 06:19:14 AM UTC 24 253374011 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.1469108361 Aug 23 06:19:13 AM UTC 24 Aug 23 06:19:17 AM UTC 24 869653546 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access.1033862838 Aug 23 06:19:02 AM UTC 24 Aug 23 06:19:21 AM UTC 24 4526788838 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.158941282 Aug 23 06:19:08 AM UTC 24 Aug 23 06:19:22 AM UTC 24 135285614 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.1220924402 Aug 23 06:19:24 AM UTC 24 Aug 23 06:19:26 AM UTC 24 47668907 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_bijection.1924071027 Aug 23 06:19:01 AM UTC 24 Aug 23 06:19:30 AM UTC 24 1843865455 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_bijection.4209823495 Aug 23 06:18:21 AM UTC 24 Aug 23 06:19:33 AM UTC 24 3768824620 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.1501561281 Aug 23 06:19:31 AM UTC 24 Aug 23 06:19:37 AM UTC 24 483496318 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1908871469 Aug 23 06:18:37 AM UTC 24 Aug 23 06:19:38 AM UTC 24 7708859621 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.3628563792 Aug 23 06:19:28 AM UTC 24 Aug 23 06:19:39 AM UTC 24 463553944 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.2160039439 Aug 23 06:19:08 AM UTC 24 Aug 23 06:19:40 AM UTC 24 480135482 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_regwen.1762636198 Aug 23 06:19:22 AM UTC 24 Aug 23 06:19:40 AM UTC 24 4086786419 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_alert_test.2398070397 Aug 23 06:19:39 AM UTC 24 Aug 23 06:19:41 AM UTC 24 15794794 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.4278377776 Aug 23 06:19:37 AM UTC 24 Aug 23 06:19:41 AM UTC 24 624789267 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_smoke.31193892 Aug 23 06:19:39 AM UTC 24 Aug 23 06:19:48 AM UTC 24 272983896 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access.1797045894 Aug 23 06:19:42 AM UTC 24 Aug 23 06:19:58 AM UTC 24 107668402 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_bijection.553488443 Aug 23 06:19:41 AM UTC 24 Aug 23 06:19:59 AM UTC 24 965811154 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.2530283014 Aug 23 06:20:00 AM UTC 24 Aug 23 06:20:31 AM UTC 24 459741844 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.2048003963 Aug 23 06:19:59 AM UTC 24 Aug 23 06:20:33 AM UTC 24 423752731 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.190274810 Aug 23 06:20:32 AM UTC 24 Aug 23 06:20:37 AM UTC 24 444684064 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2359371630 Aug 23 06:18:56 AM UTC 24 Aug 23 06:20:44 AM UTC 24 2310509078 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.1629190641 Aug 23 06:18:21 AM UTC 24 Aug 23 06:21:13 AM UTC 24 3590363634 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_executable.3039297675 Aug 23 06:20:37 AM UTC 24 Aug 23 06:21:14 AM UTC 24 1795746511 ps
T112 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.302706290 Aug 23 06:21:13 AM UTC 24 Aug 23 06:21:15 AM UTC 24 37434125 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.2852835404 Aug 23 06:18:28 AM UTC 24 Aug 23 06:21:16 AM UTC 24 43936761260 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.1022385920 Aug 23 06:21:15 AM UTC 24 Aug 23 06:21:21 AM UTC 24 353842903 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.3135940877 Aug 23 06:21:14 AM UTC 24 Aug 23 06:21:21 AM UTC 24 334827062 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.813845472 Aug 23 06:21:22 AM UTC 24 Aug 23 06:21:25 AM UTC 24 340526159 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.1652362054 Aug 23 06:19:34 AM UTC 24 Aug 23 06:21:25 AM UTC 24 980929269 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_alert_test.358177546 Aug 23 06:21:26 AM UTC 24 Aug 23 06:21:27 AM UTC 24 12701992 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_smoke.177794513 Aug 23 06:21:27 AM UTC 24 Aug 23 06:21:29 AM UTC 24 39637153 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.3305737544 Aug 23 06:18:28 AM UTC 24 Aug 23 06:21:39 AM UTC 24 15000644574 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.994357830 Aug 23 06:18:41 AM UTC 24 Aug 23 06:21:43 AM UTC 24 2144218937 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.4203442905 Aug 23 06:18:21 AM UTC 24 Aug 23 06:21:56 AM UTC 24 44751086245 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.3434717571 Aug 23 06:19:14 AM UTC 24 Aug 23 06:22:12 AM UTC 24 1429642375 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.4159027667 Aug 23 06:22:13 AM UTC 24 Aug 23 06:22:27 AM UTC 24 158602344 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access.2740626018 Aug 23 06:21:44 AM UTC 24 Aug 23 06:22:30 AM UTC 24 655866530 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.2092930866 Aug 23 06:22:30 AM UTC 24 Aug 23 06:22:35 AM UTC 24 437046222 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_bijection.3399382394 Aug 23 06:21:31 AM UTC 24 Aug 23 06:22:47 AM UTC 24 7103979041 ps
T129 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_executable.1532137328 Aug 23 06:22:48 AM UTC 24 Aug 23 06:23:03 AM UTC 24 2235217205 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.2786959442 Aug 23 06:22:27 AM UTC 24 Aug 23 06:23:08 AM UTC 24 957809039 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.1030768907 Aug 23 06:23:08 AM UTC 24 Aug 23 06:23:10 AM UTC 24 68748878 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_regwen.718052066 Aug 23 06:18:55 AM UTC 24 Aug 23 06:23:33 AM UTC 24 6959675544 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.1541001166 Aug 23 06:21:16 AM UTC 24 Aug 23 06:23:13 AM UTC 24 2120172509 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.3291889137 Aug 23 06:23:10 AM UTC 24 Aug 23 06:23:16 AM UTC 24 369345026 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.3787129630 Aug 23 06:19:07 AM UTC 24 Aug 23 06:23:17 AM UTC 24 18338773320 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.2070872730 Aug 23 06:23:13 AM UTC 24 Aug 23 06:23:19 AM UTC 24 325439704 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_alert_test.2603555831 Aug 23 06:23:20 AM UTC 24 Aug 23 06:23:21 AM UTC 24 16236886 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_smoke.4137981266 Aug 23 06:23:22 AM UTC 24 Aug 23 06:24:18 AM UTC 24 571814108 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_regwen.2062831959 Aug 23 06:23:04 AM UTC 24 Aug 23 06:24:19 AM UTC 24 1415974532 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.102278069 Aug 23 06:19:01 AM UTC 24 Aug 23 06:24:40 AM UTC 24 3982378507 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.4047978586 Aug 23 06:19:41 AM UTC 24 Aug 23 06:24:45 AM UTC 24 9445322789 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.2037309592 Aug 23 06:21:28 AM UTC 24 Aug 23 06:24:54 AM UTC 24 17647734070 ps
T125 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_executable.4031547711 Aug 23 06:18:33 AM UTC 24 Aug 23 06:24:59 AM UTC 24 10701227402 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.4203702563 Aug 23 06:18:21 AM UTC 24 Aug 23 06:25:22 AM UTC 24 37593112554 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.791324944 Aug 23 06:25:23 AM UTC 24 Aug 23 06:25:30 AM UTC 24 1925675434 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_bijection.2707237484 Aug 23 06:24:19 AM UTC 24 Aug 23 06:25:35 AM UTC 24 5084004860 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.3188735795 Aug 23 06:24:55 AM UTC 24 Aug 23 06:25:39 AM UTC 24 269536774 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access.4169830539 Aug 23 06:24:40 AM UTC 24 Aug 23 06:25:48 AM UTC 24 3449367489 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.1509453721 Aug 23 06:19:49 AM UTC 24 Aug 23 06:25:49 AM UTC 24 28904896267 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.804229587 Aug 23 06:25:49 AM UTC 24 Aug 23 06:25:50 AM UTC 24 32671803 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.4182374364 Aug 23 06:25:00 AM UTC 24 Aug 23 06:25:51 AM UTC 24 168837419 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.453257157 Aug 23 06:19:42 AM UTC 24 Aug 23 06:25:54 AM UTC 24 4238645686 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.361579398 Aug 23 06:25:51 AM UTC 24 Aug 23 06:25:55 AM UTC 24 339409029 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.3216194714 Aug 23 06:25:50 AM UTC 24 Aug 23 06:25:56 AM UTC 24 1223280766 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_alert_test.861521046 Aug 23 06:25:56 AM UTC 24 Aug 23 06:25:58 AM UTC 24 13843603 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.2891220911 Aug 23 06:25:57 AM UTC 24 Aug 23 06:26:02 AM UTC 24 135496960 ps
T126 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all.3994413149 Aug 23 06:21:21 AM UTC 24 Aug 23 06:26:06 AM UTC 24 24113906937 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_executable.4211972519 Aug 23 06:18:50 AM UTC 24 Aug 23 06:26:09 AM UTC 24 1687908894 ps
T173 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.840406527 Aug 23 06:21:41 AM UTC 24 Aug 23 06:26:18 AM UTC 24 12412220233 ps
T174 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.118924250 Aug 23 06:26:03 AM UTC 24 Aug 23 06:26:20 AM UTC 24 349316708 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.1994086085 Aug 23 06:22:36 AM UTC 24 Aug 23 06:26:22 AM UTC 24 10498627754 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.1197388644 Aug 23 06:26:09 AM UTC 24 Aug 23 06:26:25 AM UTC 24 140648039 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_regwen.316240613 Aug 23 06:18:33 AM UTC 24 Aug 23 06:26:32 AM UTC 24 10488820080 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.877035457 Aug 23 06:26:25 AM UTC 24 Aug 23 06:26:32 AM UTC 24 1290505121 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_regwen.110217416 Aug 23 06:18:21 AM UTC 24 Aug 23 06:26:33 AM UTC 24 15451857917 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.130199061 Aug 23 06:26:20 AM UTC 24 Aug 23 06:26:36 AM UTC 24 304132954 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.1200737484 Aug 23 06:20:34 AM UTC 24 Aug 23 06:26:36 AM UTC 24 32232285117 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_executable.1381975035 Aug 23 06:18:21 AM UTC 24 Aug 23 06:26:37 AM UTC 24 2745784594 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.346585093 Aug 23 06:26:37 AM UTC 24 Aug 23 06:26:38 AM UTC 24 31128020 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.2630287605 Aug 23 06:26:38 AM UTC 24 Aug 23 06:26:41 AM UTC 24 87412689 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.2367455101 Aug 23 06:26:38 AM UTC 24 Aug 23 06:26:46 AM UTC 24 139071676 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.2806329548 Aug 23 06:26:47 AM UTC 24 Aug 23 06:26:48 AM UTC 24 25162373 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.658428954 Aug 23 06:18:45 AM UTC 24 Aug 23 06:26:53 AM UTC 24 7580330704 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.3221993881 Aug 23 06:26:49 AM UTC 24 Aug 23 06:27:12 AM UTC 24 397727764 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.1247543774 Aug 23 06:26:22 AM UTC 24 Aug 23 06:27:18 AM UTC 24 155618174 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.2371646625 Aug 23 06:18:30 AM UTC 24 Aug 23 06:27:30 AM UTC 24 4392445797 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3553319128 Aug 23 06:26:39 AM UTC 24 Aug 23 06:27:37 AM UTC 24 501836235 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.339162692 Aug 23 06:26:33 AM UTC 24 Aug 23 06:27:37 AM UTC 24 1214764349 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.4009751211 Aug 23 06:27:38 AM UTC 24 Aug 23 06:28:01 AM UTC 24 91521706 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.663006147 Aug 23 06:27:12 AM UTC 24 Aug 23 06:28:13 AM UTC 24 3033131434 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.1835621597 Aug 23 06:21:57 AM UTC 24 Aug 23 06:28:17 AM UTC 24 118054717547 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.571436457 Aug 23 06:28:02 AM UTC 24 Aug 23 06:28:18 AM UTC 24 339777620 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.3767301577 Aug 23 06:25:58 AM UTC 24 Aug 23 06:28:21 AM UTC 24 754167985 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.1540384509 Aug 23 06:28:14 AM UTC 24 Aug 23 06:28:22 AM UTC 24 2314079904 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.2769467407 Aug 23 06:28:23 AM UTC 24 Aug 23 06:28:25 AM UTC 24 31123546 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.1165018104 Aug 23 06:27:31 AM UTC 24 Aug 23 06:28:31 AM UTC 24 797347998 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.384504311 Aug 23 06:28:26 AM UTC 24 Aug 23 06:28:32 AM UTC 24 1315137740 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.254412920 Aug 23 06:28:32 AM UTC 24 Aug 23 06:28:38 AM UTC 24 188620415 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.3075404615 Aug 23 06:24:46 AM UTC 24 Aug 23 06:28:43 AM UTC 24 10790624979 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.412569332 Aug 23 06:28:44 AM UTC 24 Aug 23 06:28:46 AM UTC 24 13324044 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1131693882 Aug 23 06:23:18 AM UTC 24 Aug 23 06:28:50 AM UTC 24 4112795213 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.2849342048 Aug 23 06:28:46 AM UTC 24 Aug 23 06:29:05 AM UTC 24 362776314 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.2497160768 Aug 23 06:19:01 AM UTC 24 Aug 23 06:29:46 AM UTC 24 14947140912 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.3792819353 Aug 23 06:29:05 AM UTC 24 Aug 23 06:30:07 AM UTC 24 29376798979 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.3901333241 Aug 23 06:23:34 AM UTC 24 Aug 23 06:30:15 AM UTC 24 46847911830 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.4035496078 Aug 23 06:24:20 AM UTC 24 Aug 23 06:30:21 AM UTC 24 45191536810 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3663085508 Aug 23 06:25:52 AM UTC 24 Aug 23 06:30:26 AM UTC 24 6398890828 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.4266800307 Aug 23 06:26:07 AM UTC 24 Aug 23 06:30:28 AM UTC 24 2804520575 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.855284999 Aug 23 06:30:29 AM UTC 24 Aug 23 06:30:35 AM UTC 24 575787854 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.812613421 Aug 23 06:30:08 AM UTC 24 Aug 23 06:30:49 AM UTC 24 1069150529 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_regwen.1261822724 Aug 23 06:20:44 AM UTC 24 Aug 23 06:31:08 AM UTC 24 10650207019 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.125737544 Aug 23 06:30:22 AM UTC 24 Aug 23 06:31:20 AM UTC 24 1055516484 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.176533045 Aug 23 06:28:33 AM UTC 24 Aug 23 06:31:22 AM UTC 24 15229345001 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3376445365 Aug 23 06:31:20 AM UTC 24 Aug 23 06:31:22 AM UTC 24 50690972 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.3015331733 Aug 23 06:27:37 AM UTC 24 Aug 23 06:31:28 AM UTC 24 3247459380 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.2161885770 Aug 23 06:31:22 AM UTC 24 Aug 23 06:31:29 AM UTC 24 689954659 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.108223443 Aug 23 06:31:22 AM UTC 24 Aug 23 06:31:33 AM UTC 24 904480399 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.2919075135 Aug 23 06:31:34 AM UTC 24 Aug 23 06:31:36 AM UTC 24 38797971 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.2454301177 Aug 23 06:30:27 AM UTC 24 Aug 23 06:31:37 AM UTC 24 340849945 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_smoke.228488039 Aug 23 06:35:07 AM UTC 24 Aug 23 06:35:18 AM UTC 24 131557282 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.1745986791 Aug 23 06:18:28 AM UTC 24 Aug 23 06:31:40 AM UTC 24 16598631730 ps
T128 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_executable.487720358 Aug 23 06:19:18 AM UTC 24 Aug 23 06:31:41 AM UTC 24 2565757171 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.1667903063 Aug 23 06:29:46 AM UTC 24 Aug 23 06:31:42 AM UTC 24 2271304231 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.127472231 Aug 23 06:26:19 AM UTC 24 Aug 23 06:31:43 AM UTC 24 13380778896 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_smoke.1374449884 Aug 23 06:31:36 AM UTC 24 Aug 23 06:31:46 AM UTC 24 1710159496 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.2065907848 Aug 23 06:31:47 AM UTC 24 Aug 23 06:31:49 AM UTC 24 45704022 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.1139246528 Aug 23 06:18:40 AM UTC 24 Aug 23 06:32:06 AM UTC 24 17581826173 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.913981389 Aug 23 06:31:50 AM UTC 24 Aug 23 06:32:15 AM UTC 24 132900159 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access.3840550171 Aug 23 06:31:43 AM UTC 24 Aug 23 06:32:17 AM UTC 24 3824719011 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.262179339 Aug 23 06:32:07 AM UTC 24 Aug 23 06:32:18 AM UTC 24 2482986043 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_bijection.2901227919 Aug 23 06:31:42 AM UTC 24 Aug 23 06:32:37 AM UTC 24 3406387137 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.307899594 Aug 23 06:32:38 AM UTC 24 Aug 23 06:32:40 AM UTC 24 50836353 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.2204293986 Aug 23 06:32:41 AM UTC 24 Aug 23 06:32:52 AM UTC 24 468208250 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.641445986 Aug 23 06:32:48 AM UTC 24 Aug 23 06:32:55 AM UTC 24 1120325226 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.3624831119 Aug 23 06:27:19 AM UTC 24 Aug 23 06:32:56 AM UTC 24 15337331112 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.3317152577 Aug 23 06:32:16 AM UTC 24 Aug 23 06:32:57 AM UTC 24 3217586938 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_alert_test.433746092 Aug 23 06:32:58 AM UTC 24 Aug 23 06:32:59 AM UTC 24 39519452 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_regwen.1655120557 Aug 23 06:32:19 AM UTC 24 Aug 23 06:33:00 AM UTC 24 2937727629 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_smoke.2525960184 Aug 23 06:32:58 AM UTC 24 Aug 23 06:33:05 AM UTC 24 312546525 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all.3236354995 Aug 23 06:19:34 AM UTC 24 Aug 23 06:33:41 AM UTC 24 84411099820 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.3149932556 Aug 23 06:31:38 AM UTC 24 Aug 23 06:33:43 AM UTC 24 20473373303 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access.1191702074 Aug 23 06:33:41 AM UTC 24 Aug 23 06:33:44 AM UTC 24 68512305 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_bijection.3205439777 Aug 23 06:33:01 AM UTC 24 Aug 23 06:33:45 AM UTC 24 4483861972 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.1576048917 Aug 23 06:26:54 AM UTC 24 Aug 23 06:33:54 AM UTC 24 3205171115 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.965875916 Aug 23 06:33:55 AM UTC 24 Aug 23 06:34:01 AM UTC 24 415603838 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.2937405767 Aug 23 06:31:44 AM UTC 24 Aug 23 06:34:11 AM UTC 24 4270771674 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.2504772426 Aug 23 06:33:46 AM UTC 24 Aug 23 06:34:11 AM UTC 24 488643768 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.713457556 Aug 23 06:30:16 AM UTC 24 Aug 23 06:34:48 AM UTC 24 110272776132 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.1552461364 Aug 23 06:34:49 AM UTC 24 Aug 23 06:34:50 AM UTC 24 43359291 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.1859906667 Aug 23 06:34:51 AM UTC 24 Aug 23 06:34:57 AM UTC 24 131064330 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.1024994877 Aug 23 06:33:45 AM UTC 24 Aug 23 06:34:57 AM UTC 24 758013442 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.2847115351 Aug 23 06:34:58 AM UTC 24 Aug 23 06:35:01 AM UTC 24 50274505 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.2053500957 Aug 23 06:26:32 AM UTC 24 Aug 23 06:35:04 AM UTC 24 11380765408 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_alert_test.3121201340 Aug 23 06:35:05 AM UTC 24 Aug 23 06:35:07 AM UTC 24 37869526 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.2124490127 Aug 23 06:34:01 AM UTC 24 Aug 23 06:35:11 AM UTC 24 277247869 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_executable.4045491618 Aug 23 06:25:37 AM UTC 24 Aug 23 06:35:25 AM UTC 24 10697751352 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.1538625349 Aug 23 06:25:31 AM UTC 24 Aug 23 06:35:34 AM UTC 24 9925836753 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1511842191 Aug 23 06:34:58 AM UTC 24 Aug 23 06:35:35 AM UTC 24 2949409228 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access.3002360418 Aug 23 06:35:27 AM UTC 24 Aug 23 06:35:35 AM UTC 24 361902217 ps
T130 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all.3935876633 Aug 23 06:18:57 AM UTC 24 Aug 23 06:35:42 AM UTC 24 22190267653 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.2455712735 Aug 23 06:35:44 AM UTC 24 Aug 23 06:35:47 AM UTC 24 218480334 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.3471586092 Aug 23 06:35:36 AM UTC 24 Aug 23 06:36:00 AM UTC 24 111378080 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_bijection.4040367597 Aug 23 06:35:18 AM UTC 24 Aug 23 06:36:19 AM UTC 24 4110228087 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.3437435426 Aug 23 06:31:42 AM UTC 24 Aug 23 06:36:26 AM UTC 24 3122108956 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.245187721 Aug 23 06:36:27 AM UTC 24 Aug 23 06:36:29 AM UTC 24 46538044 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.3573189406 Aug 23 06:35:36 AM UTC 24 Aug 23 06:36:31 AM UTC 24 578593623 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.3692718178 Aug 23 06:36:29 AM UTC 24 Aug 23 06:36:36 AM UTC 24 836060137 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.1092472914 Aug 23 06:35:11 AM UTC 24 Aug 23 06:36:37 AM UTC 24 672591007 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.3560239995 Aug 23 06:36:32 AM UTC 24 Aug 23 06:36:37 AM UTC 24 248083052 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_alert_test.1384117718 Aug 23 06:36:38 AM UTC 24 Aug 23 06:36:40 AM UTC 24 14051352 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_smoke.3912625167 Aug 23 06:36:40 AM UTC 24 Aug 23 06:36:54 AM UTC 24 1439012312 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all.3160978172 Aug 23 06:35:02 AM UTC 24 Aug 23 06:37:04 AM UTC 24 38483975405 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.2902986328 Aug 23 06:33:06 AM UTC 24 Aug 23 06:37:23 AM UTC 24 6230483577 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.1912206264 Aug 23 06:33:43 AM UTC 24 Aug 23 06:37:31 AM UTC 24 6334082064 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access.4280883627 Aug 23 06:37:32 AM UTC 24 Aug 23 06:37:41 AM UTC 24 707304981 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.516759165 Aug 23 06:28:19 AM UTC 24 Aug 23 06:37:47 AM UTC 24 3323974273 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_bijection.43472616 Aug 23 06:37:04 AM UTC 24 Aug 23 06:38:04 AM UTC 24 7848710006 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.3715450583 Aug 23 06:38:18 AM UTC 24 Aug 23 06:38:27 AM UTC 24 2968321227 ps
T131 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.21850883 Aug 23 06:28:22 AM UTC 24 Aug 23 06:38:40 AM UTC 24 5638082756 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.2779549142 Aug 23 06:37:48 AM UTC 24 Aug 23 06:38:54 AM UTC 24 267608076 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_regwen.237943908 Aug 23 06:36:20 AM UTC 24 Aug 23 06:39:06 AM UTC 24 2604981802 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.2654417532 Aug 23 06:39:06 AM UTC 24 Aug 23 06:39:08 AM UTC 24 41800085 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.1995256916 Aug 23 06:39:08 AM UTC 24 Aug 23 06:39:14 AM UTC 24 365608864 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.3933903217 Aug 23 06:38:05 AM UTC 24 Aug 23 06:39:18 AM UTC 24 155370256 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.2940077494 Aug 23 06:39:15 AM UTC 24 Aug 23 06:39:19 AM UTC 24 60218979 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_executable.1928680700 Aug 23 06:38:41 AM UTC 24 Aug 23 06:39:30 AM UTC 24 1675463044 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_alert_test.2679862123 Aug 23 06:39:31 AM UTC 24 Aug 23 06:39:33 AM UTC 24 14350961 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.1770057229 Aug 23 06:31:09 AM UTC 24 Aug 23 06:39:58 AM UTC 24 7410902918 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_smoke.1447192061 Aug 23 06:39:34 AM UTC 24 Aug 23 06:40:10 AM UTC 24 1999245255 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.549619720 Aug 23 06:30:35 AM UTC 24 Aug 23 06:40:22 AM UTC 24 16094911848 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.818830166 Aug 23 06:26:34 AM UTC 24 Aug 23 06:40:25 AM UTC 24 27603455214 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_bijection.3507742259 Aug 23 06:40:11 AM UTC 24 Aug 23 06:40:27 AM UTC 24 277706853 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access.3960111487 Aug 23 06:40:26 AM UTC 24 Aug 23 06:40:29 AM UTC 24 37596343 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.4124096320 Aug 23 06:35:25 AM UTC 24 Aug 23 06:40:37 AM UTC 24 13741557054 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.1670926916 Aug 23 06:40:37 AM UTC 24 Aug 23 06:40:41 AM UTC 24 58161663 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.3286670340 Aug 23 06:40:42 AM UTC 24 Aug 23 06:40:47 AM UTC 24 770200189 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.725736883 Aug 23 06:40:29 AM UTC 24 Aug 23 06:41:05 AM UTC 24 233053816 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.1447348231 Aug 23 06:28:19 AM UTC 24 Aug 23 06:41:08 AM UTC 24 8083631279 ps
T132 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_regwen.1062691432 Aug 23 06:25:40 AM UTC 24 Aug 23 06:41:17 AM UTC 24 13177281180 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.2216233282 Aug 23 06:41:18 AM UTC 24 Aug 23 06:41:19 AM UTC 24 103069560 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_regwen.4147830168 Aug 23 06:41:09 AM UTC 24 Aug 23 06:41:22 AM UTC 24 443247852 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.3365667266 Aug 23 06:41:20 AM UTC 24 Aug 23 06:41:25 AM UTC 24 285808571 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.3300010983 Aug 23 06:35:34 AM UTC 24 Aug 23 06:41:25 AM UTC 24 55748424073 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.594391560 Aug 23 06:41:23 AM UTC 24 Aug 23 06:41:29 AM UTC 24 886641233 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_alert_test.2924150835 Aug 23 06:41:30 AM UTC 24 Aug 23 06:41:32 AM UTC 24 14184090 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_smoke.2950469841 Aug 23 06:41:32 AM UTC 24 Aug 23 06:41:34 AM UTC 24 62720330 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all.3240098889 Aug 23 06:25:55 AM UTC 24 Aug 23 06:41:40 AM UTC 24 26484806297 ps
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