Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	157254226	1			T3	882		T4	946		T5	6142
instr_valid_dis	119976689	1			T3	882		T4	946		T5	6142
instr_en	25016468	1			T22	1480		T16	198		T25	56806

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	12106259	1			T51	956		T148	81814		T18	18356
sram_ifetch_valid_disable	120671410	1			T3	882		T4	946		T5	6142
sram_ifetch_enable	24476557	1			T16	26356		T25	56806		T17	71632

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	157254226	1			T3	882		T4	946		T5	6142
hw_debug_en_valid_off	120283232	1			T3	882		T4	946		T5	6142
hw_debug_en_on	24967443	1			T22	1480		T26	86826		T23	20000

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	120671410	1			T3	882		T4	946		T5	6142
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	105654113	1			T3	882		T4	946		T5	6142
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	10426358	1			T22	1480		T16	198		T24	35114
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5237158	1			T18	11032		T63	32152		T38	16724
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2017040	1			T63	32152		T65	9708		T152	19482
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2021484	1			T18	11032		T152	16216		T153	69834
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4288671	1			T51	956		T148	81814		T38	42596
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1576928	1			T51	956		T148	81814		T152	1684
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1859999	1			T38	18186		T39	9394		T65	2149
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	10934222	1			T22	1480		T26	29392		T18	7700
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4957614	1			T26	29392		T64	11326		T65	9746
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4338024	1			T22	1480		T18	7700		T38	51352

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9885577	1			T25	56806		T17	71566		T18	45460
lc_exec_en	9744550	1			T26	57434		T23	20000		T18	32998
valid_exec_dis	113919662	1			T3	882		T4	946		T5	6142
invalid_exec_dis	36582816	1			T16	26356		T25	56806		T17	71632