Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44


Total tests in report: 1030
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
72.89 72.89 91.95 91.95 74.41 74.41 94.87 94.87 33.33 33.33 81.88 81.88 93.36 93.36 40.40 40.40 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.3778205928
84.69 11.80 96.36 4.41 83.89 9.48 96.53 1.66 71.43 38.10 88.65 6.76 95.28 1.92 60.69 20.29 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2569099100
89.48 4.80 97.80 1.44 84.36 0.47 96.53 0.00 100.00 28.57 91.55 2.90 95.28 0.00 60.88 0.18 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.3388917786
92.65 3.16 98.05 0.25 86.14 1.78 96.60 0.07 100.00 0.00 92.75 1.21 95.28 0.00 79.71 18.83 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3763908790
93.76 1.11 98.39 0.34 88.51 2.37 98.13 1.53 100.00 0.00 94.44 1.69 96.02 0.74 80.80 1.10 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.2236888043
94.55 0.79 98.39 0.00 89.10 0.59 98.13 0.00 100.00 0.00 94.44 0.00 96.02 0.00 85.74 4.94 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.439171443
95.27 0.72 98.64 0.25 90.17 1.07 98.20 0.07 100.00 0.00 95.41 0.97 96.90 0.88 87.57 1.83 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.3116041629
95.66 0.39 98.64 0.00 90.17 0.00 98.20 0.00 100.00 0.00 95.41 0.00 96.90 0.00 90.31 2.74 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_executable.2770707676
95.90 0.24 98.64 0.00 90.17 0.00 98.20 0.00 100.00 0.00 95.41 0.00 96.90 0.00 91.96 1.65 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.2627108652
96.13 0.23 98.90 0.25 90.28 0.12 98.47 0.28 100.00 0.00 95.65 0.24 96.90 0.00 92.69 0.73 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.3361422194
96.31 0.18 98.90 0.00 90.28 0.00 98.54 0.07 100.00 0.00 95.65 0.00 98.08 1.18 92.69 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.261485921
96.48 0.18 98.90 0.00 90.28 0.00 98.54 0.00 100.00 0.00 95.65 0.00 98.23 0.15 93.78 1.10 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.2411863599
96.66 0.17 98.90 0.00 90.52 0.24 98.61 0.07 100.00 0.00 95.65 0.00 98.23 0.00 94.70 0.91 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all.2443968421
96.80 0.14 98.98 0.08 90.52 0.00 99.51 0.90 100.00 0.00 95.65 0.00 98.23 0.00 94.70 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.2271457086
96.93 0.13 98.98 0.00 90.52 0.00 99.51 0.00 100.00 0.00 95.65 0.00 98.23 0.00 95.61 0.91 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all.2105494924
97.05 0.12 99.15 0.17 90.64 0.12 99.58 0.07 100.00 0.00 96.14 0.48 98.23 0.00 95.61 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.2899987728
97.16 0.11 99.15 0.00 90.64 0.00 99.58 0.00 100.00 0.00 96.14 0.00 98.97 0.74 95.61 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1273648426
97.26 0.10 99.15 0.00 90.64 0.00 99.58 0.00 100.00 0.00 96.14 0.00 98.97 0.00 96.34 0.73 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.717155149
97.32 0.06 99.15 0.00 91.00 0.36 99.65 0.07 100.00 0.00 96.14 0.00 98.97 0.00 96.34 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.1565579906
97.37 0.05 99.15 0.00 91.00 0.00 99.65 0.00 100.00 0.00 96.14 0.00 98.97 0.00 96.71 0.37 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2069557591
97.40 0.03 99.15 0.00 91.00 0.00 99.65 0.00 100.00 0.00 96.14 0.00 98.97 0.00 96.89 0.18 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.285366087
97.43 0.03 99.15 0.00 91.00 0.00 99.65 0.00 100.00 0.00 96.14 0.00 98.97 0.00 97.07 0.18 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1584038746
97.45 0.03 99.15 0.00 91.00 0.00 99.65 0.00 100.00 0.00 96.14 0.00 98.97 0.00 97.26 0.18 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_executable.1694388662
97.48 0.03 99.15 0.00 91.00 0.00 99.65 0.00 100.00 0.00 96.14 0.00 98.97 0.00 97.44 0.18 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all.495401975
97.50 0.02 99.15 0.00 91.00 0.00 99.65 0.00 100.00 0.00 96.14 0.00 99.12 0.15 97.44 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.4141026773
97.51 0.01 99.15 0.00 91.00 0.00 99.72 0.07 100.00 0.00 96.14 0.00 99.12 0.00 97.44 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.4087780521

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.659251241
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1487573149
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.875542273
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.814645489
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2629922743
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2471425325
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3315397194
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3878093930
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2745257927
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2062550929
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3923945360
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3585964183
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.511641752
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2371457458
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.272569641
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.4106707195
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.399938785
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.606982832
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.234401298
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1841989617
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2274644390
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.198077053
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3600059446
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.559718620
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1056355878
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3400126228
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2326861869
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3427248880
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.952081663
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.181473895
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2431106451
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1393707305
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3974292292
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1728980058
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3531406814
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2831490717
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1316584768
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3455104208
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2991811520
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2973214179
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2292441032
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2657137690
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.4118320322
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3330733313
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1671478612
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2062989740
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3056911403
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3472346026
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3542927573
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.111040086
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.678791965
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2744469659
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1572124215
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3612857073
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2824075648
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3269685202
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2925050476
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1531202977
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1890260587
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3018067170
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.739921819
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.4274916792
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.604892559
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3914151609
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2444046352
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1860362080
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2448590606
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1280804197
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3967183498
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1362579119
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3268212514
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2142605
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2040378505
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2725122920
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.383998720
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3733158559
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.12097524
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2978885282
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3398530693
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2841732164
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/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.2557691436
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.1963383317
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.2911879128
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.2216640328
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/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.3925372364
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.3782614150
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/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.1322256091
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.1151256902
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/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.2848631277
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.710542629
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.646637694
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.4097121184
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.1171083549
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.1553511534
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.485093094
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.4169859250
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.3518431932
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.1254727517
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.319061902
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.166778741
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.1541394602
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/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.808925657
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.4021280055
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.2123592292
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.3947563438
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/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.340459640
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.2915607006
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.2553730554
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.2699572253
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.2539928188
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.505369923
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3835584645
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.4219561617
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.2645132343
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.4014590146
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.4176370567
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.887070056
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.2394099329



Total test records in report: 1030
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.1565579906 Aug 25 07:52:19 AM UTC 24 Aug 25 07:52:21 AM UTC 24 101971366 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.4215377399 Aug 25 07:52:19 AM UTC 24 Aug 25 07:52:22 AM UTC 24 86034489 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.4087780521 Aug 25 07:52:19 AM UTC 24 Aug 25 07:52:24 AM UTC 24 1708003379 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.2271457086 Aug 25 07:52:21 AM UTC 24 Aug 25 07:52:26 AM UTC 24 39903740 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_alert_test.3170361166 Aug 25 07:52:21 AM UTC 24 Aug 25 07:52:27 AM UTC 24 23754383 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.4250201540 Aug 25 07:52:21 AM UTC 24 Aug 25 07:52:28 AM UTC 24 90776809 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.2899987728 Aug 25 07:52:19 AM UTC 24 Aug 25 07:52:29 AM UTC 24 334628927 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.1635434507 Aug 25 07:52:19 AM UTC 24 Aug 25 07:52:30 AM UTC 24 317175417 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.2557196522 Aug 25 07:52:21 AM UTC 24 Aug 25 07:52:31 AM UTC 24 110335815 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.3778205928 Aug 25 07:52:21 AM UTC 24 Aug 25 07:52:32 AM UTC 24 489276308 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.1756060880 Aug 25 07:52:21 AM UTC 24 Aug 25 07:52:34 AM UTC 24 1610531816 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access.1975552936 Aug 25 07:52:18 AM UTC 24 Aug 25 07:52:34 AM UTC 24 205027115 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.4188735739 Aug 25 07:52:19 AM UTC 24 Aug 25 07:52:35 AM UTC 24 1374083257 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_smoke.1939466733 Aug 25 07:52:18 AM UTC 24 Aug 25 07:52:36 AM UTC 24 522515400 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.4142540912 Aug 25 07:52:35 AM UTC 24 Aug 25 07:52:38 AM UTC 24 47415018 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.1191594094 Aug 25 07:52:35 AM UTC 24 Aug 25 07:52:38 AM UTC 24 88222148 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access.2338808707 Aug 25 07:52:20 AM UTC 24 Aug 25 07:52:39 AM UTC 24 219631820 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_alert_test.712416319 Aug 25 07:52:37 AM UTC 24 Aug 25 07:52:40 AM UTC 24 79590041 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.3116041629 Aug 25 07:52:35 AM UTC 24 Aug 25 07:52:41 AM UTC 24 193131593 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.2236888043 Aug 25 07:52:37 AM UTC 24 Aug 25 07:52:44 AM UTC 24 879056525 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.3109867745 Aug 25 07:52:35 AM UTC 24 Aug 25 07:52:45 AM UTC 24 692208491 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.3410088973 Aug 25 07:52:35 AM UTC 24 Aug 25 07:52:46 AM UTC 24 490018329 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_smoke.3553298259 Aug 25 07:52:37 AM UTC 24 Aug 25 07:52:50 AM UTC 24 1308210803 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.3739096645 Aug 25 07:52:35 AM UTC 24 Aug 25 07:52:52 AM UTC 24 78062423 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access.3452594342 Aug 25 07:52:34 AM UTC 24 Aug 25 07:52:53 AM UTC 24 210871301 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.4090118512 Aug 25 07:52:52 AM UTC 24 Aug 25 07:52:54 AM UTC 24 39707033 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.2373140619 Aug 25 07:52:53 AM UTC 24 Aug 25 07:52:58 AM UTC 24 136618797 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.1631502772 Aug 25 07:52:45 AM UTC 24 Aug 25 07:52:59 AM UTC 24 2616784227 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.2854910985 Aug 25 07:52:56 AM UTC 24 Aug 25 07:53:00 AM UTC 24 132886762 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_alert_test.2597368037 Aug 25 07:53:00 AM UTC 24 Aug 25 07:53:02 AM UTC 24 13348173 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_smoke.4024912357 Aug 25 07:53:00 AM UTC 24 Aug 25 07:53:04 AM UTC 24 50559985 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.2192980469 Aug 25 07:52:52 AM UTC 24 Aug 25 07:53:07 AM UTC 24 352104371 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access.3680971851 Aug 25 07:52:41 AM UTC 24 Aug 25 07:53:17 AM UTC 24 4683124134 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.322742637 Aug 25 07:52:41 AM UTC 24 Aug 25 07:53:24 AM UTC 24 365354188 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_bijection.3572394862 Aug 25 07:52:18 AM UTC 24 Aug 25 07:53:26 AM UTC 24 657993742 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.97872286 Aug 25 07:52:21 AM UTC 24 Aug 25 07:53:26 AM UTC 24 121681673 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.4294918137 Aug 25 07:52:19 AM UTC 24 Aug 25 07:53:29 AM UTC 24 136012682 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_smoke.127153154 Aug 25 07:52:21 AM UTC 24 Aug 25 07:53:32 AM UTC 24 137949540 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_bijection.2069258538 Aug 25 07:53:03 AM UTC 24 Aug 25 07:53:34 AM UTC 24 935652335 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.3361422194 Aug 25 07:53:27 AM UTC 24 Aug 25 07:53:38 AM UTC 24 583564302 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.552480714 Aug 25 07:52:19 AM UTC 24 Aug 25 07:53:41 AM UTC 24 139937616 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.2977921597 Aug 25 07:53:39 AM UTC 24 Aug 25 07:53:41 AM UTC 24 52504206 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.45270681 Aug 25 07:53:25 AM UTC 24 Aug 25 07:53:43 AM UTC 24 264048601 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_bijection.1185530604 Aug 25 07:52:20 AM UTC 24 Aug 25 07:53:47 AM UTC 24 7002635352 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.1411523424 Aug 25 07:53:42 AM UTC 24 Aug 25 07:53:47 AM UTC 24 214780093 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.985833343 Aug 25 07:53:42 AM UTC 24 Aug 25 07:53:51 AM UTC 24 909939427 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_bijection.1153907164 Aug 25 07:52:32 AM UTC 24 Aug 25 07:53:51 AM UTC 24 9756626991 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_alert_test.319214062 Aug 25 07:53:50 AM UTC 24 Aug 25 07:53:53 AM UTC 24 14155466 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.3056991402 Aug 25 07:53:48 AM UTC 24 Aug 25 07:53:54 AM UTC 24 440893980 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.2922761759 Aug 25 07:53:01 AM UTC 24 Aug 25 07:53:59 AM UTC 24 2939211330 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_bijection.1295888319 Aug 25 07:52:39 AM UTC 24 Aug 25 07:54:04 AM UTC 24 3530938822 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_smoke.3044914188 Aug 25 07:52:20 AM UTC 24 Aug 25 07:54:04 AM UTC 24 157032015 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_smoke.3527958968 Aug 25 07:53:52 AM UTC 24 Aug 25 07:54:04 AM UTC 24 300904945 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access.1272231988 Aug 25 07:53:54 AM UTC 24 Aug 25 07:54:10 AM UTC 24 221210533 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.2539847626 Aug 25 07:54:05 AM UTC 24 Aug 25 07:54:14 AM UTC 24 294882896 ps
T174 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.2258037836 Aug 25 07:54:06 AM UTC 24 Aug 25 07:54:16 AM UTC 24 598281110 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.3704966445 Aug 25 07:54:17 AM UTC 24 Aug 25 07:54:20 AM UTC 24 31778905 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.1767362343 Aug 25 07:52:21 AM UTC 24 Aug 25 07:54:25 AM UTC 24 525595650 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.3190731067 Aug 25 07:54:20 AM UTC 24 Aug 25 07:54:29 AM UTC 24 494340390 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2569099100 Aug 25 07:52:54 AM UTC 24 Aug 25 07:54:33 AM UTC 24 446630228 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.3623218076 Aug 25 07:52:42 AM UTC 24 Aug 25 07:54:36 AM UTC 24 157391499 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.1572391641 Aug 25 07:54:25 AM UTC 24 Aug 25 07:54:36 AM UTC 24 626101434 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_alert_test.1751491703 Aug 25 07:54:37 AM UTC 24 Aug 25 07:54:39 AM UTC 24 35145766 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.927692094 Aug 25 07:52:21 AM UTC 24 Aug 25 07:54:46 AM UTC 24 2019197040 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access.3811653882 Aug 25 07:54:48 AM UTC 24 Aug 25 07:55:10 AM UTC 24 620445442 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access.1932649371 Aug 25 07:53:07 AM UTC 24 Aug 25 07:55:13 AM UTC 24 2853350918 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.30105492 Aug 25 07:53:26 AM UTC 24 Aug 25 07:55:18 AM UTC 24 643703768 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.3024632750 Aug 25 07:55:19 AM UTC 24 Aug 25 07:55:24 AM UTC 24 196895437 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.2411863599 Aug 25 07:52:18 AM UTC 24 Aug 25 07:55:34 AM UTC 24 29468188805 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.4057764961 Aug 25 07:55:10 AM UTC 24 Aug 25 07:55:34 AM UTC 24 430618536 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_bijection.1133679373 Aug 25 07:54:48 AM UTC 24 Aug 25 07:55:42 AM UTC 24 5134500288 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.751498953 Aug 25 07:55:43 AM UTC 24 Aug 25 07:55:45 AM UTC 24 79310635 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_regwen.438139362 Aug 25 07:52:35 AM UTC 24 Aug 25 07:55:47 AM UTC 24 440290388 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_bijection.772340212 Aug 25 07:53:53 AM UTC 24 Aug 25 07:55:51 AM UTC 24 4926421708 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.2126291209 Aug 25 07:55:46 AM UTC 24 Aug 25 07:55:54 AM UTC 24 256983898 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.2247239569 Aug 25 07:55:48 AM UTC 24 Aug 25 07:55:55 AM UTC 24 202683358 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_alert_test.1438438167 Aug 25 07:55:55 AM UTC 24 Aug 25 07:55:57 AM UTC 24 117574200 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.4211485144 Aug 25 07:54:05 AM UTC 24 Aug 25 07:55:59 AM UTC 24 155332143 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.3928754046 Aug 25 07:55:14 AM UTC 24 Aug 25 07:56:11 AM UTC 24 192506342 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_regwen.399150740 Aug 25 07:52:19 AM UTC 24 Aug 25 07:56:12 AM UTC 24 11750256128 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.746794701 Aug 25 07:52:39 AM UTC 24 Aug 25 07:56:32 AM UTC 24 1428182338 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.3925372364 Aug 25 07:56:33 AM UTC 24 Aug 25 07:56:35 AM UTC 24 36054143 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_smoke.3316708987 Aug 25 07:54:37 AM UTC 24 Aug 25 07:56:42 AM UTC 24 131523348 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.2286181581 Aug 25 07:56:36 AM UTC 24 Aug 25 07:56:48 AM UTC 24 605861118 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.646637694 Aug 25 07:55:56 AM UTC 24 Aug 25 07:56:48 AM UTC 24 391363703 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.2848631277 Aug 25 07:56:49 AM UTC 24 Aug 25 07:56:52 AM UTC 24 39074864 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_regwen.1240417767 Aug 25 07:54:17 AM UTC 24 Aug 25 07:57:00 AM UTC 24 291245825 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.3147040683 Aug 25 07:56:52 AM UTC 24 Aug 25 07:57:03 AM UTC 24 334612863 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.3782614150 Aug 25 07:57:01 AM UTC 24 Aug 25 07:57:08 AM UTC 24 200568911 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.1151256902 Aug 25 07:56:13 AM UTC 24 Aug 25 07:57:12 AM UTC 24 490278070 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.1963383317 Aug 25 07:57:13 AM UTC 24 Aug 25 07:57:15 AM UTC 24 27289914 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.1891833577 Aug 25 07:57:16 AM UTC 24 Aug 25 07:57:28 AM UTC 24 174173690 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.2911879128 Aug 25 07:56:00 AM UTC 24 Aug 25 07:57:39 AM UTC 24 10854274886 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_regwen.1596610651 Aug 25 07:52:21 AM UTC 24 Aug 25 07:57:41 AM UTC 24 2471923632 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all.2443968421 Aug 25 07:54:33 AM UTC 24 Aug 25 07:57:44 AM UTC 24 29355568355 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.3167608688 Aug 25 08:03:55 AM UTC 24 Aug 25 08:04:40 AM UTC 24 90432501 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1050306986 Aug 25 07:52:19 AM UTC 24 Aug 25 07:57:46 AM UTC 24 1559055946 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.166778741 Aug 25 07:57:46 AM UTC 24 Aug 25 07:57:49 AM UTC 24 126151047 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.538297004 Aug 25 07:53:54 AM UTC 24 Aug 25 07:57:52 AM UTC 24 1858939817 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.319061902 Aug 25 07:57:52 AM UTC 24 Aug 25 07:58:00 AM UTC 24 469960749 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.80926568 Aug 25 07:57:44 AM UTC 24 Aug 25 07:58:07 AM UTC 24 865678807 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.1993124960 Aug 25 07:52:32 AM UTC 24 Aug 25 07:58:16 AM UTC 24 10337202677 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.1553511534 Aug 25 07:56:33 AM UTC 24 Aug 25 07:58:21 AM UTC 24 158377018 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3444775165 Aug 25 07:54:30 AM UTC 24 Aug 25 07:58:22 AM UTC 24 2564251902 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.2482333094 Aug 25 07:58:23 AM UTC 24 Aug 25 07:58:25 AM UTC 24 89754909 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_regwen.1906988931 Aug 25 07:53:35 AM UTC 24 Aug 25 07:58:28 AM UTC 24 2761653708 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.1541394602 Aug 25 07:58:27 AM UTC 24 Aug 25 07:58:35 AM UTC 24 681905071 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.726375733 Aug 25 07:58:23 AM UTC 24 Aug 25 07:58:40 AM UTC 24 888111069 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.4169859250 Aug 25 07:58:39 AM UTC 24 Aug 25 07:58:41 AM UTC 24 53386484 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.2557691436 Aug 25 07:56:40 AM UTC 24 Aug 25 07:58:49 AM UTC 24 1394376237 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.3518431932 Aug 25 07:57:40 AM UTC 24 Aug 25 07:58:57 AM UTC 24 2986290919 ps
T112 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.3698385061 Aug 25 07:52:41 AM UTC 24 Aug 25 07:59:22 AM UTC 24 14275200015 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.3266113742 Aug 25 07:57:49 AM UTC 24 Aug 25 07:59:33 AM UTC 24 554058647 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.2645132343 Aug 25 07:58:41 AM UTC 24 Aug 25 07:59:33 AM UTC 24 1745591729 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.2539928188 Aug 25 07:59:09 AM UTC 24 Aug 25 07:59:34 AM UTC 24 303003663 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.2394099329 Aug 25 07:59:35 AM UTC 24 Aug 25 07:59:42 AM UTC 24 209630082 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.3646932492 Aug 25 07:59:35 AM UTC 24 Aug 25 07:59:43 AM UTC 24 463236858 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.340459640 Aug 25 07:59:33 AM UTC 24 Aug 25 07:59:46 AM UTC 24 126869098 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.1758226816 Aug 25 07:52:20 AM UTC 24 Aug 25 07:59:53 AM UTC 24 11128641451 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3835584645 Aug 25 07:59:54 AM UTC 24 Aug 25 07:59:56 AM UTC 24 95029265 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.4288079865 Aug 25 07:54:40 AM UTC 24 Aug 25 07:59:59 AM UTC 24 10328860777 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.2553730554 Aug 25 07:59:57 AM UTC 24 Aug 25 08:00:05 AM UTC 24 362270625 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.2915607006 Aug 25 08:00:00 AM UTC 24 Aug 25 08:00:08 AM UTC 24 98728249 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.1171083549 Aug 25 07:56:12 AM UTC 24 Aug 25 08:00:11 AM UTC 24 1932865579 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.4021280055 Aug 25 08:00:12 AM UTC 24 Aug 25 08:00:15 AM UTC 24 14413137 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.2123592292 Aug 25 07:58:50 AM UTC 24 Aug 25 08:00:29 AM UTC 24 5867021788 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_smoke.3059935966 Aug 25 08:00:15 AM UTC 24 Aug 25 08:00:30 AM UTC 24 362938650 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.16020413 Aug 25 07:53:05 AM UTC 24 Aug 25 08:00:42 AM UTC 24 12378095618 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.2408104752 Aug 25 07:52:20 AM UTC 24 Aug 25 08:00:47 AM UTC 24 5323428673 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.1806674757 Aug 25 07:52:35 AM UTC 24 Aug 25 08:01:07 AM UTC 24 50695841352 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.3583289401 Aug 25 07:54:48 AM UTC 24 Aug 25 08:01:07 AM UTC 24 2901704237 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access.875280257 Aug 25 08:00:48 AM UTC 24 Aug 25 08:01:11 AM UTC 24 1981943091 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.1665447879 Aug 25 07:52:21 AM UTC 24 Aug 25 08:01:24 AM UTC 24 15529151789 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.2888597034 Aug 25 08:01:25 AM UTC 24 Aug 25 08:01:31 AM UTC 24 202089814 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_bijection.894760211 Aug 25 08:00:32 AM UTC 24 Aug 25 08:01:32 AM UTC 24 6740700322 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.2702054046 Aug 25 07:52:21 AM UTC 24 Aug 25 08:01:43 AM UTC 24 5860944671 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.1761909901 Aug 25 08:01:49 AM UTC 24 Aug 25 08:01:51 AM UTC 24 34081121 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.668992779 Aug 25 08:01:11 AM UTC 24 Aug 25 08:01:59 AM UTC 24 416522367 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.1994332713 Aug 25 08:01:52 AM UTC 24 Aug 25 08:02:06 AM UTC 24 456232947 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.1900324563 Aug 25 08:02:00 AM UTC 24 Aug 25 08:02:09 AM UTC 24 70000671 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.3192309221 Aug 25 08:01:08 AM UTC 24 Aug 25 08:02:44 AM UTC 24 1071842589 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_alert_test.68976633 Aug 25 08:02:45 AM UTC 24 Aug 25 08:02:47 AM UTC 24 24994637 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_smoke.3905460325 Aug 25 08:02:48 AM UTC 24 Aug 25 08:02:59 AM UTC 24 133415364 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.3662805215 Aug 25 07:52:46 AM UTC 24 Aug 25 08:03:00 AM UTC 24 10175076238 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_bijection.808780431 Aug 25 08:03:01 AM UTC 24 Aug 25 08:03:20 AM UTC 24 928229983 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.3139223792 Aug 25 07:53:17 AM UTC 24 Aug 25 08:03:29 AM UTC 24 5941253478 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3763908790 Aug 25 07:57:04 AM UTC 24 Aug 25 08:03:54 AM UTC 24 8361761969 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.1102815092 Aug 25 08:00:44 AM UTC 24 Aug 25 08:03:55 AM UTC 24 8791664107 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.2761008524 Aug 25 07:52:19 AM UTC 24 Aug 25 08:04:00 AM UTC 24 47301897716 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.1095607330 Aug 25 07:52:37 AM UTC 24 Aug 25 08:04:06 AM UTC 24 3250854682 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.1560646093 Aug 25 08:04:01 AM UTC 24 Aug 25 08:04:12 AM UTC 24 533719670 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.1457606312 Aug 25 07:56:29 AM UTC 24 Aug 25 08:04:23 AM UTC 24 4388821501 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.1678505014 Aug 25 07:52:35 AM UTC 24 Aug 25 08:04:31 AM UTC 24 7240018319 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.1370643678 Aug 25 08:04:32 AM UTC 24 Aug 25 08:04:34 AM UTC 24 30628042 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.3771484632 Aug 25 08:04:35 AM UTC 24 Aug 25 08:04:51 AM UTC 24 459243113 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.2481475323 Aug 25 08:04:41 AM UTC 24 Aug 25 08:04:46 AM UTC 24 226911878 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3746062684 Aug 25 08:02:07 AM UTC 24 Aug 25 08:04:48 AM UTC 24 10451106165 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_alert_test.1345146202 Aug 25 08:04:52 AM UTC 24 Aug 25 08:04:54 AM UTC 24 16649764 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.505369923 Aug 25 07:59:22 AM UTC 24 Aug 25 08:04:56 AM UTC 24 14232204778 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_smoke.2968650351 Aug 25 08:04:55 AM UTC 24 Aug 25 08:04:59 AM UTC 24 98855052 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.887070056 Aug 25 07:58:58 AM UTC 24 Aug 25 08:05:13 AM UTC 24 15087548530 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.4216468055 Aug 25 07:54:00 AM UTC 24 Aug 25 08:05:14 AM UTC 24 71687093109 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_bijection.3329889466 Aug 25 08:04:59 AM UTC 24 Aug 25 08:05:19 AM UTC 24 238069125 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access.804401538 Aug 25 08:05:15 AM UTC 24 Aug 25 08:05:28 AM UTC 24 821152532 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access.3561648191 Aug 25 08:03:30 AM UTC 24 Aug 25 08:05:29 AM UTC 24 1229454581 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.4227004974 Aug 25 08:05:30 AM UTC 24 Aug 25 08:05:33 AM UTC 24 42815505 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_executable.3497012717 Aug 25 07:53:34 AM UTC 24 Aug 25 08:05:43 AM UTC 24 32468572177 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.3416236431 Aug 25 08:05:34 AM UTC 24 Aug 25 08:05:43 AM UTC 24 356682587 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.3360557286 Aug 25 08:05:29 AM UTC 24 Aug 25 08:05:47 AM UTC 24 95303036 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.4255714517 Aug 25 08:03:56 AM UTC 24 Aug 25 08:05:58 AM UTC 24 582787634 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.1974208434 Aug 25 08:05:59 AM UTC 24 Aug 25 08:06:02 AM UTC 24 29842027 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_regwen.3265222655 Aug 25 07:52:49 AM UTC 24 Aug 25 08:06:16 AM UTC 24 37297016245 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.1184889975 Aug 25 07:52:19 AM UTC 24 Aug 25 08:06:17 AM UTC 24 2515852424 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.3619920575 Aug 25 08:06:02 AM UTC 24 Aug 25 08:06:21 AM UTC 24 2718736477 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.870319696 Aug 25 07:57:46 AM UTC 24 Aug 25 08:06:22 AM UTC 24 49843027187 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.367007631 Aug 25 07:55:07 AM UTC 24 Aug 25 08:06:25 AM UTC 24 11711284625 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.2511026727 Aug 25 08:06:17 AM UTC 24 Aug 25 08:06:25 AM UTC 24 301278868 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_alert_test.1671591631 Aug 25 08:06:26 AM UTC 24 Aug 25 08:06:29 AM UTC 24 17105203 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_smoke.3285864231 Aug 25 08:06:26 AM UTC 24 Aug 25 08:06:57 AM UTC 24 2241589653 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.1624506697 Aug 25 07:57:42 AM UTC 24 Aug 25 08:07:12 AM UTC 24 10311544189 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.130732143 Aug 25 07:53:44 AM UTC 24 Aug 25 08:07:16 AM UTC 24 2537903674 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.808925657 Aug 25 07:59:43 AM UTC 24 Aug 25 08:07:21 AM UTC 24 3874178363 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.4180332276 Aug 25 07:52:35 AM UTC 24 Aug 25 08:07:27 AM UTC 24 2324344330 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.1707647608 Aug 25 08:00:30 AM UTC 24 Aug 25 08:07:28 AM UTC 24 48278137971 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_bijection.3069445249 Aug 25 08:06:26 AM UTC 24 Aug 25 08:07:32 AM UTC 24 43398030004 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.950002009 Aug 25 08:07:32 AM UTC 24 Aug 25 08:07:46 AM UTC 24 577880968 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.2991230538 Aug 25 08:07:46 AM UTC 24 Aug 25 08:07:49 AM UTC 24 82953372 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.1833172473 Aug 25 08:07:50 AM UTC 24 Aug 25 08:07:57 AM UTC 24 454932257 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.503289262 Aug 25 07:53:31 AM UTC 24 Aug 25 08:08:02 AM UTC 24 2916436665 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.2207328848 Aug 25 08:07:16 AM UTC 24 Aug 25 08:08:04 AM UTC 24 198616535 ps
T173 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.2627108652 Aug 25 08:01:08 AM UTC 24 Aug 25 08:08:06 AM UTC 24 49526916276 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.3912129043 Aug 25 08:07:58 AM UTC 24 Aug 25 08:08:07 AM UTC 24 612248316 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_alert_test.1354926549 Aug 25 08:08:06 AM UTC 24 Aug 25 08:08:08 AM UTC 24 14531090 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_smoke.2219553999 Aug 25 08:08:07 AM UTC 24 Aug 25 08:08:26 AM UTC 24 1156760105 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.572360476 Aug 25 08:07:22 AM UTC 24 Aug 25 08:08:29 AM UTC 24 143287601 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access.2619546024 Aug 25 08:08:30 AM UTC 24 Aug 25 08:08:34 AM UTC 24 232606811 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access.1675978404 Aug 25 08:06:58 AM UTC 24 Aug 25 08:08:41 AM UTC 24 753878010 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_bijection.2301533341 Aug 25 08:08:09 AM UTC 24 Aug 25 08:08:49 AM UTC 24 2280964199 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.898985336 Aug 25 08:03:21 AM UTC 24 Aug 25 08:08:56 AM UTC 24 2413236645 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.1220319347 Aug 25 08:06:26 AM UTC 24 Aug 25 08:09:00 AM UTC 24 896451474 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.1908289120 Aug 25 08:08:42 AM UTC 24 Aug 25 08:09:10 AM UTC 24 88374837 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.1807927898 Aug 25 08:08:50 AM UTC 24 Aug 25 08:09:11 AM UTC 24 1028050615 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_executable.1694388662 Aug 25 07:52:19 AM UTC 24 Aug 25 08:09:11 AM UTC 24 13773971824 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.445656024 Aug 25 08:08:57 AM UTC 24 Aug 25 08:09:11 AM UTC 24 948749085 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.2088920910 Aug 25 08:09:12 AM UTC 24 Aug 25 08:09:15 AM UTC 24 84932631 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.3505864765 Aug 25 08:09:15 AM UTC 24 Aug 25 08:09:21 AM UTC 24 98689286 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.1555643226 Aug 25 08:09:12 AM UTC 24 Aug 25 08:09:21 AM UTC 24 97188769 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.4159622766 Aug 25 08:04:47 AM UTC 24 Aug 25 08:09:49 AM UTC 24 679059769 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_alert_test.2731689522 Aug 25 08:09:50 AM UTC 24 Aug 25 08:09:52 AM UTC 24 17118850 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_smoke.2322190246 Aug 25 08:09:53 AM UTC 24 Aug 25 08:09:57 AM UTC 24 42332173 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_executable.2770707676 Aug 25 07:52:35 AM UTC 24 Aug 25 08:10:12 AM UTC 24 31667153440 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_executable.2354757335 Aug 25 07:55:35 AM UTC 24 Aug 25 08:10:26 AM UTC 24 79559893819 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.2864367968 Aug 25 08:05:14 AM UTC 24 Aug 25 08:10:29 AM UTC 24 7888289663 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.2130149483 Aug 25 08:04:06 AM UTC 24 Aug 25 08:10:53 AM UTC 24 1520411504 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.875864515 Aug 25 08:05:20 AM UTC 24 Aug 25 08:11:00 AM UTC 24 8899444003 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access.2730948887 Aug 25 08:10:29 AM UTC 24 Aug 25 08:11:04 AM UTC 24 593837867 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.1463931905 Aug 25 08:11:01 AM UTC 24 Aug 25 08:11:06 AM UTC 24 47290624 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.2216640328 Aug 25 07:56:43 AM UTC 24 Aug 25 08:11:09 AM UTC 24 8200229677 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.1787309336 Aug 25 08:11:07 AM UTC 24 Aug 25 08:11:11 AM UTC 24 785643595 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_bijection.5245411 Aug 25 08:10:13 AM UTC 24 Aug 25 08:11:21 AM UTC 24 9796915213 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.4176370567 Aug 25 08:00:12 AM UTC 24 Aug 25 08:11:26 AM UTC 24 20502084999 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.75666388 Aug 25 08:11:27 AM UTC 24 Aug 25 08:11:29 AM UTC 24 29374005 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.2009523886 Aug 25 08:11:30 AM UTC 24 Aug 25 08:11:38 AM UTC 24 230925006 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.3389541329 Aug 25 08:06:30 AM UTC 24 Aug 25 08:11:41 AM UTC 24 2475302054 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.3778831354 Aug 25 08:11:39 AM UTC 24 Aug 25 08:11:45 AM UTC 24 113423113 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.1681138786 Aug 25 08:09:00 AM UTC 24 Aug 25 08:11:50 AM UTC 24 2802930357 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_alert_test.2680770275 Aug 25 08:11:52 AM UTC 24 Aug 25 08:11:54 AM UTC 24 48659089 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.2730628146 Aug 25 07:52:18 AM UTC 24 Aug 25 08:11:57 AM UTC 24 134801899810 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.3274603635 Aug 25 08:01:31 AM UTC 24 Aug 25 08:12:00 AM UTC 24 1993888175 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_smoke.952173478 Aug 25 08:18:04 AM UTC 24 Aug 25 08:18:10 AM UTC 24 727918479 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.1216913211 Aug 25 08:11:05 AM UTC 24 Aug 25 08:12:01 AM UTC 24 230645737 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_smoke.3843552281 Aug 25 08:11:55 AM UTC 24 Aug 25 08:12:32 AM UTC 24 1431314465 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_bijection.4270541870 Aug 25 08:12:01 AM UTC 24 Aug 25 08:12:35 AM UTC 24 2113711517 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access.1900371046 Aug 25 08:12:33 AM UTC 24 Aug 25 08:12:39 AM UTC 24 152720827 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.2690912292 Aug 25 08:03:41 AM UTC 24 Aug 25 08:12:41 AM UTC 24 12454492377 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.1584380947 Aug 25 08:11:41 AM UTC 24 Aug 25 08:12:57 AM UTC 24 730406714 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.2106234256 Aug 25 08:12:42 AM UTC 24 Aug 25 08:12:59 AM UTC 24 284986929 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.2699572253 Aug 25 07:58:42 AM UTC 24 Aug 25 08:12:59 AM UTC 24 54629384807 ps
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