Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	151176794	1			T3	614		T4	1010		T5	2034
instr_valid_dis	118476168	1			T3	614		T4	1010		T5	2034
instr_en	22245966	1			T65	57812		T18	181520		T53	62408

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10006470	1			T40	732		T18	1768		T54	39416
sram_ifetch_valid_disable	116763345	1			T3	614		T4	1010		T5	2034
sram_ifetch_enable	24406979	1			T24	7548		T65	30236		T17	17990

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	151176794	1			T3	614		T4	1010		T5	2034
hw_debug_en_valid_off	117357150	1			T3	614		T4	1010		T5	2034
hw_debug_en_on	22544495	1			T65	8074		T40	732		T18	76062

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	116763345	1			T3	614		T4	1010		T5	2034
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	103311414	1			T3	614		T4	1010		T5	2034
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8937083	1			T65	35720		T18	143744		T53	62408
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4008672	1			T54	24484		T149	610		T135	13146
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1771124	1			T135	13146		T136	24198		T141	54368
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1559522	1			T54	24484		T149	610		T48	2354
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3913866	1			T40	732		T18	1768		T54	14932
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1586418	1			T19	14638		T139	45486		T140	20000
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1525680	1			T18	1768		T146	38858		T149	32644
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9788267	1			T18	42094		T19	33986		T138	45628
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4453427	1			T138	45628		T146	12958		T135	49616
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3264746	1			T18	42094		T19	33986		T155	87108

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9457161	1			T65	22092		T18	36008		T138	36666
lc_exec_en	8842362	1			T65	8074		T18	32200		T138	33920
valid_exec_dis	113506517	1			T3	614		T4	1010		T5	2034
invalid_exec_dis	34413449	1			T24	7548		T65	30236		T17	17990