Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44


Total tests in report: 1027
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
63.57 63.57 89.49 89.49 68.48 68.48 62.14 62.14 23.81 23.81 77.29 77.29 93.95 93.95 29.80 29.80 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.3566888640
79.80 16.23 94.58 5.08 80.92 12.44 64.84 2.70 71.43 47.62 85.51 8.21 95.87 1.92 65.45 35.65 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.1683261174
89.43 9.63 97.54 2.97 84.83 3.91 97.09 32.25 80.95 9.52 91.06 5.56 96.31 0.44 78.24 12.80 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.3003266292
92.86 3.42 98.56 1.02 84.95 0.12 97.09 0.00 100.00 19.05 93.00 1.93 97.05 0.74 79.34 1.10 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.177624220
93.91 1.06 98.90 0.34 87.44 2.49 98.47 1.39 100.00 0.00 94.69 1.69 97.64 0.59 80.26 0.91 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.2463822399
94.83 0.92 99.07 0.17 89.57 2.13 98.65 0.17 100.00 0.00 95.89 1.21 97.64 0.00 83.00 2.74 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_regwen.1005632474
95.60 0.76 99.07 0.00 90.17 0.59 98.65 0.00 100.00 0.00 95.89 0.00 97.64 0.00 87.75 4.75 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.305797188
95.90 0.30 99.07 0.00 90.28 0.12 98.65 0.00 100.00 0.00 95.89 0.00 97.64 0.00 89.76 2.01 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2498938247
96.19 0.29 99.07 0.00 90.28 0.00 98.65 0.00 100.00 0.00 95.89 0.00 97.64 0.00 91.77 2.01 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.3855705075
96.37 0.18 99.07 0.00 90.28 0.00 98.72 0.07 100.00 0.00 95.89 0.00 98.82 1.18 91.77 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.382671452
96.54 0.18 99.07 0.00 90.28 0.00 98.72 0.00 100.00 0.00 95.89 0.00 98.97 0.15 92.87 1.10 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.1585036574
96.71 0.17 99.15 0.08 90.28 0.00 99.55 0.83 100.00 0.00 96.14 0.24 98.97 0.00 92.87 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.815233448
96.87 0.16 99.15 0.00 90.28 0.00 99.55 0.00 100.00 0.00 96.14 0.00 98.97 0.00 93.97 1.10 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_executable.1308473109
97.02 0.16 99.15 0.00 90.64 0.36 99.55 0.00 100.00 0.00 96.14 0.00 98.97 0.00 94.70 0.73 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.564348837
97.12 0.10 99.15 0.00 90.64 0.00 99.55 0.00 100.00 0.00 96.14 0.00 98.97 0.00 95.43 0.73 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1910013481
97.21 0.09 99.15 0.00 91.00 0.36 99.62 0.07 100.00 0.00 96.14 0.00 98.97 0.00 95.61 0.18 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_alert_test.1342444692
97.29 0.08 99.15 0.00 91.00 0.00 99.62 0.00 100.00 0.00 96.14 0.00 98.97 0.00 96.16 0.55 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3911189341
97.34 0.05 99.15 0.00 91.00 0.00 99.62 0.00 100.00 0.00 96.14 0.00 98.97 0.00 96.53 0.37 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2609521605
97.39 0.05 99.15 0.00 91.00 0.00 99.62 0.00 100.00 0.00 96.14 0.00 98.97 0.00 96.89 0.37 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_regwen.2685670059
97.42 0.03 99.15 0.00 91.00 0.00 99.62 0.00 100.00 0.00 96.14 0.00 98.97 0.00 97.07 0.18 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.459541127
97.45 0.03 99.15 0.00 91.00 0.00 99.62 0.00 100.00 0.00 96.14 0.00 98.97 0.00 97.26 0.18 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2620000957
97.47 0.03 99.15 0.00 91.00 0.00 99.62 0.00 100.00 0.00 96.14 0.00 98.97 0.00 97.44 0.18 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.3448608139
97.49 0.02 99.15 0.00 91.00 0.00 99.62 0.00 100.00 0.00 96.14 0.00 99.12 0.15 97.44 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.507065215
97.51 0.01 99.15 0.00 91.00 0.00 99.72 0.10 100.00 0.00 96.14 0.00 99.12 0.00 97.44 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all.1088599229

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2481788362
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3173572728
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1143797083
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1998673776
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3319105223
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3778775123
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3763877391
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.374322062
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.799262402
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2030106931
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1696279365
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.261143156
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.4154674617
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.61528599
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.242489477
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3255408108
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.4180837680
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3017087189
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4119768308
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1163564048
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2863456651
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2399138064
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1286635858
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2158952077
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.4088703478
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1953695812
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.961964101
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3216987655
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.481405798
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1375046231
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1086454218
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3829034867
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1714242422
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2420259504
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1516451142
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2107097594
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3677706177
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2718604255
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1128196128
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3162867376
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1148088135
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1567846419
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.881800758
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.4189730814
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2888803559
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2921001150
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2000230538
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.16820434
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.25465116
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3335187156
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1666470354
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1121756209
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3922563445
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2284373508
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1011588418
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.518117650
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2542630528
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.835118266
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1365022754
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1421952363
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1285823866
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3505620735
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.154192094
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.884945873
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2722043348
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.349137176
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2763367489
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3603710295
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.822766817
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.390379970
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.510426726
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.455298443
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1835682321
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3044607445
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3907686820
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1020836821
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2861636408
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3915420242
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2317035636
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.297844981
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.685767712
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.783019142
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1552558931
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.70523511
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/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.2317318867
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access.3275836433
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.3279006793
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.1504928527
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_regwen.3851898660
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_smoke.1016202215
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all.3872075444
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.1411476103
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.997593105
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.156539083
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.3367941818
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.2681788946
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.409351548
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.579069727
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.268880774
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.2455996375
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.3663284533
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.2233570159
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.2579667576
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.2366763999
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.3066057483
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.841678306
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.260313054
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.2089446802
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1992597968
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.690620945
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.1435792748
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.3989035549
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.3826741536
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.2526478721
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.3533202075
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.1467573923
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.3811226766
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.1550633364
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3261831976
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.105337412
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.1468327607
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.422131388
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.3659801000
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.2094927274
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.3364145241
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all.3743891864
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3933588351
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.192484308
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.3049122981
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.1386174278
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.1733599664
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.3784761531
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.2579832291
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.2540785213
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.3856604692
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.3775416829
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.1315676405
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.3904266682
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.1817021589
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.403937033
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.610965476
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.2608274456
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.3860835979
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.208067474
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.685491928
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.4044941713
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.2104771641



Total test records in report: 1027
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.3110076668 Aug 27 07:58:43 AM UTC 24 Aug 27 07:58:45 AM UTC 24 74958560 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.1103598017 Aug 27 07:58:43 AM UTC 24 Aug 27 07:58:45 AM UTC 24 62250548 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.2078708380 Aug 27 07:58:43 AM UTC 24 Aug 27 07:58:45 AM UTC 24 190649880 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_alert_test.1342444692 Aug 27 07:58:44 AM UTC 24 Aug 27 07:58:46 AM UTC 24 19248539 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.875327206 Aug 27 07:58:44 AM UTC 24 Aug 27 07:58:46 AM UTC 24 81771027 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.2463822399 Aug 27 07:58:43 AM UTC 24 Aug 27 07:58:47 AM UTC 24 807205573 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.3566888640 Aug 27 07:58:43 AM UTC 24 Aug 27 07:58:48 AM UTC 24 94985098 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.2219624950 Aug 27 07:58:44 AM UTC 24 Aug 27 07:58:48 AM UTC 24 222089297 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access.1411652613 Aug 27 07:58:43 AM UTC 24 Aug 27 07:58:48 AM UTC 24 505752743 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.2347264868 Aug 27 07:58:43 AM UTC 24 Aug 27 07:58:49 AM UTC 24 93609115 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.3003266292 Aug 27 07:58:43 AM UTC 24 Aug 27 07:58:50 AM UTC 24 674755484 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.3218692948 Aug 27 07:58:44 AM UTC 24 Aug 27 07:58:50 AM UTC 24 177811114 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.3041579619 Aug 27 07:58:43 AM UTC 24 Aug 27 07:58:50 AM UTC 24 3404253986 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_smoke.835734325 Aug 27 07:58:43 AM UTC 24 Aug 27 07:58:51 AM UTC 24 108035836 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_smoke.258348117 Aug 27 07:58:44 AM UTC 24 Aug 27 07:58:52 AM UTC 24 439877151 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_smoke.722371056 Aug 27 07:58:43 AM UTC 24 Aug 27 07:58:52 AM UTC 24 153161055 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.458242726 Aug 27 07:58:44 AM UTC 24 Aug 27 07:58:54 AM UTC 24 461389060 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access.2364452406 Aug 27 07:58:43 AM UTC 24 Aug 27 07:58:55 AM UTC 24 227019088 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.706451291 Aug 27 07:58:43 AM UTC 24 Aug 27 07:58:55 AM UTC 24 74165000 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.3448608139 Aug 27 07:58:43 AM UTC 24 Aug 27 07:59:03 AM UTC 24 346322128 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access.4037706253 Aug 27 07:58:44 AM UTC 24 Aug 27 07:59:05 AM UTC 24 4842528949 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.1295685744 Aug 27 07:58:43 AM UTC 24 Aug 27 07:59:10 AM UTC 24 219487075 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_bijection.517549662 Aug 27 07:58:43 AM UTC 24 Aug 27 07:59:31 AM UTC 24 11620940914 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_bijection.568397461 Aug 27 07:58:43 AM UTC 24 Aug 27 07:59:33 AM UTC 24 3531787295 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1847229139 Aug 27 07:58:43 AM UTC 24 Aug 27 07:59:34 AM UTC 24 8405607232 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_alert_test.2246238198 Aug 27 07:59:32 AM UTC 24 Aug 27 07:59:34 AM UTC 24 54690088 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.815233448 Aug 27 07:59:32 AM UTC 24 Aug 27 07:59:34 AM UTC 24 28143295 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_alert_test.39075741 Aug 27 07:59:33 AM UTC 24 Aug 27 07:59:35 AM UTC 24 95232514 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.2430530300 Aug 27 07:59:33 AM UTC 24 Aug 27 07:59:35 AM UTC 24 30280689 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.4921169 Aug 27 07:59:33 AM UTC 24 Aug 27 07:59:37 AM UTC 24 868940113 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.1396874148 Aug 27 07:59:33 AM UTC 24 Aug 27 07:59:37 AM UTC 24 46422097 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.2591681183 Aug 27 07:59:31 AM UTC 24 Aug 27 07:59:38 AM UTC 24 524872271 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.2356525421 Aug 27 07:59:33 AM UTC 24 Aug 27 07:59:38 AM UTC 24 1364594682 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.3274695762 Aug 27 07:59:33 AM UTC 24 Aug 27 07:59:38 AM UTC 24 241465239 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.889194716 Aug 27 07:59:32 AM UTC 24 Aug 27 07:59:39 AM UTC 24 411612296 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access.3277749252 Aug 27 07:59:34 AM UTC 24 Aug 27 07:59:39 AM UTC 24 552341334 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.2386743816 Aug 27 07:59:32 AM UTC 24 Aug 27 07:59:39 AM UTC 24 597467482 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.4232831863 Aug 27 07:59:32 AM UTC 24 Aug 27 07:59:39 AM UTC 24 326118767 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.4278823236 Aug 27 07:59:39 AM UTC 24 Aug 27 07:59:41 AM UTC 24 28273897 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access.3713300397 Aug 27 07:59:33 AM UTC 24 Aug 27 07:59:43 AM UTC 24 180180093 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_alert_test.3006670370 Aug 27 07:59:43 AM UTC 24 Aug 27 07:59:45 AM UTC 24 20071522 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.1049221531 Aug 27 07:59:41 AM UTC 24 Aug 27 07:59:46 AM UTC 24 1747263732 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_smoke.389833107 Aug 27 07:59:33 AM UTC 24 Aug 27 07:59:46 AM UTC 24 673159994 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.159756289 Aug 27 07:59:41 AM UTC 24 Aug 27 07:59:47 AM UTC 24 188636409 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.4190230892 Aug 27 07:59:33 AM UTC 24 Aug 27 07:59:50 AM UTC 24 5015794062 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.564348837 Aug 27 07:59:37 AM UTC 24 Aug 27 07:59:51 AM UTC 24 6980654848 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.1257868196 Aug 27 07:59:37 AM UTC 24 Aug 27 07:59:52 AM UTC 24 296547660 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_smoke.205377776 Aug 27 07:59:33 AM UTC 24 Aug 27 07:59:53 AM UTC 24 1030371928 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_smoke.4256710266 Aug 27 07:59:43 AM UTC 24 Aug 27 07:59:54 AM UTC 24 163999220 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_bijection.3684653210 Aug 27 07:58:44 AM UTC 24 Aug 27 07:59:54 AM UTC 24 12719439130 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.795212424 Aug 27 07:59:41 AM UTC 24 Aug 27 07:59:55 AM UTC 24 708858969 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.2691155178 Aug 27 07:59:52 AM UTC 24 Aug 27 08:00:01 AM UTC 24 232776393 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access.1362747652 Aug 27 07:59:48 AM UTC 24 Aug 27 08:00:02 AM UTC 24 694396249 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.2083798253 Aug 27 07:59:33 AM UTC 24 Aug 27 08:00:04 AM UTC 24 86780355 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.339942216 Aug 27 08:00:02 AM UTC 24 Aug 27 08:00:08 AM UTC 24 75053609 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.931508104 Aug 27 07:59:54 AM UTC 24 Aug 27 08:00:08 AM UTC 24 3761868104 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_bijection.2632093249 Aug 27 07:59:48 AM UTC 24 Aug 27 08:00:10 AM UTC 24 281994361 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_alert_test.2248079497 Aug 27 08:00:11 AM UTC 24 Aug 27 08:00:13 AM UTC 24 11786534 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.621451527 Aug 27 08:00:06 AM UTC 24 Aug 27 08:00:14 AM UTC 24 134765225 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.1683261174 Aug 27 07:59:41 AM UTC 24 Aug 27 08:00:15 AM UTC 24 644805996 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.3728537880 Aug 27 07:59:31 AM UTC 24 Aug 27 08:00:18 AM UTC 24 904789215 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.2262199302 Aug 27 08:00:02 AM UTC 24 Aug 27 08:00:21 AM UTC 24 2941274199 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access.3275836433 Aug 27 08:00:19 AM UTC 24 Aug 27 08:00:34 AM UTC 24 1634194689 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.4213483007 Aug 27 07:59:32 AM UTC 24 Aug 27 08:00:39 AM UTC 24 906118147 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_bijection.1189196834 Aug 27 07:59:34 AM UTC 24 Aug 27 08:00:41 AM UTC 24 3372484404 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_executable.1136036298 Aug 27 07:59:39 AM UTC 24 Aug 27 08:00:41 AM UTC 24 8728345648 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.997593105 Aug 27 08:00:42 AM UTC 24 Aug 27 08:00:46 AM UTC 24 42842500 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.3233605501 Aug 27 07:59:31 AM UTC 24 Aug 27 08:00:50 AM UTC 24 175624349 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.658341194 Aug 27 08:00:42 AM UTC 24 Aug 27 08:00:52 AM UTC 24 701918661 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.1504928527 Aug 27 08:00:53 AM UTC 24 Aug 27 08:00:55 AM UTC 24 32380427 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.1139771506 Aug 27 07:59:37 AM UTC 24 Aug 27 08:01:00 AM UTC 24 134973786 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.933065141 Aug 27 08:00:58 AM UTC 24 Aug 27 08:01:02 AM UTC 24 362864902 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_bijection.1637459606 Aug 27 07:59:33 AM UTC 24 Aug 27 08:01:04 AM UTC 24 5581425959 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.1590891015 Aug 27 08:00:57 AM UTC 24 Aug 27 08:01:05 AM UTC 24 1226055140 ps
T173 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_alert_test.3522841946 Aug 27 08:01:04 AM UTC 24 Aug 27 08:01:07 AM UTC 24 161850473 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_smoke.1016202215 Aug 27 08:00:15 AM UTC 24 Aug 27 08:01:08 AM UTC 24 1288895949 ps
T174 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.27450782 Aug 27 08:00:35 AM UTC 24 Aug 27 08:01:09 AM UTC 24 192924556 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_bijection.1368122432 Aug 27 08:00:15 AM UTC 24 Aug 27 08:01:29 AM UTC 24 2508967967 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.1585036574 Aug 27 07:58:43 AM UTC 24 Aug 27 08:01:34 AM UTC 24 6482669588 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.1488994398 Aug 27 07:59:54 AM UTC 24 Aug 27 08:01:41 AM UTC 24 1834648054 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.268880774 Aug 27 08:01:42 AM UTC 24 Aug 27 08:01:50 AM UTC 24 242327455 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.2579667576 Aug 27 08:01:30 AM UTC 24 Aug 27 08:01:57 AM UTC 24 2826852424 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.801027172 Aug 27 08:00:08 AM UTC 24 Aug 27 08:02:00 AM UTC 24 1047909458 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.260313054 Aug 27 08:01:06 AM UTC 24 Aug 27 08:02:04 AM UTC 24 431388702 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.579069727 Aug 27 08:01:58 AM UTC 24 Aug 27 08:02:07 AM UTC 24 830851611 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.2681788946 Aug 27 08:01:09 AM UTC 24 Aug 27 08:02:11 AM UTC 24 7837519830 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.3066057483 Aug 27 08:02:13 AM UTC 24 Aug 27 08:02:15 AM UTC 24 87809463 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.3663284533 Aug 27 08:02:16 AM UTC 24 Aug 27 08:02:31 AM UTC 24 5517422979 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2498938247 Aug 27 08:01:01 AM UTC 24 Aug 27 08:02:33 AM UTC 24 14128699641 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_regwen.2483802739 Aug 27 07:58:43 AM UTC 24 Aug 27 08:02:35 AM UTC 24 2184735023 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.2455996375 Aug 27 08:02:32 AM UTC 24 Aug 27 08:02:40 AM UTC 24 184951396 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.3367941818 Aug 27 08:02:40 AM UTC 24 Aug 27 08:02:42 AM UTC 24 21711938 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.3364145241 Aug 27 08:02:43 AM UTC 24 Aug 27 08:02:47 AM UTC 24 207784839 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.1850440223 Aug 27 07:59:33 AM UTC 24 Aug 27 08:03:12 AM UTC 24 1003839546 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2609521605 Aug 27 07:58:44 AM UTC 24 Aug 27 08:03:18 AM UTC 24 1035686344 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.1411476103 Aug 27 08:00:17 AM UTC 24 Aug 27 08:03:24 AM UTC 24 11676008620 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.1435792748 Aug 27 08:01:50 AM UTC 24 Aug 27 08:03:29 AM UTC 24 150685507 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.1468327607 Aug 27 08:03:24 AM UTC 24 Aug 27 08:03:40 AM UTC 24 1665550258 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_regwen.1675243049 Aug 27 07:59:32 AM UTC 24 Aug 27 08:03:50 AM UTC 24 29822649746 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.982686708 Aug 27 07:58:43 AM UTC 24 Aug 27 08:03:50 AM UTC 24 19568305298 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.1467573923 Aug 27 08:03:51 AM UTC 24 Aug 27 08:03:58 AM UTC 24 1237847180 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.1483215197 Aug 27 07:58:43 AM UTC 24 Aug 27 08:03:59 AM UTC 24 30466486418 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.3049122981 Aug 27 08:03:51 AM UTC 24 Aug 27 08:04:05 AM UTC 24 81528421 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.2902562325 Aug 27 07:58:43 AM UTC 24 Aug 27 08:04:07 AM UTC 24 10619762452 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.3659801000 Aug 27 08:04:08 AM UTC 24 Aug 27 08:04:10 AM UTC 24 47204943 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1992597968 Aug 27 08:02:34 AM UTC 24 Aug 27 08:04:16 AM UTC 24 6529462884 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.1609635431 Aug 27 07:59:33 AM UTC 24 Aug 27 08:04:18 AM UTC 24 17236631043 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.3811226766 Aug 27 08:03:41 AM UTC 24 Aug 27 08:04:20 AM UTC 24 431549532 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3261831976 Aug 27 08:04:11 AM UTC 24 Aug 27 08:04:21 AM UTC 24 343680285 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.3826741536 Aug 27 08:04:21 AM UTC 24 Aug 27 08:04:24 AM UTC 24 95827516 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.1550633364 Aug 27 08:04:17 AM UTC 24 Aug 27 08:04:25 AM UTC 24 98184695 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.3296133545 Aug 27 07:59:34 AM UTC 24 Aug 27 08:04:30 AM UTC 24 23865744581 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.2424056550 Aug 27 07:58:43 AM UTC 24 Aug 27 08:04:34 AM UTC 24 4805127573 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.1232387729 Aug 27 07:59:33 AM UTC 24 Aug 27 08:04:37 AM UTC 24 4742862093 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_executable.1090161390 Aug 27 07:59:33 AM UTC 24 Aug 27 08:04:38 AM UTC 24 16558241691 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.2526478721 Aug 27 08:03:13 AM UTC 24 Aug 27 08:04:44 AM UTC 24 31780321053 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.3856604692 Aug 27 08:04:45 AM UTC 24 Aug 27 08:04:51 AM UTC 24 187368742 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.2233570159 Aug 27 08:01:07 AM UTC 24 Aug 27 08:04:56 AM UTC 24 382273962 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.1817021589 Aug 27 08:04:38 AM UTC 24 Aug 27 08:04:56 AM UTC 24 319450557 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.2540785213 Aug 27 08:04:57 AM UTC 24 Aug 27 08:05:08 AM UTC 24 806793388 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.3425328583 Aug 27 07:59:48 AM UTC 24 Aug 27 08:05:13 AM UTC 24 3015217144 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.3784761531 Aug 27 08:04:31 AM UTC 24 Aug 27 08:05:44 AM UTC 24 4356354098 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.610965476 Aug 27 08:05:45 AM UTC 24 Aug 27 08:05:47 AM UTC 24 47944032 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.1110918425 Aug 27 07:58:44 AM UTC 24 Aug 27 08:05:50 AM UTC 24 68287492482 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.192484308 Aug 27 08:03:18 AM UTC 24 Aug 27 08:05:55 AM UTC 24 1710429512 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.409351548 Aug 27 08:02:04 AM UTC 24 Aug 27 08:05:56 AM UTC 24 10856591794 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.1315676405 Aug 27 08:05:48 AM UTC 24 Aug 27 08:05:57 AM UTC 24 1332823057 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.3775416829 Aug 27 08:05:51 AM UTC 24 Aug 27 08:05:57 AM UTC 24 257922153 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3933588351 Aug 27 08:04:19 AM UTC 24 Aug 27 08:05:59 AM UTC 24 6193292874 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.1733599664 Aug 27 08:05:58 AM UTC 24 Aug 27 08:06:00 AM UTC 24 11454921 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.4228042882 Aug 27 07:58:44 AM UTC 24 Aug 27 08:06:02 AM UTC 24 3874813676 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.3860835979 Aug 27 08:04:25 AM UTC 24 Aug 27 08:06:04 AM UTC 24 2499764220 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.685491928 Aug 27 08:05:56 AM UTC 24 Aug 27 08:06:09 AM UTC 24 550682449 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access.433800634 Aug 27 08:06:04 AM UTC 24 Aug 27 08:06:13 AM UTC 24 162484402 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_smoke.1070527578 Aug 27 08:05:58 AM UTC 24 Aug 27 08:06:13 AM UTC 24 180043451 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.1162211963 Aug 27 08:06:14 AM UTC 24 Aug 27 08:06:16 AM UTC 24 38866812 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.2104771641 Aug 27 08:04:52 AM UTC 24 Aug 27 08:06:17 AM UTC 24 593998308 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.929834183 Aug 27 08:06:14 AM UTC 24 Aug 27 08:06:21 AM UTC 24 231280940 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.3369675735 Aug 27 08:06:18 AM UTC 24 Aug 27 08:06:33 AM UTC 24 1888756066 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.4148775715 Aug 27 07:58:43 AM UTC 24 Aug 27 08:06:45 AM UTC 24 2555994652 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_bijection.1124988364 Aug 27 08:06:01 AM UTC 24 Aug 27 08:06:47 AM UTC 24 6070337149 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.1777971169 Aug 27 08:06:46 AM UTC 24 Aug 27 08:06:48 AM UTC 24 64715511 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.702267160 Aug 27 08:06:49 AM UTC 24 Aug 27 08:06:55 AM UTC 24 146681202 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.2466607745 Aug 27 08:06:48 AM UTC 24 Aug 27 08:06:56 AM UTC 24 98854028 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_regwen.583188078 Aug 27 07:59:56 AM UTC 24 Aug 27 08:07:19 AM UTC 24 8906499019 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_alert_test.2767842572 Aug 27 08:07:20 AM UTC 24 Aug 27 08:07:21 AM UTC 24 46661809 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.2521366985 Aug 27 07:59:36 AM UTC 24 Aug 27 08:07:27 AM UTC 24 6013425686 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.690620945 Aug 27 08:01:11 AM UTC 24 Aug 27 08:07:36 AM UTC 24 3476803792 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_smoke.4207703195 Aug 27 08:07:23 AM UTC 24 Aug 27 08:07:49 AM UTC 24 444860779 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.2366763999 Aug 27 08:01:35 AM UTC 24 Aug 27 08:08:02 AM UTC 24 51344109634 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1449789845 Aug 27 08:06:55 AM UTC 24 Aug 27 08:08:06 AM UTC 24 19365218552 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_bijection.1705227990 Aug 27 08:07:37 AM UTC 24 Aug 27 08:08:40 AM UTC 24 7446566681 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.3279006793 Aug 27 08:00:23 AM UTC 24 Aug 27 08:08:42 AM UTC 24 81353586074 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access.2323810610 Aug 27 08:08:03 AM UTC 24 Aug 27 08:08:44 AM UTC 24 263861978 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.2301367331 Aug 27 08:08:45 AM UTC 24 Aug 27 08:08:57 AM UTC 24 715372279 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.3670946477 Aug 27 08:08:42 AM UTC 24 Aug 27 08:09:07 AM UTC 24 93520990 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.2861913367 Aug 27 08:08:41 AM UTC 24 Aug 27 08:09:16 AM UTC 24 1242101603 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all.1088599229 Aug 27 07:58:43 AM UTC 24 Aug 27 08:09:17 AM UTC 24 15090435856 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.786514980 Aug 27 08:09:17 AM UTC 24 Aug 27 08:09:20 AM UTC 24 48289929 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.1591271155 Aug 27 07:59:39 AM UTC 24 Aug 27 08:09:25 AM UTC 24 4299652486 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.1691453085 Aug 27 08:09:21 AM UTC 24 Aug 27 08:09:26 AM UTC 24 340802506 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.841678306 Aug 27 08:02:07 AM UTC 24 Aug 27 08:09:29 AM UTC 24 6633080126 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_alert_test.4143605917 Aug 27 08:09:30 AM UTC 24 Aug 27 08:09:32 AM UTC 24 167086271 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.1937383082 Aug 27 08:09:18 AM UTC 24 Aug 27 08:09:35 AM UTC 24 2715229646 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.4093094574 Aug 27 07:58:44 AM UTC 24 Aug 27 08:09:39 AM UTC 24 34889681425 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_smoke.3219642244 Aug 27 08:09:33 AM UTC 24 Aug 27 08:09:52 AM UTC 24 1141028096 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.4044941713 Aug 27 08:04:35 AM UTC 24 Aug 27 08:10:39 AM UTC 24 3079552292 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_regwen.1005632474 Aug 27 07:58:44 AM UTC 24 Aug 27 08:10:40 AM UTC 24 22255656218 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.2317318867 Aug 27 08:00:15 AM UTC 24 Aug 27 08:10:44 AM UTC 24 1905258726 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_bijection.1759758258 Aug 27 08:09:40 AM UTC 24 Aug 27 08:10:49 AM UTC 24 9250380105 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.2527714936 Aug 27 08:10:45 AM UTC 24 Aug 27 08:10:54 AM UTC 24 124885553 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.2220143598 Aug 27 08:10:51 AM UTC 24 Aug 27 08:11:03 AM UTC 24 10245407603 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access.3380483542 Aug 27 08:10:41 AM UTC 24 Aug 27 08:11:07 AM UTC 24 1033374945 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.4145443814 Aug 27 08:10:50 AM UTC 24 Aug 27 08:11:09 AM UTC 24 83489341 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.2103520265 Aug 27 08:11:10 AM UTC 24 Aug 27 08:11:12 AM UTC 24 48590118 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.952533629 Aug 27 08:06:02 AM UTC 24 Aug 27 08:11:17 AM UTC 24 13283196692 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.1764598259 Aug 27 08:11:18 AM UTC 24 Aug 27 08:11:24 AM UTC 24 379446551 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.144930862 Aug 27 08:11:13 AM UTC 24 Aug 27 08:11:29 AM UTC 24 3112960694 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_alert_test.2186667942 Aug 27 08:11:30 AM UTC 24 Aug 27 08:11:32 AM UTC 24 19204921 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_smoke.4009706027 Aug 27 08:11:33 AM UTC 24 Aug 27 08:11:36 AM UTC 24 108593138 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.177624220 Aug 27 08:11:22 AM UTC 24 Aug 27 08:11:47 AM UTC 24 6762766454 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.3855705075 Aug 27 08:06:09 AM UTC 24 Aug 27 08:11:55 AM UTC 24 24318536590 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.3530219961 Aug 27 08:07:50 AM UTC 24 Aug 27 08:12:01 AM UTC 24 3695925483 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.4057224850 Aug 27 07:59:52 AM UTC 24 Aug 27 08:12:05 AM UTC 24 53378240068 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.403937033 Aug 27 08:04:39 AM UTC 24 Aug 27 08:12:07 AM UTC 24 25984247660 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.766230190 Aug 27 08:08:07 AM UTC 24 Aug 27 08:12:08 AM UTC 24 2649473757 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.3989035549 Aug 27 08:03:59 AM UTC 24 Aug 27 08:12:16 AM UTC 24 1884718996 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_regwen.3482854305 Aug 27 07:59:33 AM UTC 24 Aug 27 08:12:16 AM UTC 24 44971719339 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_bijection.2662127239 Aug 27 08:11:47 AM UTC 24 Aug 27 08:12:25 AM UTC 24 6841904453 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.611702485 Aug 27 07:59:47 AM UTC 24 Aug 27 08:12:27 AM UTC 24 65873562311 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.4211301935 Aug 27 08:12:17 AM UTC 24 Aug 27 08:12:29 AM UTC 24 2050310428 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.2184698735 Aug 27 08:12:29 AM UTC 24 Aug 27 08:12:32 AM UTC 24 74036039 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.3877205847 Aug 27 07:58:43 AM UTC 24 Aug 27 08:12:34 AM UTC 24 9169937197 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.422131388 Aug 27 08:03:30 AM UTC 24 Aug 27 08:12:36 AM UTC 24 17811132019 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.2904547222 Aug 27 08:12:34 AM UTC 24 Aug 27 08:12:40 AM UTC 24 598596339 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.2098106488 Aug 27 08:12:10 AM UTC 24 Aug 27 08:12:41 AM UTC 24 228011104 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_alert_test.685212523 Aug 27 08:12:42 AM UTC 24 Aug 27 08:12:44 AM UTC 24 23263560 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.2098201754 Aug 27 08:12:32 AM UTC 24 Aug 27 08:12:45 AM UTC 24 1781096938 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.29397420 Aug 27 08:12:09 AM UTC 24 Aug 27 08:13:04 AM UTC 24 286094793 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.3618301244 Aug 27 07:59:33 AM UTC 24 Aug 27 08:13:08 AM UTC 24 16040447944 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.1929908505 Aug 27 07:59:32 AM UTC 24 Aug 27 08:13:14 AM UTC 24 3350501677 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_regwen.2516170539 Aug 27 07:59:39 AM UTC 24 Aug 27 08:13:20 AM UTC 24 13273026080 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access.3868123859 Aug 27 08:12:01 AM UTC 24 Aug 27 08:13:22 AM UTC 24 2122386972 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.1838620229 Aug 27 08:13:23 AM UTC 24 Aug 27 08:13:26 AM UTC 24 147621341 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_executable.1308473109 Aug 27 07:58:44 AM UTC 24 Aug 27 08:13:33 AM UTC 24 4857041215 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_bijection.1319685500 Aug 27 08:13:05 AM UTC 24 Aug 27 08:13:44 AM UTC 24 2095354603 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.936360568 Aug 27 08:13:27 AM UTC 24 Aug 27 08:13:44 AM UTC 24 282333503 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.3600187192 Aug 27 08:13:35 AM UTC 24 Aug 27 08:13:48 AM UTC 24 1007306980 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_smoke.3851146329 Aug 27 08:12:45 AM UTC 24 Aug 27 08:14:04 AM UTC 24 237926623 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.732233700 Aug 27 08:14:05 AM UTC 24 Aug 27 08:14:08 AM UTC 24 78602658 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.683881258 Aug 27 08:14:08 AM UTC 24 Aug 27 08:14:23 AM UTC 24 2629609768 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.3718762268 Aug 27 08:14:24 AM UTC 24 Aug 27 08:14:29 AM UTC 24 92341278 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.2094927274 Aug 27 08:04:06 AM UTC 24 Aug 27 08:14:40 AM UTC 24 141344308701 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.1386174278 Aug 27 08:04:57 AM UTC 24 Aug 27 08:14:51 AM UTC 24 3219690748 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_alert_test.4126084662 Aug 27 08:14:52 AM UTC 24 Aug 27 08:14:54 AM UTC 24 14382469 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access.1290314684 Aug 27 08:13:15 AM UTC 24 Aug 27 08:14:58 AM UTC 24 3092597744 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.869604952 Aug 27 07:59:33 AM UTC 24 Aug 27 08:15:05 AM UTC 24 3856509780 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.624792641 Aug 27 07:58:43 AM UTC 24 Aug 27 08:15:08 AM UTC 24 3799818014 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2890351809 Aug 27 08:09:26 AM UTC 24 Aug 27 08:15:13 AM UTC 24 3493282312 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.3560189669 Aug 27 08:11:55 AM UTC 24 Aug 27 08:15:19 AM UTC 24 9847323257 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.3466436850 Aug 27 08:07:29 AM UTC 24 Aug 27 08:15:23 AM UTC 24 25902265627 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_smoke.539072243 Aug 27 08:14:55 AM UTC 24 Aug 27 08:15:34 AM UTC 24 203957906 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_bijection.1908101320 Aug 27 08:15:06 AM UTC 24 Aug 27 08:15:36 AM UTC 24 1044045554 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.2528231010 Aug 27 08:09:53 AM UTC 24 Aug 27 08:15:36 AM UTC 24 10815592686 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.2579832291 Aug 27 08:05:09 AM UTC 24 Aug 27 08:15:45 AM UTC 24 19526705610 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access.402998626 Aug 27 08:15:14 AM UTC 24 Aug 27 08:15:45 AM UTC 24 449732211 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.384481325 Aug 27 08:15:37 AM UTC 24 Aug 27 08:15:48 AM UTC 24 1561927148 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.1135212008 Aug 27 08:15:49 AM UTC 24 Aug 27 08:15:51 AM UTC 24 32573108 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.544780777 Aug 27 08:15:52 AM UTC 24 Aug 27 08:16:00 AM UTC 24 74450994 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_smoke.67686866 Aug 27 08:16:17 AM UTC 24 Aug 27 08:16:46 AM UTC 24 421706525 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_executable.3393587019 Aug 27 07:58:43 AM UTC 24 Aug 27 08:16:00 AM UTC 24 21476962728 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.1716583999 Aug 27 08:16:00 AM UTC 24 Aug 27 08:16:09 AM UTC 24 199663823 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.2719580482 Aug 27 08:00:42 AM UTC 24 Aug 27 08:16:13 AM UTC 24 3176824374 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_alert_test.725826765 Aug 27 08:16:14 AM UTC 24 Aug 27 08:16:15 AM UTC 24 31627843 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.1593219348 Aug 27 08:15:23 AM UTC 24 Aug 27 08:16:18 AM UTC 24 116264558 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3370328444 Aug 27 08:16:01 AM UTC 24 Aug 27 08:16:26 AM UTC 24 488351632 ps
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T292 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.156789277 Aug 27 08:09:35 AM UTC 24 Aug 27 08:16:34 AM UTC 24 44122974005 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.2162796680 Aug 27 08:06:00 AM UTC 24 Aug 27 08:16:43 AM UTC 24 42367335653 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.2555590382 Aug 27 08:15:35 AM UTC 24 Aug 27 08:16:56 AM UTC 24 513225311 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.3922056135 Aug 27 07:59:33 AM UTC 24 Aug 27 08:17:04 AM UTC 24 20209359673 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.729534220 Aug 27 08:16:58 AM UTC 24 Aug 27 08:17:09 AM UTC 24 1052340436 ps
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T304 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_alert_test.4198806836 Aug 27 08:17:26 AM UTC 24 Aug 27 08:17:28 AM UTC 24 28500716 ps
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