Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	151368680	1			T3	3298		T4	960		T5	1982
instr_valid_dis	118820039	1			T3	3298		T4	960		T5	1982
instr_en	24102636	1			T25	14564		T26	362		T16	5688

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11153103	1			T26	362		T16	81924		T53	52860
sram_ifetch_valid_disable	116410781	1			T3	3298		T4	960		T5	1982
sram_ifetch_enable	23804796	1			T25	14564		T16	69712		T53	59392

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	151368680	1			T3	3298		T4	960		T5	1982
hw_debug_en_valid_off	118783218	1			T3	3298		T4	960		T5	1982
hw_debug_en_on	21525190	1			T16	61626		T53	49960		T143	35338

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	116410781	1			T3	3298		T4	960		T5	1982
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	104330635	1			T3	3298		T4	960		T5	1982
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8765381	1			T145	58		T148	3556		T149	996
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5284761	1			T53	46734		T143	12786		T145	29402
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2328398	1			T53	46734		T143	12786		T145	29402
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2137253	1			T149	45560		T146	1732		T18	61738
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3931330	1			T16	23806		T53	6126		T145	12114
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1721144	1			T53	6126		T149	51454		T146	1482
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1553094	1			T145	12114		T148	22164		T39	260
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8264656	1			T53	42142		T143	35338		T145	21968
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3787524	1			T53	42142		T143	35338		T145	21910
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3212458	1			T145	58		T149	996		T18	73174

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10645292	1			T25	14564		T16	5688		T143	58
lc_exec_en	9329204	1			T16	37820		T53	1692		T145	29356
valid_exec_dis	113238599	1			T3	3298		T4	960		T5	1982
invalid_exec_dis	34957899	1			T25	14564		T26	362		T16	151636