Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44


Total tests in report: 1024
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
71.03 71.03 91.95 91.95 69.91 69.91 85.92 85.92 33.33 33.33 82.13 82.13 93.36 93.36 40.59 40.59 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.173358449
86.01 14.98 96.78 4.83 82.82 12.91 88.49 2.57 71.43 38.10 90.10 7.97 95.28 1.92 77.15 36.56 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.9334645
91.21 5.21 98.22 1.44 83.29 0.47 88.63 0.14 100.00 28.57 93.00 2.90 95.28 0.00 80.07 2.93 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3885208900
93.99 2.78 98.56 0.34 88.74 5.45 98.68 10.06 100.00 0.00 94.93 1.93 96.02 0.74 80.99 0.91 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.3396799600
94.95 0.96 99.07 0.51 89.81 1.07 98.68 0.00 100.00 0.00 96.14 1.21 97.05 1.03 83.91 2.93 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.3499099591
95.76 0.81 99.07 0.00 90.17 0.36 98.68 0.00 100.00 0.00 96.14 0.00 97.05 0.00 89.21 5.30 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1551200646
96.14 0.38 99.07 0.00 90.28 0.12 98.68 0.00 100.00 0.00 96.14 0.00 97.05 0.00 91.77 2.56 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_regwen.1712864658
96.42 0.28 99.07 0.00 90.52 0.24 98.75 0.07 100.00 0.00 96.14 0.00 98.67 1.62 91.77 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.981137547
96.68 0.26 99.07 0.00 90.52 0.00 98.75 0.00 100.00 0.00 96.14 0.00 98.67 0.00 93.60 1.83 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.1797344936
96.85 0.17 99.07 0.00 90.52 0.00 98.82 0.07 100.00 0.00 96.14 0.00 98.67 0.00 94.70 1.10 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_smoke.2757953283
97.00 0.16 99.07 0.00 90.52 0.00 98.82 0.00 100.00 0.00 96.14 0.00 98.67 0.00 95.80 1.10 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_executable.3468726904
97.13 0.13 99.15 0.08 90.52 0.00 99.65 0.83 100.00 0.00 96.14 0.00 98.67 0.00 95.80 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.1244238041
97.24 0.10 99.15 0.00 90.52 0.00 99.65 0.00 100.00 0.00 96.14 0.00 98.67 0.00 96.53 0.73 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3949188396
97.31 0.07 99.15 0.00 90.64 0.12 99.65 0.00 100.00 0.00 96.14 0.00 98.67 0.00 96.89 0.37 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.924864361
97.37 0.06 99.15 0.00 91.00 0.36 99.72 0.07 100.00 0.00 96.14 0.00 98.67 0.00 96.89 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.3805743945
97.41 0.04 99.15 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.14 0.00 98.97 0.29 96.89 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.3417973164
97.44 0.03 99.15 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.14 0.00 98.97 0.00 97.07 0.18 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1001086500
97.46 0.03 99.15 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.14 0.00 98.97 0.00 97.26 0.18 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2809003545
97.49 0.03 99.15 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.14 0.00 98.97 0.00 97.44 0.18 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.2171679023
97.51 0.02 99.15 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.14 0.00 99.12 0.15 97.44 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2263606705

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3490695011
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.456277889
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3636886505
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.600808978
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1278893628
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3444901988
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2135394234
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1904578842
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1121950217
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2000397622
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.9484846
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.758271419
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.664307258
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1503161254
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.291470876
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.199332844
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3585411588
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1350604458
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1235671975
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3519907080
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.4275938962
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1234701893
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.815641564
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3498523961
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1824589841
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1082778493
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.768410384
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.468362478
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.786511059
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3416339880
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1087068602
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.109332642
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.373974195
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3189261245
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1805665163
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1266788426
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1337303031
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.622238926
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1483002658
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2098575504
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2693002364
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1351913801
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3204736757
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3690313979
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1799818954
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3457170846
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2535847401
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2868094929
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1278040760
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3444799699
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2195700630
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.4204215467
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1339269513
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2467027446
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1400883911
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2327824884
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.901983042
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3116989397
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3964743093
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2723546720
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.283428651
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3533219102
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1956410284
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1033711452
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.4023553768
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4225632215
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.822861231
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.4098693201
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3892152132
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.291024794
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4101526805
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3910922513
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2009481291
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2602716189
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1385812590
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3221715669
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1534382647
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.222377779
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.894113114
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.4213638216
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2944300043
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2781747119
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1081828921
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2412143173
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.867182059
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.40771336
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1764064199
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3781247882
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.852789177
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1378249204
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.617768184
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/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2090680718
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.3489941748
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.1215720153
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.3469417460
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.709936706
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.1324409015
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.4018297050
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.2633444966
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.2347829602
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.3787218040
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.2037817328
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.1034682048
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.2050482719
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.1806255365
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.278485207
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.4062918486
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.2408563392
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.3982682648
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2257302493
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.2131924598
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.1996520169
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.4128685137
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.3921411917
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.731438292
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.4171841365
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.2232542379
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.2630093633
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.3624960034
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3272437630
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.2697301033
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.794671177
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.3523653089
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.2691598705
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.1230566610
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.2563301869
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all.2281371684
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1680677463
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.1838192554
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.1547487317
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.191899833
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.429550337
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.3465511433
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.1724281453
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.4269531373
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.3052204257
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.3812799246
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.1199293682
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.1765561506
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.4051437458
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.1015899432
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3257625993
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.1399753460
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.2199388379
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.2851475734
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.188351935
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.230904203



Total test records in report: 1024
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.1244238041 Aug 28 10:56:27 PM UTC 24 Aug 28 10:56:29 PM UTC 24 26717933 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.3805743945 Aug 28 10:56:29 PM UTC 24 Aug 28 10:56:31 PM UTC 24 121717645 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access.93488286 Aug 28 10:56:25 PM UTC 24 Aug 28 10:56:31 PM UTC 24 422778853 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.3396799600 Aug 28 10:56:29 PM UTC 24 Aug 28 10:56:33 PM UTC 24 145086703 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.2192356273 Aug 28 10:56:28 PM UTC 24 Aug 28 10:56:34 PM UTC 24 172411931 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.1575442699 Aug 28 10:56:35 PM UTC 24 Aug 28 10:56:37 PM UTC 24 282138345 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.1721890358 Aug 28 10:56:27 PM UTC 24 Aug 28 10:56:38 PM UTC 24 713360842 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.173358449 Aug 28 10:56:26 PM UTC 24 Aug 28 10:56:40 PM UTC 24 11027931689 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.3576653437 Aug 28 10:56:35 PM UTC 24 Aug 28 10:56:42 PM UTC 24 114577633 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_alert_test.1019830709 Aug 28 10:56:41 PM UTC 24 Aug 28 10:56:43 PM UTC 24 32711348 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.216528934 Aug 28 10:56:38 PM UTC 24 Aug 28 10:56:43 PM UTC 24 112025219 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.577820928 Aug 28 10:56:33 PM UTC 24 Aug 28 10:56:43 PM UTC 24 467297454 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.3404126719 Aug 28 10:56:40 PM UTC 24 Aug 28 10:56:43 PM UTC 24 427784495 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_smoke.87030084 Aug 28 10:56:30 PM UTC 24 Aug 28 10:56:44 PM UTC 24 601505941 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access.4264633968 Aug 28 10:56:44 PM UTC 24 Aug 28 10:56:48 PM UTC 24 76841167 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_smoke.2757953283 Aug 28 10:56:41 PM UTC 24 Aug 28 10:56:48 PM UTC 24 302099773 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.2770451898 Aug 28 10:56:45 PM UTC 24 Aug 28 10:56:50 PM UTC 24 405367243 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.2704008539 Aug 28 10:56:50 PM UTC 24 Aug 28 10:56:52 PM UTC 24 41018459 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_smoke.1755531768 Aug 28 10:56:23 PM UTC 24 Aug 28 10:56:57 PM UTC 24 474960730 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.3499099591 Aug 28 10:56:52 PM UTC 24 Aug 28 10:56:58 PM UTC 24 98520067 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_alert_test.1386168802 Aug 28 10:56:58 PM UTC 24 Aug 28 10:57:00 PM UTC 24 31152901 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.1309608647 Aug 28 10:56:33 PM UTC 24 Aug 28 10:57:04 PM UTC 24 211556921 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.169379936 Aug 28 10:56:57 PM UTC 24 Aug 28 10:57:04 PM UTC 24 328821868 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.3639461165 Aug 28 10:56:51 PM UTC 24 Aug 28 10:57:05 PM UTC 24 2902106095 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access.1850980035 Aug 28 10:56:31 PM UTC 24 Aug 28 10:57:07 PM UTC 24 1236149634 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.924864361 Aug 28 10:57:08 PM UTC 24 Aug 28 10:57:15 PM UTC 24 557505782 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_smoke.3569449765 Aug 28 10:57:02 PM UTC 24 Aug 28 10:57:17 PM UTC 24 3377768355 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_bijection.59492714 Aug 28 10:56:31 PM UTC 24 Aug 28 10:57:18 PM UTC 24 8104977259 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access.3213653070 Aug 28 10:57:05 PM UTC 24 Aug 28 10:57:19 PM UTC 24 690545219 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_bijection.49416919 Aug 28 10:56:43 PM UTC 24 Aug 28 10:57:19 PM UTC 24 2128774545 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.2861653485 Aug 28 10:57:18 PM UTC 24 Aug 28 10:57:20 PM UTC 24 75807739 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.67845571 Aug 28 10:57:20 PM UTC 24 Aug 28 10:57:25 PM UTC 24 385225491 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.2507449482 Aug 28 10:57:19 PM UTC 24 Aug 28 10:57:27 PM UTC 24 381919717 ps
T174 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_alert_test.761589976 Aug 28 10:57:26 PM UTC 24 Aug 28 10:57:28 PM UTC 24 45377468 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_smoke.553028147 Aug 28 10:57:27 PM UTC 24 Aug 28 10:57:30 PM UTC 24 53870270 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.278485207 Aug 28 11:00:55 PM UTC 24 Aug 28 11:00:58 PM UTC 24 75860464 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.2189081159 Aug 28 10:57:26 PM UTC 24 Aug 28 10:57:31 PM UTC 24 977287074 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.4245373672 Aug 28 10:56:45 PM UTC 24 Aug 28 10:57:35 PM UTC 24 391887022 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.3822376968 Aug 28 10:56:26 PM UTC 24 Aug 28 10:57:36 PM UTC 24 304990057 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_bijection.4138250630 Aug 28 10:57:02 PM UTC 24 Aug 28 10:57:38 PM UTC 24 5259358827 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.853663058 Aug 28 10:56:31 PM UTC 24 Aug 28 10:57:39 PM UTC 24 122035481 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.1837911673 Aug 28 10:57:36 PM UTC 24 Aug 28 10:57:42 PM UTC 24 107258433 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.1050543258 Aug 28 10:57:37 PM UTC 24 Aug 28 10:57:44 PM UTC 24 246962500 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.2458789748 Aug 28 10:56:44 PM UTC 24 Aug 28 10:57:45 PM UTC 24 123958318 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.3261622133 Aug 28 10:57:45 PM UTC 24 Aug 28 10:57:47 PM UTC 24 83383489 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_bijection.445647220 Aug 28 10:56:24 PM UTC 24 Aug 28 10:57:51 PM UTC 24 2096796549 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.3733430202 Aug 28 10:57:06 PM UTC 24 Aug 28 10:57:51 PM UTC 24 113264696 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.3036014340 Aug 28 10:57:48 PM UTC 24 Aug 28 10:57:53 PM UTC 24 47925595 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.3365657725 Aug 28 10:57:34 PM UTC 24 Aug 28 10:57:54 PM UTC 24 71044455 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.1880863675 Aug 28 10:57:53 PM UTC 24 Aug 28 10:57:56 PM UTC 24 100785632 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_alert_test.1542809330 Aug 28 10:57:55 PM UTC 24 Aug 28 10:57:57 PM UTC 24 66488995 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.2171679023 Aug 28 10:56:25 PM UTC 24 Aug 28 10:58:00 PM UTC 24 531880128 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.4093074133 Aug 28 10:57:46 PM UTC 24 Aug 28 10:58:04 PM UTC 24 893206062 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.3810588705 Aug 28 10:58:05 PM UTC 24 Aug 28 10:58:08 PM UTC 24 308136351 ps
T173 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_smoke.491019110 Aug 28 10:57:57 PM UTC 24 Aug 28 10:58:12 PM UTC 24 194713827 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access.1363686411 Aug 28 10:58:01 PM UTC 24 Aug 28 10:58:19 PM UTC 24 4853833706 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.2200393889 Aug 28 10:58:12 PM UTC 24 Aug 28 10:58:20 PM UTC 24 332630326 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.875313434 Aug 28 10:58:28 PM UTC 24 Aug 28 10:58:31 PM UTC 24 48929651 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_bijection.781958739 Aug 28 10:57:29 PM UTC 24 Aug 28 10:58:32 PM UTC 24 2269909324 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.3661272334 Aug 28 10:57:07 PM UTC 24 Aug 28 10:58:32 PM UTC 24 606276307 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.1948897491 Aug 28 10:58:33 PM UTC 24 Aug 28 10:58:38 PM UTC 24 107649000 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.489333200 Aug 28 10:58:34 PM UTC 24 Aug 28 10:58:45 PM UTC 24 718169216 ps
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T66 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_alert_test.391110263 Aug 28 10:58:46 PM UTC 24 Aug 28 10:58:48 PM UTC 24 14298195 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access.3609662554 Aug 28 10:57:32 PM UTC 24 Aug 28 10:59:03 PM UTC 24 2347082251 ps
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T69 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.4025725217 Aug 28 10:59:06 PM UTC 24 Aug 28 10:59:17 PM UTC 24 215417738 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.1215720153 Aug 28 10:59:17 PM UTC 24 Aug 28 10:59:21 PM UTC 24 155568226 ps
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T72 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access.2399306122 Aug 28 10:59:04 PM UTC 24 Aug 28 10:59:29 PM UTC 24 1351562429 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.4193439192 Aug 28 10:59:18 PM UTC 24 Aug 28 10:59:31 PM UTC 24 478868794 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.9334645 Aug 28 10:57:20 PM UTC 24 Aug 28 10:59:31 PM UTC 24 490584518 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.2057346243 Aug 28 10:59:29 PM UTC 24 Aug 28 10:59:32 PM UTC 24 42529042 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.2301257569 Aug 28 10:59:33 PM UTC 24 Aug 28 10:59:38 PM UTC 24 58154012 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_bijection.311361841 Aug 28 10:58:57 PM UTC 24 Aug 28 10:59:40 PM UTC 24 5576713690 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_alert_test.2526099883 Aug 28 10:59:40 PM UTC 24 Aug 28 10:59:42 PM UTC 24 64046879 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.1043257910 Aug 28 10:59:31 PM UTC 24 Aug 28 10:59:47 PM UTC 24 601195633 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.2408563392 Aug 28 10:59:41 PM UTC 24 Aug 28 10:59:49 PM UTC 24 765575136 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.2633444966 Aug 28 11:00:22 PM UTC 24 Aug 28 11:00:33 PM UTC 24 1003556970 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.1556120943 Aug 28 10:58:09 PM UTC 24 Aug 28 10:59:50 PM UTC 24 154238116 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.1979757354 Aug 28 10:56:43 PM UTC 24 Aug 28 11:00:13 PM UTC 24 2063182010 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2090680718 Aug 28 10:59:33 PM UTC 24 Aug 28 11:00:20 PM UTC 24 4248695168 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.1996520169 Aug 28 11:00:21 PM UTC 24 Aug 28 11:00:26 PM UTC 24 97840408 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.3867418311 Aug 28 10:56:31 PM UTC 24 Aug 28 11:00:54 PM UTC 24 10201667144 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.2037817328 Aug 28 11:00:58 PM UTC 24 Aug 28 11:01:12 PM UTC 24 726337095 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.2050482719 Aug 28 10:59:50 PM UTC 24 Aug 28 11:01:13 PM UTC 24 1125250757 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.3186061386 Aug 28 10:56:25 PM UTC 24 Aug 28 11:01:17 PM UTC 24 9260597726 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.1324409015 Aug 28 10:59:48 PM UTC 24 Aug 28 11:01:18 PM UTC 24 4605640187 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.709936706 Aug 28 11:01:19 PM UTC 24 Aug 28 11:01:20 PM UTC 24 57987057 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.3787218040 Aug 28 11:01:13 PM UTC 24 Aug 28 11:01:21 PM UTC 24 792467957 ps
T124 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.2563301869 Aug 28 11:01:21 PM UTC 24 Aug 28 11:01:44 PM UTC 24 3740152643 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.1797344936 Aug 28 10:56:31 PM UTC 24 Aug 28 11:02:03 PM UTC 24 134918549847 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.2347829602 Aug 28 11:00:14 PM UTC 24 Aug 28 11:02:06 PM UTC 24 140109797 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.3489941748 Aug 28 10:58:58 PM UTC 24 Aug 28 11:02:12 PM UTC 24 6803185786 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.1547487317 Aug 28 11:02:13 PM UTC 24 Aug 28 11:02:27 PM UTC 24 124292452 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.1321381126 Aug 28 10:57:04 PM UTC 24 Aug 28 11:02:32 PM UTC 24 10174647520 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.3410511853 Aug 28 10:56:44 PM UTC 24 Aug 28 11:02:33 PM UTC 24 11894760824 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.2232542379 Aug 28 11:02:28 PM UTC 24 Aug 28 11:02:34 PM UTC 24 190236846 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.1180397879 Aug 28 10:58:02 PM UTC 24 Aug 28 11:02:36 PM UTC 24 7644952616 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.2691598705 Aug 28 11:02:37 PM UTC 24 Aug 28 11:02:39 PM UTC 24 32709890 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.1093004660 Aug 28 10:58:00 PM UTC 24 Aug 28 11:02:41 PM UTC 24 2625568901 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.2923212902 Aug 28 10:57:31 PM UTC 24 Aug 28 11:02:42 PM UTC 24 2881258817 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.465396132 Aug 28 10:56:25 PM UTC 24 Aug 28 11:02:43 PM UTC 24 46599025097 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.3624960034 Aug 28 11:02:41 PM UTC 24 Aug 28 11:02:49 PM UTC 24 213650453 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.3921411917 Aug 28 11:02:49 PM UTC 24 Aug 28 11:02:51 PM UTC 24 103561713 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3272437630 Aug 28 11:02:40 PM UTC 24 Aug 28 11:02:51 PM UTC 24 1915741228 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.794671177 Aug 28 11:01:48 PM UTC 24 Aug 28 11:03:04 PM UTC 24 631395685 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.346559286 Aug 28 10:57:29 PM UTC 24 Aug 28 11:03:08 PM UTC 24 1375039912 ps
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T176 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.731438292 Aug 28 11:01:30 PM UTC 24 Aug 28 11:03:25 PM UTC 24 27478504642 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.2131924598 Aug 28 10:59:50 PM UTC 24 Aug 28 11:03:31 PM UTC 24 7434907630 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.4051437458 Aug 28 11:03:15 PM UTC 24 Aug 28 11:03:43 PM UTC 24 1936406300 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.2630093633 Aug 28 11:02:07 PM UTC 24 Aug 28 11:03:53 PM UTC 24 266539809 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.3052204257 Aug 28 11:03:32 PM UTC 24 Aug 28 11:03:55 PM UTC 24 261861453 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.4269531373 Aug 28 11:03:54 PM UTC 24 Aug 28 11:04:02 PM UTC 24 341304680 ps
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T211 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.230904203 Aug 28 11:03:44 PM UTC 24 Aug 28 11:04:21 PM UTC 24 386283663 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3257625993 Aug 28 11:04:22 PM UTC 24 Aug 28 11:04:24 PM UTC 24 47506604 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.1806255365 Aug 28 11:00:08 PM UTC 24 Aug 28 11:04:29 PM UTC 24 18821035722 ps
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T214 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.1199293682 Aug 28 11:04:25 PM UTC 24 Aug 28 11:04:41 PM UTC 24 690058302 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.429550337 Aug 28 11:04:42 PM UTC 24 Aug 28 11:04:44 PM UTC 24 34106663 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_regwen.3515083824 Aug 28 10:57:43 PM UTC 24 Aug 28 11:04:47 PM UTC 24 5291703503 ps
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T219 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access.2118089104 Aug 28 11:06:16 PM UTC 24 Aug 28 11:06:22 PM UTC 24 480788955 ps
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T223 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.1169524379 Aug 28 11:07:18 PM UTC 24 Aug 28 11:07:20 PM UTC 24 33191071 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.3523653089 Aug 28 11:02:04 PM UTC 24 Aug 28 11:07:20 PM UTC 24 4012942608 ps
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T170 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_alert_test.3216457745 Aug 28 11:07:31 PM UTC 24 Aug 28 11:07:33 PM UTC 24 74311878 ps
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T233 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.3309011394 Aug 28 11:08:35 PM UTC 24 Aug 28 11:08:37 PM UTC 24 313910844 ps
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T234 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.1235262636 Aug 28 11:08:31 PM UTC 24 Aug 28 11:08:40 PM UTC 24 343468908 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_regwen.1712864658 Aug 28 10:56:34 PM UTC 24 Aug 28 11:08:41 PM UTC 24 29648368119 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_smoke.159135075 Aug 28 11:10:17 PM UTC 24 Aug 28 11:10:59 PM UTC 24 449468715 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.3484893372 Aug 28 11:08:40 PM UTC 24 Aug 28 11:08:45 PM UTC 24 108664482 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.931018750 Aug 28 11:08:38 PM UTC 24 Aug 28 11:08:48 PM UTC 24 954493382 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_alert_test.3559298496 Aug 28 11:08:46 PM UTC 24 Aug 28 11:08:48 PM UTC 24 82854498 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.2760099495 Aug 28 10:58:49 PM UTC 24 Aug 28 11:08:54 PM UTC 24 12452641998 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1680677463 Aug 28 11:02:43 PM UTC 24 Aug 28 11:09:03 PM UTC 24 2126105314 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_smoke.2116767381 Aug 28 11:08:48 PM UTC 24 Aug 28 11:09:03 PM UTC 24 486715020 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.4171841365 Aug 28 11:02:34 PM UTC 24 Aug 28 11:09:05 PM UTC 24 5196820119 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access.176992622 Aug 28 11:09:04 PM UTC 24 Aug 28 11:09:10 PM UTC 24 483534602 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.3826126320 Aug 28 11:09:06 PM UTC 24 Aug 28 11:09:11 PM UTC 24 46530082 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.3226757044 Aug 28 11:09:12 PM UTC 24 Aug 28 11:09:16 PM UTC 24 702723695 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.4160659002 Aug 28 11:08:29 PM UTC 24 Aug 28 11:09:18 PM UTC 24 151996159 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_bijection.2283148737 Aug 28 11:07:56 PM UTC 24 Aug 28 11:09:33 PM UTC 24 12193802944 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.2697301033 Aug 28 11:01:22 PM UTC 24 Aug 28 11:09:47 PM UTC 24 11062789397 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_bijection.1780465832 Aug 28 11:08:53 PM UTC 24 Aug 28 11:09:48 PM UTC 24 3157671418 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.141153971 Aug 28 11:09:48 PM UTC 24 Aug 28 11:09:50 PM UTC 24 31662404 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.2117750463 Aug 28 11:09:49 PM UTC 24 Aug 28 11:09:57 PM UTC 24 226580692 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.3588580842 Aug 28 11:09:51 PM UTC 24 Aug 28 11:10:00 PM UTC 24 1236362266 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.1411751377 Aug 28 11:09:11 PM UTC 24 Aug 28 11:10:14 PM UTC 24 243191895 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_alert_test.3227084706 Aug 28 11:10:14 PM UTC 24 Aug 28 11:10:16 PM UTC 24 28699421 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3885208900 Aug 28 11:07:27 PM UTC 24 Aug 28 11:10:19 PM UTC 24 5508185172 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_executable.3468726904 Aug 28 10:57:40 PM UTC 24 Aug 28 11:10:21 PM UTC 24 1728266575 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.1034682048 Aug 28 10:59:43 PM UTC 24 Aug 28 11:10:39 PM UTC 24 28863965012 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3097538690 Aug 28 11:09:58 PM UTC 24 Aug 28 11:10:59 PM UTC 24 1120330634 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.24372340 Aug 28 10:57:02 PM UTC 24 Aug 28 11:11:04 PM UTC 24 12237301037 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2257302493 Aug 28 11:01:14 PM UTC 24 Aug 28 11:11:05 PM UTC 24 10639200904 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.1399753460 Aug 28 11:04:11 PM UTC 24 Aug 28 11:11:07 PM UTC 24 7113368745 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.932457893 Aug 28 11:11:08 PM UTC 24 Aug 28 11:11:15 PM UTC 24 305653030 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_executable.463156967 Aug 28 10:56:33 PM UTC 24 Aug 28 11:11:29 PM UTC 24 30317513942 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.3936865988 Aug 28 11:11:05 PM UTC 24 Aug 28 11:11:35 PM UTC 24 99615371 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_executable.1161701618 Aug 28 10:59:22 PM UTC 24 Aug 28 11:11:42 PM UTC 24 16008355576 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access.2430925453 Aug 28 11:15:42 PM UTC 24 Aug 28 11:16:03 PM UTC 24 769254989 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.1942938054 Aug 28 11:11:42 PM UTC 24 Aug 28 11:11:44 PM UTC 24 29713590 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access.757130441 Aug 28 11:11:00 PM UTC 24 Aug 28 11:11:44 PM UTC 24 153771470 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.3261760613 Aug 28 11:11:45 PM UTC 24 Aug 28 11:11:54 PM UTC 24 472975373 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.36532165 Aug 28 11:11:45 PM UTC 24 Aug 28 11:12:00 PM UTC 24 913625358 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1261231494 Aug 28 11:11:45 PM UTC 24 Aug 28 11:12:00 PM UTC 24 3244544790 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_alert_test.4078281291 Aug 28 11:12:01 PM UTC 24 Aug 28 11:12:03 PM UTC 24 12716270 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_bijection.2573593220 Aug 28 11:10:23 PM UTC 24 Aug 28 11:12:04 PM UTC 24 32463661516 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.493801302 Aug 28 10:56:42 PM UTC 24 Aug 28 11:12:24 PM UTC 24 5633669614 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.1077333962 Aug 28 11:11:05 PM UTC 24 Aug 28 11:12:31 PM UTC 24 248717139 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.501425417 Aug 28 10:57:38 PM UTC 24 Aug 28 11:12:37 PM UTC 24 10507810977 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.1765561506 Aug 28 11:02:53 PM UTC 24 Aug 28 11:12:50 PM UTC 24 13173917861 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access.198321433 Aug 28 11:12:32 PM UTC 24 Aug 28 11:12:53 PM UTC 24 284580129 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.156607021 Aug 28 11:12:54 PM UTC 24 Aug 28 11:12:57 PM UTC 24 254354078 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.1731146775 Aug 28 11:08:01 PM UTC 24 Aug 28 11:13:25 PM UTC 24 2977022738 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.2836733217 Aug 28 11:12:37 PM UTC 24 Aug 28 11:13:30 PM UTC 24 514969688 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_bijection.1055235812 Aug 28 11:12:05 PM UTC 24 Aug 28 11:13:33 PM UTC 24 16256819307 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.1750601760 Aug 28 11:13:34 PM UTC 24 Aug 28 11:13:36 PM UTC 24 32093313 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.4128685137 Aug 28 11:02:33 PM UTC 24 Aug 28 11:13:40 PM UTC 24 12567682322 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.2119569701 Aug 28 11:13:37 PM UTC 24 Aug 28 11:13:45 PM UTC 24 625716710 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.1124144061 Aug 28 10:58:20 PM UTC 24 Aug 28 11:13:48 PM UTC 24 3896169283 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.353914211 Aug 28 11:10:19 PM UTC 24 Aug 28 11:13:49 PM UTC 24 52902545243 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.3702068543 Aug 28 11:13:40 PM UTC 24 Aug 28 11:13:49 PM UTC 24 1469641957 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.683168107 Aug 28 11:12:51 PM UTC 24 Aug 28 11:13:51 PM UTC 24 965595743 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_alert_test.159050108 Aug 28 11:13:50 PM UTC 24 Aug 28 11:13:52 PM UTC 24 28784336 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_smoke.2674904855 Aug 28 11:12:01 PM UTC 24 Aug 28 11:13:57 PM UTC 24 642238820 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_smoke.3305267709 Aug 28 11:13:51 PM UTC 24 Aug 28 11:13:57 PM UTC 24 236978781 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_bijection.2109992443 Aug 28 11:13:53 PM UTC 24 Aug 28 11:14:18 PM UTC 24 1272810798 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access.2619169343 Aug 28 11:13:58 PM UTC 24 Aug 28 11:14:23 PM UTC 24 271315354 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.1695612190 Aug 28 11:08:26 PM UTC 24 Aug 28 11:14:53 PM UTC 24 7718388901 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_regwen.1253998647 Aug 28 10:56:26 PM UTC 24 Aug 28 11:14:53 PM UTC 24 12912141060 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.531773779 Aug 28 11:09:04 PM UTC 24 Aug 28 11:14:58 PM UTC 24 11752803302 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.270563553 Aug 28 11:14:54 PM UTC 24 Aug 28 11:15:06 PM UTC 24 1239868615 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_executable.309427202 Aug 28 11:08:33 PM UTC 24 Aug 28 11:15:15 PM UTC 24 9507795805 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.1802441682 Aug 28 11:14:54 PM UTC 24 Aug 28 11:15:19 PM UTC 24 88695433 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3600854044 Aug 28 11:08:41 PM UTC 24 Aug 28 11:15:21 PM UTC 24 1356581446 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.1336860001 Aug 28 11:15:20 PM UTC 24 Aug 28 11:15:22 PM UTC 24 87725313 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.826007814 Aug 28 11:15:21 PM UTC 24 Aug 28 11:15:28 PM UTC 24 278742439 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_executable.2167482684 Aug 28 10:56:49 PM UTC 24 Aug 28 11:15:30 PM UTC 24 15922257219 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.1681661307 Aug 28 11:15:23 PM UTC 24 Aug 28 11:15:31 PM UTC 24 604327568 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_alert_test.1564615865 Aug 28 11:15:30 PM UTC 24 Aug 28 11:15:32 PM UTC 24 30604130 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.3546446303 Aug 28 11:08:55 PM UTC 24 Aug 28 11:15:35 PM UTC 24 3754803196 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.813621451 Aug 28 11:07:39 PM UTC 24 Aug 28 11:15:35 PM UTC 24 9803426983 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_smoke.375205249 Aug 28 11:15:32 PM UTC 24 Aug 28 11:15:41 PM UTC 24 500303673 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.1336057068 Aug 28 11:10:40 PM UTC 24 Aug 28 11:15:50 PM UTC 24 3288838624 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.2352598208 Aug 28 11:14:24 PM UTC 24 Aug 28 11:16:02 PM UTC 24 534990860 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.3514195731 Aug 28 11:16:03 PM UTC 24 Aug 28 11:16:16 PM UTC 24 63747168 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.1544348399 Aug 28 11:12:31 PM UTC 24 Aug 28 11:16:19 PM UTC 24 7350005010 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.1442019003 Aug 28 11:16:17 PM UTC 24 Aug 28 11:16:26 PM UTC 24 407714188 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.1230566610 Aug 28 11:02:35 PM UTC 24 Aug 28 11:16:32 PM UTC 24 56240269257 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3484069986 Aug 28 11:15:28 PM UTC 24 Aug 28 11:16:41 PM UTC 24 5258190029 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.3879811689 Aug 28 11:16:42 PM UTC 24 Aug 28 11:16:44 PM UTC 24 110657451 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.2907798472 Aug 28 11:16:04 PM UTC 24 Aug 28 11:16:52 PM UTC 24 117455837 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.2032164993 Aug 28 11:16:45 PM UTC 24 Aug 28 11:16:53 PM UTC 24 344101346 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_bijection.649541666 Aug 28 11:15:36 PM UTC 24 Aug 28 11:17:01 PM UTC 24 1085645256 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.3109452034 Aug 28 11:16:53 PM UTC 24 Aug 28 11:17:02 PM UTC 24 1523556063 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_alert_test.186874618 Aug 28 11:17:02 PM UTC 24 Aug 28 11:17:04 PM UTC 24 30700199 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.4018297050 Aug 28 11:00:34 PM UTC 24 Aug 28 11:17:17 PM UTC 24 19475452976 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_smoke.1787987855 Aug 28 11:17:04 PM UTC 24 Aug 28 11:17:19 PM UTC 24 192425027 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.4029948317 Aug 28 11:06:17 PM UTC 24 Aug 28 11:17:20 PM UTC 24 98827417491 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access.3985504676 Aug 28 11:17:21 PM UTC 24 Aug 28 11:17:33 PM UTC 24 181540672 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.3469417460 Aug 28 11:00:27 PM UTC 24 Aug 28 11:18:02 PM UTC 24 12669405514 ps
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T311 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.2436069471 Aug 28 11:18:14 PM UTC 24 Aug 28 11:18:25 PM UTC 24 254284971 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.2266807597 Aug 28 11:18:03 PM UTC 24 Aug 28 11:18:26 PM UTC 24 526496273 ps