Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	151587898	1			T2	1982		T3	6512		T4	4726
instr_valid_dis	120631433	1			T2	1982		T3	6512		T4	4726
instr_en	21121166	1			T23	5304		T39	116554		T151	92258

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	9596535	1			T23	5304		T21	47334		T17	72160
sram_ifetch_valid_disable	120977980	1			T2	1982		T3	6512		T4	4726
sram_ifetch_enable	21013383	1			T23	42698		T21	34234		T17	86410

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	151587898	1			T2	1982		T3	6512		T4	4726
hw_debug_en_valid_off	117843910	1			T2	1982		T3	6512		T4	4726
hw_debug_en_on	22459925	1			T23	7814		T21	37590		T17	150766

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	120977980	1			T2	1982		T3	6512		T4	4726
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	107807449	1			T2	1982		T3	6512		T4	4726
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8926082	1			T39	39912		T151	30454		T148	14808
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3982804	1			T39	30156		T148	20000		T150	36684
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1571158	1			T155	5082		T164	36664		T165	46910
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1561722	1			T150	36684		T154	3984		T155	8566
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3635407	1			T23	5304		T17	72160		T39	54386
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1391524	1			T17	72160		T154	40		T164	766
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1474973	1			T23	5304		T39	54386		T149	6726
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9755754	1			T21	3356		T17	49662		T39	90988
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4585946	1			T17	49662		T39	51076		T151	76240
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3478924	1			T39	39912		T151	15294		T148	14808

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8470121	1			T39	22256		T151	61804		T148	1686
lc_exec_en	9068764	1			T23	2510		T21	34234		T17	28944
valid_exec_dis	115354966	1			T2	1982		T3	6512		T4	4726
invalid_exec_dis	30609918	1			T23	48002		T21	81568		T17	158570