Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.93 99.16 94.27 99.72 100.00 95.95 99.12 97.26


Total tests in report: 1027
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
72.93 72.93 91.95 91.95 74.53 74.53 93.17 93.17 33.33 33.33 81.88 81.88 93.22 93.22 42.41 42.41 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.232677368
87.56 14.64 96.78 4.83 85.31 10.78 96.01 2.84 71.43 38.10 89.86 7.97 95.13 1.92 78.43 36.01 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1631327331
92.57 5.01 98.22 1.44 85.78 0.47 96.01 0.00 100.00 28.57 92.75 2.90 95.87 0.74 79.34 0.91 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3448148968
93.66 1.09 98.56 0.34 88.27 2.49 97.50 1.49 100.00 0.00 94.44 1.69 96.61 0.74 80.26 0.91 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.1701516269
94.49 0.83 98.81 0.25 89.45 1.18 98.68 1.18 100.00 0.00 95.65 1.21 97.49 0.88 81.35 1.10 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.3727551687
95.28 0.79 98.81 0.00 90.05 0.59 98.68 0.00 100.00 0.00 95.65 0.00 97.49 0.00 86.29 4.94 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2690082768
95.85 0.56 98.81 0.00 90.28 0.24 98.68 0.00 100.00 0.00 95.89 0.24 97.49 0.00 89.76 3.47 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_executable.1508961640
96.13 0.29 98.81 0.00 90.28 0.00 98.68 0.00 100.00 0.00 95.89 0.00 97.49 0.00 91.77 2.01 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.427628315
96.39 0.25 99.07 0.25 90.28 0.00 98.68 0.00 100.00 0.00 96.14 0.24 97.49 0.00 93.05 1.28 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.3693692633
96.60 0.21 99.07 0.00 90.28 0.00 98.68 0.00 100.00 0.00 96.14 0.00 97.49 0.00 94.52 1.46 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_executable.874484869
96.80 0.20 99.07 0.00 90.28 0.00 98.75 0.07 100.00 0.00 96.14 0.00 98.82 1.33 94.52 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1988677232
96.93 0.13 99.15 0.08 90.28 0.00 99.58 0.83 100.00 0.00 96.14 0.00 98.82 0.00 94.52 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.921862446
97.03 0.10 99.15 0.00 90.28 0.00 99.58 0.00 100.00 0.00 96.14 0.00 98.82 0.00 95.25 0.73 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_executable.874584218
97.12 0.09 99.15 0.00 90.64 0.36 99.65 0.07 100.00 0.00 96.14 0.00 98.82 0.00 95.43 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.3261655597
97.20 0.08 99.15 0.00 90.64 0.00 99.65 0.00 100.00 0.00 96.14 0.00 98.82 0.00 95.98 0.55 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3261738386
97.26 0.06 99.15 0.00 90.88 0.24 99.65 0.00 100.00 0.00 96.14 0.00 98.82 0.00 96.16 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all.3854167831
97.30 0.05 99.15 0.00 90.88 0.00 99.65 0.00 100.00 0.00 96.14 0.00 98.97 0.15 96.34 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access.3140213512
97.34 0.04 99.15 0.00 90.88 0.00 99.72 0.07 100.00 0.00 96.14 0.00 98.97 0.00 96.53 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.2794032108
97.37 0.03 99.15 0.00 90.88 0.00 99.72 0.00 100.00 0.00 96.14 0.00 98.97 0.00 96.71 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.4197373517
97.39 0.03 99.15 0.00 90.88 0.00 99.72 0.00 100.00 0.00 96.14 0.00 98.97 0.00 96.89 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.297439431
97.42 0.03 99.15 0.00 90.88 0.00 99.72 0.00 100.00 0.00 96.14 0.00 98.97 0.00 97.07 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.125093504
97.44 0.03 99.15 0.00 90.88 0.00 99.72 0.00 100.00 0.00 96.14 0.00 98.97 0.00 97.26 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2005153337
97.47 0.02 99.15 0.00 90.88 0.00 99.72 0.00 100.00 0.00 96.14 0.00 99.12 0.15 97.26 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.718153558
97.48 0.02 99.15 0.00 91.00 0.12 99.72 0.00 100.00 0.00 96.14 0.00 99.12 0.00 97.26 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_regwen.2140836129

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2332939532
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2007805605
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.310627567
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.674401016
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1297174811
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1708920909
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3287391630
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1645257386
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.736255890
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3858817368
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1444873784
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2557288339
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3376430225
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1896364497
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.966291220
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2719391563
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3774065118
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2634597805
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2286355607
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2418589126
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.511883239
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.478463563
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1216476186
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1470958329
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1112907335
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1648029540
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4253213896
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.446179853
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2311272988
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.4117547332
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.217502843
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2589366637
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2686027596
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1641115353
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4080721694
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3378315312
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3724458280
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2519896972
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3164106751
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2820058501
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3558674722
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3309487572
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.4182984595
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.960997023
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1703885267
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.94539583
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2350145374
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.271806845
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.179269027
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2067110911
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.99578235
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3173321380
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2995320701
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3463514737
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1193722560
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2769797585
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3694893924
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1683791959
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.956839727
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3685257619
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3994125117
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3182536475
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2226492954
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1597922618
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1056671395
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3209737395
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1777724813
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2116262198
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2902235830
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2885427200
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1714014838
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4220118455
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2854158846
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2777388868
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2052725053
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1562415759
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1951929982
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.4272186937
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3931472775
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2140619306
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2078067784
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3063022786
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3311195271
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3795048796
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/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_executable.179531141
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.1654202939
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.110863911
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.2492896217
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.898451940
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.4004783290
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access.177147100
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.4150937511
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.1917810854
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_regwen.590129208
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_smoke.4215255140
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2411539744
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.4254781215
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.1087847767
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.246917422
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.4102565388
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.3043035741
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.402422956
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.3071853060
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.3068081975
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.293737282
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.1098574876
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.80948108
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.1241147457
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.1398584228
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.79730607
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.1809551146
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.2851120689
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.223854811
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.2975015242
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.339585732
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.3113830672
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.3353324161
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.3268495077
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.726242838
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.1747661889
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.1755008697
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3845611364
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.3821157159
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.3855656720
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.3149688856
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.1447730347
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.1858209977
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.1899620673
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all.3271345323
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.285561671
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.2631226865
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.2476556850
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.4010779336
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.2929865421
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.2487647602
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.1675037652
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.292327938
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.2026168265
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.1993347180
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.541741559
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.36397410
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.1884931635
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.1294550198
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.2202648433
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.654379386
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.1072453971
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.2442734698
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.2778635388



Total test records in report: 1027
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.921862446 Sep 01 09:45:16 PM UTC 24 Sep 01 09:45:18 PM UTC 24 30267491 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.3727551687 Sep 01 09:45:16 PM UTC 24 Sep 01 09:45:21 PM UTC 24 89057772 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_smoke.3125335763 Sep 01 09:45:13 PM UTC 24 Sep 01 09:45:21 PM UTC 24 327580349 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.3261655597 Sep 01 09:45:23 PM UTC 24 Sep 01 09:45:25 PM UTC 24 39962420 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.232677368 Sep 01 09:45:15 PM UTC 24 Sep 01 09:45:25 PM UTC 24 2465142909 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.2827842902 Sep 01 09:45:22 PM UTC 24 Sep 01 09:45:27 PM UTC 24 467280258 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.2416608985 Sep 01 09:45:16 PM UTC 24 Sep 01 09:45:33 PM UTC 24 1773419813 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_bijection.2225649119 Sep 01 09:45:14 PM UTC 24 Sep 01 09:45:35 PM UTC 24 962198928 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_smoke.406032852 Sep 01 09:45:26 PM UTC 24 Sep 01 09:45:39 PM UTC 24 520846757 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.3341189958 Sep 01 09:45:47 PM UTC 24 Sep 01 09:45:52 PM UTC 24 99770989 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access.3348166799 Sep 01 09:45:35 PM UTC 24 Sep 01 09:46:05 PM UTC 24 3543724321 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_bijection.2121282690 Sep 01 09:45:28 PM UTC 24 Sep 01 09:46:08 PM UTC 24 1195474033 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.1426943930 Sep 01 09:45:40 PM UTC 24 Sep 01 09:46:09 PM UTC 24 92331793 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.3395117418 Sep 01 09:46:09 PM UTC 24 Sep 01 09:46:11 PM UTC 24 212705995 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.3300403568 Sep 01 09:46:12 PM UTC 24 Sep 01 09:46:21 PM UTC 24 245194996 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.1615868835 Sep 01 09:45:15 PM UTC 24 Sep 01 09:46:21 PM UTC 24 115074729 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.2884909322 Sep 01 09:46:10 PM UTC 24 Sep 01 09:46:24 PM UTC 24 140219146 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_alert_test.3533064053 Sep 01 09:46:24 PM UTC 24 Sep 01 09:46:27 PM UTC 24 50455023 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.1701516269 Sep 01 09:46:23 PM UTC 24 Sep 01 09:46:28 PM UTC 24 1166816540 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_smoke.1697273727 Sep 01 09:46:25 PM UTC 24 Sep 01 09:46:39 PM UTC 24 365486308 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access.3140213512 Sep 01 09:45:15 PM UTC 24 Sep 01 09:46:50 PM UTC 24 2426261995 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access.901635819 Sep 01 09:46:51 PM UTC 24 Sep 01 09:47:06 PM UTC 24 732566924 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_bijection.303853439 Sep 01 09:46:30 PM UTC 24 Sep 01 09:47:08 PM UTC 24 5137821611 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.3967332204 Sep 01 09:45:15 PM UTC 24 Sep 01 09:47:15 PM UTC 24 546023006 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.2846222287 Sep 01 09:47:15 PM UTC 24 Sep 01 09:47:25 PM UTC 24 1336831483 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.2582187361 Sep 01 09:47:34 PM UTC 24 Sep 01 09:47:36 PM UTC 24 114150111 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.3693692633 Sep 01 09:45:41 PM UTC 24 Sep 01 09:47:42 PM UTC 24 168291920 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.699551654 Sep 01 09:47:37 PM UTC 24 Sep 01 09:47:44 PM UTC 24 242012221 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.2030103265 Sep 01 09:47:43 PM UTC 24 Sep 01 09:47:50 PM UTC 24 65039817 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.1473604959 Sep 01 09:47:09 PM UTC 24 Sep 01 09:47:52 PM UTC 24 1600700011 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3011267339 Sep 01 09:47:45 PM UTC 24 Sep 01 09:47:55 PM UTC 24 588240817 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.3720023886 Sep 01 09:47:52 PM UTC 24 Sep 01 09:47:58 PM UTC 24 262681266 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_alert_test.3446242775 Sep 01 09:47:56 PM UTC 24 Sep 01 09:47:58 PM UTC 24 29678882 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_smoke.3607323900 Sep 01 09:47:58 PM UTC 24 Sep 01 09:48:20 PM UTC 24 723284883 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_regwen.491093690 Sep 01 09:47:26 PM UTC 24 Sep 01 09:48:21 PM UTC 24 1657922236 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access.890847926 Sep 01 09:48:23 PM UTC 24 Sep 01 09:48:29 PM UTC 24 346938123 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all.2041187228 Sep 01 09:45:19 PM UTC 24 Sep 01 09:48:33 PM UTC 24 85674153099 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.3695124294 Sep 01 09:48:50 PM UTC 24 Sep 01 09:48:56 PM UTC 24 533089500 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.503570106 Sep 01 09:47:14 PM UTC 24 Sep 01 09:49:08 PM UTC 24 158868726 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.3986297061 Sep 01 09:48:34 PM UTC 24 Sep 01 09:49:13 PM UTC 24 246233956 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.677521446 Sep 01 09:49:14 PM UTC 24 Sep 01 09:49:16 PM UTC 24 32005151 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.2051868153 Sep 01 09:49:21 PM UTC 24 Sep 01 09:49:26 PM UTC 24 165936420 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.1424075225 Sep 01 09:49:17 PM UTC 24 Sep 01 09:49:36 PM UTC 24 1358857412 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.718153558 Sep 01 09:45:15 PM UTC 24 Sep 01 09:49:47 PM UTC 24 2453174137 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.1872580110 Sep 01 09:45:34 PM UTC 24 Sep 01 09:49:52 PM UTC 24 2248321370 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.1800655688 Sep 01 09:49:48 PM UTC 24 Sep 01 09:49:54 PM UTC 24 244343570 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_alert_test.3772689273 Sep 01 09:49:52 PM UTC 24 Sep 01 09:49:54 PM UTC 24 13765424 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_bijection.3617291339 Sep 01 09:48:14 PM UTC 24 Sep 01 09:50:05 PM UTC 24 3542933369 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_smoke.3548583701 Sep 01 09:49:54 PM UTC 24 Sep 01 09:50:15 PM UTC 24 86354092 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.1472877947 Sep 01 09:48:30 PM UTC 24 Sep 01 09:50:22 PM UTC 24 139605104 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.108994019 Sep 01 09:50:36 PM UTC 24 Sep 01 09:50:41 PM UTC 24 84063283 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.3672772268 Sep 01 09:45:15 PM UTC 24 Sep 01 09:50:43 PM UTC 24 4432982738 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.2098777243 Sep 01 09:50:41 PM UTC 24 Sep 01 09:50:51 PM UTC 24 1695646548 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1631327331 Sep 01 09:45:16 PM UTC 24 Sep 01 09:50:58 PM UTC 24 1431109761 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.1262018074 Sep 01 09:50:22 PM UTC 24 Sep 01 09:51:05 PM UTC 24 330133575 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.618134248 Sep 01 09:51:07 PM UTC 24 Sep 01 09:51:09 PM UTC 24 27228901 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.1317208462 Sep 01 09:51:10 PM UTC 24 Sep 01 09:51:17 PM UTC 24 555914504 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.3041178551 Sep 01 09:51:08 PM UTC 24 Sep 01 09:51:17 PM UTC 24 100855517 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_bijection.2258007035 Sep 01 09:49:56 PM UTC 24 Sep 01 09:51:21 PM UTC 24 7769250503 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.3837203802 Sep 01 09:51:21 PM UTC 24 Sep 01 09:51:25 PM UTC 24 186926444 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_alert_test.2862298374 Sep 01 09:51:26 PM UTC 24 Sep 01 09:51:28 PM UTC 24 86450597 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_smoke.2441785416 Sep 01 09:51:29 PM UTC 24 Sep 01 09:51:48 PM UTC 24 622465380 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.466906163 Sep 01 09:51:17 PM UTC 24 Sep 01 09:51:49 PM UTC 24 905632372 ps
T173 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access.3177017117 Sep 01 09:50:07 PM UTC 24 Sep 01 09:52:16 PM UTC 24 1442196819 ps
T112 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.3856098621 Sep 01 09:46:40 PM UTC 24 Sep 01 09:52:17 PM UTC 24 2784151262 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.682727106 Sep 01 09:48:21 PM UTC 24 Sep 01 09:52:32 PM UTC 24 2140282133 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.1329442383 Sep 01 09:49:27 PM UTC 24 Sep 01 09:52:41 PM UTC 24 8346829160 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.2523947080 Sep 01 09:48:23 PM UTC 24 Sep 01 09:52:46 PM UTC 24 11067867214 ps
T174 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.3181054866 Sep 01 09:52:43 PM UTC 24 Sep 01 09:52:56 PM UTC 24 2068503001 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_regwen.1465797589 Sep 01 09:46:06 PM UTC 24 Sep 01 09:53:03 PM UTC 24 15363366066 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_bijection.2596829550 Sep 01 09:51:49 PM UTC 24 Sep 01 09:53:15 PM UTC 24 8443879412 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.383010734 Sep 01 09:53:16 PM UTC 24 Sep 01 09:53:18 PM UTC 24 31278406 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access.4232403892 Sep 01 09:52:17 PM UTC 24 Sep 01 09:53:34 PM UTC 24 548175563 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.842508364 Sep 01 09:53:19 PM UTC 24 Sep 01 09:53:35 PM UTC 24 3253116113 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.562339812 Sep 01 09:53:35 PM UTC 24 Sep 01 09:53:42 PM UTC 24 103478713 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1741431009 Sep 01 09:53:36 PM UTC 24 Sep 01 09:54:05 PM UTC 24 2668440659 ps
T126 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_alert_test.1784100154 Sep 01 09:54:06 PM UTC 24 Sep 01 09:54:08 PM UTC 24 13032133 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.2961178308 Sep 01 09:52:33 PM UTC 24 Sep 01 09:54:12 PM UTC 24 123171431 ps
T128 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_smoke.4215255140 Sep 01 09:54:10 PM UTC 24 Sep 01 09:54:19 PM UTC 24 100404175 ps
T129 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.1679195717 Sep 01 09:52:34 PM UTC 24 Sep 01 09:54:40 PM UTC 24 164256094 ps
T115 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.548359042 Sep 01 09:49:58 PM UTC 24 Sep 01 09:54:48 PM UTC 24 16266327924 ps
T130 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access.177147100 Sep 01 09:54:41 PM UTC 24 Sep 01 09:55:05 PM UTC 24 1249292271 ps
T131 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.110863911 Sep 01 09:55:06 PM UTC 24 Sep 01 09:55:09 PM UTC 24 68462902 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_executable.1508961640 Sep 01 09:46:01 PM UTC 24 Sep 01 09:55:15 PM UTC 24 23620948064 ps
T132 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.1654202939 Sep 01 09:55:15 PM UTC 24 Sep 01 09:55:25 PM UTC 24 2757225891 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.427628315 Sep 01 09:45:35 PM UTC 24 Sep 01 09:56:03 PM UTC 24 82471510079 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.1087847767 Sep 01 09:55:10 PM UTC 24 Sep 01 09:56:09 PM UTC 24 627852544 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.1917810854 Sep 01 09:56:10 PM UTC 24 Sep 01 09:56:12 PM UTC 24 84860114 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_bijection.881115535 Sep 01 09:54:21 PM UTC 24 Sep 01 09:56:14 PM UTC 24 25282561310 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.2492896217 Sep 01 09:56:15 PM UTC 24 Sep 01 09:56:24 PM UTC 24 629119902 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.898451940 Sep 01 09:56:13 PM UTC 24 Sep 01 09:56:31 PM UTC 24 1340273088 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_alert_test.1259057723 Sep 01 09:56:32 PM UTC 24 Sep 01 09:56:33 PM UTC 24 21241602 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.1647898131 Sep 01 09:50:16 PM UTC 24 Sep 01 09:56:50 PM UTC 24 34844156788 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.3076262744 Sep 01 09:47:07 PM UTC 24 Sep 01 09:57:26 PM UTC 24 16941813210 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_executable.3975952184 Sep 01 09:45:16 PM UTC 24 Sep 01 09:57:34 PM UTC 24 31063541375 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.4254781215 Sep 01 09:54:26 PM UTC 24 Sep 01 09:57:41 PM UTC 24 2974679301 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.1241147457 Sep 01 09:57:27 PM UTC 24 Sep 01 09:57:46 PM UTC 24 821775358 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.2975015242 Sep 01 09:57:46 PM UTC 24 Sep 01 09:57:49 PM UTC 24 118712696 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.3044578883 Sep 01 09:51:50 PM UTC 24 Sep 01 09:57:51 PM UTC 24 23405124445 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.3068081975 Sep 01 09:57:42 PM UTC 24 Sep 01 09:57:52 PM UTC 24 202381069 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.3071853060 Sep 01 09:57:50 PM UTC 24 Sep 01 09:57:54 PM UTC 24 255925673 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.2002509353 Sep 01 09:52:18 PM UTC 24 Sep 01 09:58:09 PM UTC 24 11349077852 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.79730607 Sep 01 09:58:10 PM UTC 24 Sep 01 09:58:12 PM UTC 24 35628623 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.2851120689 Sep 01 09:56:35 PM UTC 24 Sep 01 09:58:18 PM UTC 24 149957038 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.3043035741 Sep 01 09:57:01 PM UTC 24 Sep 01 09:58:25 PM UTC 24 6784120877 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.293737282 Sep 01 09:58:19 PM UTC 24 Sep 01 09:58:25 PM UTC 24 378934808 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.1098574876 Sep 01 09:58:13 PM UTC 24 Sep 01 09:58:28 PM UTC 24 601779218 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.4102565388 Sep 01 09:58:29 PM UTC 24 Sep 01 09:58:31 PM UTC 24 90902818 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_executable.3243823457 Sep 01 09:48:59 PM UTC 24 Sep 01 09:58:45 PM UTC 24 7825247836 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.1899620673 Sep 01 09:58:33 PM UTC 24 Sep 01 09:58:47 PM UTC 24 800313682 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.4150937511 Sep 01 09:54:48 PM UTC 24 Sep 01 09:58:49 PM UTC 24 8784737407 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.3855656720 Sep 01 09:59:16 PM UTC 24 Sep 01 09:59:33 PM UTC 24 264208167 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.2631226865 Sep 01 09:59:36 PM UTC 24 Sep 01 09:59:43 PM UTC 24 446697241 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_regwen.288807376 Sep 01 09:49:08 PM UTC 24 Sep 01 09:59:51 PM UTC 24 15014896245 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.726242838 Sep 01 09:59:44 PM UTC 24 Sep 01 09:59:56 PM UTC 24 1624407532 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.3647853073 Sep 01 09:45:52 PM UTC 24 Sep 01 09:59:59 PM UTC 24 2138194730 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.1398584228 Sep 01 09:57:34 PM UTC 24 Sep 01 10:00:24 PM UTC 24 4141863233 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.1447730347 Sep 01 10:00:25 PM UTC 24 Sep 01 10:00:27 PM UTC 24 26396248 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.3353324161 Sep 01 09:58:48 PM UTC 24 Sep 01 10:00:28 PM UTC 24 5032901624 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_executable.3142642156 Sep 01 09:50:52 PM UTC 24 Sep 01 10:00:33 PM UTC 24 7610536757 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.1755008697 Sep 01 10:00:29 PM UTC 24 Sep 01 10:00:34 PM UTC 24 58332044 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3845611364 Sep 01 10:00:28 PM UTC 24 Sep 01 10:00:35 PM UTC 24 777401603 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.3113830672 Sep 01 10:00:35 PM UTC 24 Sep 01 10:00:37 PM UTC 24 19228248 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.315439282 Sep 01 09:47:16 PM UTC 24 Sep 01 10:00:48 PM UTC 24 21321335376 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.654379386 Sep 01 10:00:39 PM UTC 24 Sep 01 10:01:04 PM UTC 24 906828731 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.1747661889 Sep 01 09:59:34 PM UTC 24 Sep 01 10:01:07 PM UTC 24 130201294 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.3444981043 Sep 01 09:45:26 PM UTC 24 Sep 01 10:01:23 PM UTC 24 14111979468 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_regwen.2140836129 Sep 01 09:45:16 PM UTC 24 Sep 01 10:01:58 PM UTC 24 55326285130 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.36397410 Sep 01 10:01:08 PM UTC 24 Sep 01 10:02:06 PM UTC 24 521698799 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.1675037652 Sep 01 10:02:04 PM UTC 24 Sep 01 10:02:07 PM UTC 24 118398043 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.2778635388 Sep 01 10:01:59 PM UTC 24 Sep 01 10:02:10 PM UTC 24 364934159 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.1294550198 Sep 01 10:02:11 PM UTC 24 Sep 01 10:02:13 PM UTC 24 30062498 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.1993347180 Sep 01 10:02:14 PM UTC 24 Sep 01 10:02:25 PM UTC 24 352196886 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_regwen.590129208 Sep 01 09:56:04 PM UTC 24 Sep 01 10:02:27 PM UTC 24 6190363182 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.2929865421 Sep 01 10:01:01 PM UTC 24 Sep 01 10:02:29 PM UTC 24 15315003034 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.292327938 Sep 01 10:01:34 PM UTC 24 Sep 01 10:02:30 PM UTC 24 625696235 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.4010779336 Sep 01 10:02:29 PM UTC 24 Sep 01 10:02:31 PM UTC 24 42734754 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.2026168265 Sep 01 10:02:26 PM UTC 24 Sep 01 10:02:31 PM UTC 24 46535859 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.572200112 Sep 01 09:45:14 PM UTC 24 Sep 01 10:02:33 PM UTC 24 4121086155 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_smoke.922012616 Sep 01 10:02:30 PM UTC 24 Sep 01 10:02:52 PM UTC 24 291623389 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3448148968 Sep 01 10:02:27 PM UTC 24 Sep 01 10:03:20 PM UTC 24 1428693501 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_executable.179531141 Sep 01 09:55:26 PM UTC 24 Sep 01 10:03:39 PM UTC 24 14543853856 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2411539744 Sep 01 09:56:23 PM UTC 24 Sep 01 10:03:48 PM UTC 24 1227119034 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.223854811 Sep 01 09:57:23 PM UTC 24 Sep 01 10:03:56 PM UTC 24 26483556794 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access.1109648487 Sep 01 10:02:53 PM UTC 24 Sep 01 10:03:59 PM UTC 24 309758216 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.181859414 Sep 01 10:03:40 PM UTC 24 Sep 01 10:04:03 PM UTC 24 337101298 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.4012668399 Sep 01 10:03:56 PM UTC 24 Sep 01 10:04:08 PM UTC 24 6248220393 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.233509509 Sep 01 10:04:10 PM UTC 24 Sep 01 10:04:12 PM UTC 24 30769362 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.1939573127 Sep 01 10:04:13 PM UTC 24 Sep 01 10:04:25 PM UTC 24 595480043 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_bijection.1419678815 Sep 01 10:02:33 PM UTC 24 Sep 01 10:04:25 PM UTC 24 3364224637 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.2686578330 Sep 01 10:04:26 PM UTC 24 Sep 01 10:04:31 PM UTC 24 102578394 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.149321783 Sep 01 09:46:28 PM UTC 24 Sep 01 10:04:54 PM UTC 24 3756055296 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_alert_test.794722587 Sep 01 10:04:55 PM UTC 24 Sep 01 10:04:57 PM UTC 24 57169068 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_smoke.1073411691 Sep 01 10:04:59 PM UTC 24 Sep 01 10:05:01 PM UTC 24 37177023 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.402422956 Sep 01 09:57:53 PM UTC 24 Sep 01 10:05:41 PM UTC 24 14124674207 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_smoke.254790341 Sep 01 10:06:39 PM UTC 24 Sep 01 10:07:07 PM UTC 24 1064575616 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.1520672936 Sep 01 10:03:48 PM UTC 24 Sep 01 10:05:54 PM UTC 24 168836063 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.1858209977 Sep 01 10:00:00 PM UTC 24 Sep 01 10:05:56 PM UTC 24 4496433760 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.32951505 Sep 01 09:50:44 PM UTC 24 Sep 01 10:05:56 PM UTC 24 6757812399 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.3766699624 Sep 01 10:05:57 PM UTC 24 Sep 01 10:06:05 PM UTC 24 1655071380 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.1884931635 Sep 01 10:01:24 PM UTC 24 Sep 01 10:06:14 PM UTC 24 11460846001 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.3907585873 Sep 01 09:49:55 PM UTC 24 Sep 01 10:06:21 PM UTC 24 2844233470 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.354682609 Sep 01 10:05:57 PM UTC 24 Sep 01 10:06:22 PM UTC 24 133910992 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.3009226601 Sep 01 10:06:21 PM UTC 24 Sep 01 10:06:23 PM UTC 24 88900730 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.60839182 Sep 01 10:06:24 PM UTC 24 Sep 01 10:06:30 PM UTC 24 361019082 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.2442734698 Sep 01 10:01:05 PM UTC 24 Sep 01 10:06:33 PM UTC 24 10495403792 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3912376292 Sep 01 10:04:26 PM UTC 24 Sep 01 10:06:35 PM UTC 24 1308452187 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.3305439968 Sep 01 10:06:23 PM UTC 24 Sep 01 10:06:38 PM UTC 24 1433831812 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_alert_test.1390852602 Sep 01 10:06:36 PM UTC 24 Sep 01 10:06:38 PM UTC 24 38344850 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.2267422197 Sep 01 09:45:15 PM UTC 24 Sep 01 10:06:43 PM UTC 24 3931144354 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.285561671 Sep 01 09:58:50 PM UTC 24 Sep 01 10:06:48 PM UTC 24 4645285721 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_bijection.3869685337 Sep 01 10:05:28 PM UTC 24 Sep 01 10:07:01 PM UTC 24 3179534026 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.3268495077 Sep 01 09:59:57 PM UTC 24 Sep 01 10:07:24 PM UTC 24 4471515347 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_bijection.3542864878 Sep 01 10:06:44 PM UTC 24 Sep 01 10:07:24 PM UTC 24 2005620906 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access.2331816622 Sep 01 10:05:39 PM UTC 24 Sep 01 10:07:25 PM UTC 24 420120066 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.4260139707 Sep 01 10:07:25 PM UTC 24 Sep 01 10:07:30 PM UTC 24 596056206 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.1808359319 Sep 01 10:07:26 PM UTC 24 Sep 01 10:07:33 PM UTC 24 242653870 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.1373961295 Sep 01 10:07:25 PM UTC 24 Sep 01 10:07:35 PM UTC 24 69889001 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.3704426662 Sep 01 09:55:26 PM UTC 24 Sep 01 10:07:45 PM UTC 24 2564278736 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.2990501592 Sep 01 10:07:46 PM UTC 24 Sep 01 10:07:48 PM UTC 24 77871430 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_executable.874584218 Sep 01 09:47:18 PM UTC 24 Sep 01 10:07:57 PM UTC 24 11003782383 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.54969108 Sep 01 10:05:56 PM UTC 24 Sep 01 10:07:57 PM UTC 24 504217645 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.245846374 Sep 01 10:07:49 PM UTC 24 Sep 01 10:07:58 PM UTC 24 236417560 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.3241344622 Sep 01 10:02:34 PM UTC 24 Sep 01 10:08:03 PM UTC 24 8654414933 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.4023337614 Sep 01 10:07:57 PM UTC 24 Sep 01 10:08:06 PM UTC 24 167314743 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_alert_test.3884782935 Sep 01 10:08:04 PM UTC 24 Sep 01 10:08:06 PM UTC 24 50376772 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_smoke.1401294398 Sep 01 10:08:05 PM UTC 24 Sep 01 10:08:07 PM UTC 24 108655840 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access.3942093436 Sep 01 10:08:14 PM UTC 24 Sep 01 10:08:19 PM UTC 24 208836343 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_regwen.2057755706 Sep 01 10:04:09 PM UTC 24 Sep 01 10:08:20 PM UTC 24 4059362914 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_regwen.2690627765 Sep 01 09:50:59 PM UTC 24 Sep 01 10:08:22 PM UTC 24 10848644603 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access.787647477 Sep 01 10:07:01 PM UTC 24 Sep 01 10:08:32 PM UTC 24 3190898677 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1813660603 Sep 01 10:06:30 PM UTC 24 Sep 01 10:08:35 PM UTC 24 7981429243 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.1264116012 Sep 01 10:08:33 PM UTC 24 Sep 01 10:08:40 PM UTC 24 1822906143 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3124541298 Sep 01 10:07:58 PM UTC 24 Sep 01 10:08:41 PM UTC 24 1506689684 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.1925324515 Sep 01 10:08:23 PM UTC 24 Sep 01 10:08:49 PM UTC 24 92551413 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.660182008 Sep 01 10:08:50 PM UTC 24 Sep 01 10:08:53 PM UTC 24 29228275 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.4081365246 Sep 01 10:08:54 PM UTC 24 Sep 01 10:09:00 PM UTC 24 77223522 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.1809551146 Sep 01 09:57:55 PM UTC 24 Sep 01 10:09:03 PM UTC 24 13158301746 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_bijection.212393400 Sep 01 10:08:06 PM UTC 24 Sep 01 10:09:05 PM UTC 24 786136170 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.2526228382 Sep 01 10:09:01 PM UTC 24 Sep 01 10:09:10 PM UTC 24 1108125388 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_alert_test.1958839299 Sep 01 10:09:11 PM UTC 24 Sep 01 10:09:13 PM UTC 24 11914686 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_smoke.260751011 Sep 01 10:09:14 PM UTC 24 Sep 01 10:09:24 PM UTC 24 218761605 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.2902818407 Sep 01 10:05:32 PM UTC 24 Sep 01 10:09:43 PM UTC 24 15212512756 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.1200431087 Sep 01 10:06:39 PM UTC 24 Sep 01 10:09:48 PM UTC 24 1783608693 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all.916360883 Sep 01 10:09:06 PM UTC 24 Sep 01 10:10:11 PM UTC 24 12637343712 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.2487647602 Sep 01 10:02:07 PM UTC 24 Sep 01 10:10:17 PM UTC 24 13815485670 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access.149997589 Sep 01 10:10:13 PM UTC 24 Sep 01 10:10:19 PM UTC 24 680805663 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.3191173730 Sep 01 10:08:21 PM UTC 24 Sep 01 10:10:27 PM UTC 24 526092164 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.1725375733 Sep 01 10:10:28 PM UTC 24 Sep 01 10:10:35 PM UTC 24 2886395572 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_regwen.36094660 Sep 01 10:08:42 PM UTC 24 Sep 01 10:10:35 PM UTC 24 2987953596 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.4260851734 Sep 01 10:10:18 PM UTC 24 Sep 01 10:10:52 PM UTC 24 167496920 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_regwen.956341429 Sep 01 09:53:04 PM UTC 24 Sep 01 10:10:54 PM UTC 24 59216033701 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_bijection.3312718024 Sep 01 10:09:43 PM UTC 24 Sep 01 10:10:56 PM UTC 24 9110484442 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.2228316732 Sep 01 10:10:55 PM UTC 24 Sep 01 10:10:57 PM UTC 24 91101427 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.2794308313 Sep 01 10:10:58 PM UTC 24 Sep 01 10:11:04 PM UTC 24 102878740 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_executable.3205040018 Sep 01 10:07:33 PM UTC 24 Sep 01 10:11:04 PM UTC 24 6071963453 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.1952471391 Sep 01 10:08:08 PM UTC 24 Sep 01 10:11:07 PM UTC 24 12282268275 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.1779567009 Sep 01 10:03:21 PM UTC 24 Sep 01 10:11:10 PM UTC 24 37012340459 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_alert_test.293937427 Sep 01 10:11:08 PM UTC 24 Sep 01 10:11:10 PM UTC 24 14702351 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.2977905584 Sep 01 10:10:56 PM UTC 24 Sep 01 10:11:12 PM UTC 24 351677690 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.668591019 Sep 01 10:10:20 PM UTC 24 Sep 01 10:11:16 PM UTC 24 237408274 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.289400960 Sep 01 10:07:32 PM UTC 24 Sep 01 10:11:29 PM UTC 24 2784224754 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_smoke.3470789709 Sep 01 10:11:11 PM UTC 24 Sep 01 10:11:30 PM UTC 24 641551474 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access.40024559 Sep 01 10:11:30 PM UTC 24 Sep 01 10:11:47 PM UTC 24 1139846716 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.3149688856 Sep 01 09:59:31 PM UTC 24 Sep 01 10:11:55 PM UTC 24 201201386923 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.541741559 Sep 01 10:00:49 PM UTC 24 Sep 01 10:11:57 PM UTC 24 41632069911 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.3740942908 Sep 01 10:11:56 PM UTC 24 Sep 01 10:11:59 PM UTC 24 327055219 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.3738109054 Sep 01 09:47:59 PM UTC 24 Sep 01 10:12:05 PM UTC 24 19614030263 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.3467986759 Sep 01 10:11:50 PM UTC 24 Sep 01 10:12:06 PM UTC 24 270962039 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.2561019860 Sep 01 10:08:36 PM UTC 24 Sep 01 10:12:07 PM UTC 24 7836767923 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.1783322252 Sep 01 10:12:07 PM UTC 24 Sep 01 10:12:09 PM UTC 24 31777915 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_executable.3814424995 Sep 01 10:10:37 PM UTC 24 Sep 01 10:12:14 PM UTC 24 13808067679 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.2154605126 Sep 01 10:12:10 PM UTC 24 Sep 01 10:12:16 PM UTC 24 232223515 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.3166547352 Sep 01 10:06:49 PM UTC 24 Sep 01 10:12:17 PM UTC 24 2850676620 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_alert_test.1703114219 Sep 01 10:12:18 PM UTC 24 Sep 01 10:12:19 PM UTC 24 15518787 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.2952541309 Sep 01 10:12:08 PM UTC 24 Sep 01 10:12:26 PM UTC 24 691661568 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.3697328429 Sep 01 10:05:42 PM UTC 24 Sep 01 10:12:27 PM UTC 24 25900069313 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2313340909 Sep 01 10:12:14 PM UTC 24 Sep 01 10:12:34 PM UTC 24 4048220334 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_bijection.2188928900 Sep 01 10:11:13 PM UTC 24 Sep 01 10:12:35 PM UTC 24 3822185321 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_bijection.2440103566 Sep 01 10:12:28 PM UTC 24 Sep 01 10:13:04 PM UTC 24 1244108798 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.3205867109 Sep 01 10:11:48 PM UTC 24 Sep 01 10:13:07 PM UTC 24 1269371380 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_smoke.3371658753 Sep 01 10:12:21 PM UTC 24 Sep 01 10:13:23 PM UTC 24 459999360 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.924283243 Sep 01 10:13:23 PM UTC 24 Sep 01 10:13:31 PM UTC 24 1419558795 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.1102903694 Sep 01 10:13:04 PM UTC 24 Sep 01 10:13:36 PM UTC 24 162903028 ps
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