Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	150268644	1			T1	966		T3	6560		T4	1824
instr_valid_dis	117074091	1			T1	966		T3	6560		T4	1824
instr_en	22695881	1			T24	3005		T37	35566		T18	183106

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10681474	1			T24	3001		T132	13916		T130	2716
sram_ifetch_valid_disable	115431326	1			T1	966		T3	6560		T4	1824
sram_ifetch_enable	24155844	1			T25	3966		T37	34910		T18	167306

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	150268644	1			T1	966		T3	6560		T4	1824
hw_debug_en_valid_off	115332053	1			T1	966		T3	6560		T4	1824
hw_debug_en_on	24235199	1			T24	5916		T25	3966		T18	131698

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	115431326	1			T1	966		T3	6560		T4	1824
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	102006652	1			T1	966		T3	6560		T4	1824
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9435314	1			T24	4		T37	656		T18	15800
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4315282	1			T24	1893		T130	2716		T19	58710
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1863167	1			T130	2716		T131	9038		T135	20000
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1822127	1			T24	1893		T19	58710		T140	10032
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4434688	1			T132	13916		T133	43156		T135	39726
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1908538	1			T133	1158		T135	39726		T139	32518
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1688318	1			T133	32452		T139	52870		T142	30380
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8466766	1			T24	5916		T132	40		T133	57990
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3271373	1			T133	57448		T131	41158		T141	47324
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3425453	1			T139	25840		T140	43016		T142	38194

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8956486	1			T37	34910		T18	167306		T134	20076
lc_exec_en	11333745	1			T25	3966		T18	131698		T132	57112
valid_exec_dis	113146958	1			T1	966		T3	6560		T4	1824
invalid_exec_dis	34837318	1			T24	3001		T25	3966		T37	34910