Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44


Total tests in report: 1029
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
71.61 71.61 95.42 95.42 67.30 67.30 39.60 39.60 85.71 85.71 85.02 85.02 94.54 94.54 33.64 33.64 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.3914724833
90.11 18.50 97.29 1.86 82.82 15.52 96.98 57.39 90.48 4.76 89.86 4.83 96.02 1.47 77.33 43.69 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1771757496
92.96 2.85 98.64 1.36 86.02 3.20 98.23 1.25 100.00 9.52 93.00 3.14 96.61 0.59 78.24 0.91 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.6237682
94.19 1.23 98.90 0.25 88.03 2.01 98.23 0.00 100.00 0.00 94.20 1.21 96.61 0.00 83.36 5.12 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all.3551735302
94.97 0.78 98.90 0.00 88.39 0.36 98.23 0.00 100.00 0.00 94.20 0.00 96.61 0.00 88.48 5.12 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1929433528
95.53 0.56 98.98 0.08 89.10 0.71 98.23 0.00 100.00 0.00 94.93 0.72 96.61 0.00 90.86 2.38 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_executable.1148353616
96.04 0.51 99.07 0.08 90.28 1.18 98.75 0.52 100.00 0.00 95.65 0.72 96.90 0.29 91.59 0.73 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.4125328966
96.36 0.33 99.07 0.00 90.52 0.24 98.82 0.07 100.00 0.00 95.65 0.00 98.53 1.62 91.96 0.37 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2070894652
96.65 0.28 99.07 0.00 90.52 0.00 98.82 0.00 100.00 0.00 95.65 0.00 98.67 0.15 93.78 1.83 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.3634984706
96.78 0.13 99.15 0.08 90.52 0.00 99.65 0.83 100.00 0.00 95.65 0.00 98.67 0.00 93.78 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.2941165671
96.91 0.13 99.15 0.00 90.52 0.00 99.65 0.00 100.00 0.00 95.65 0.00 98.67 0.00 94.70 0.91 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.1212230819
97.04 0.13 99.15 0.00 90.52 0.00 99.65 0.00 100.00 0.00 95.65 0.00 98.67 0.00 95.61 0.91 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_regwen.1917329050
97.13 0.09 99.15 0.00 90.64 0.12 99.65 0.00 100.00 0.00 95.89 0.24 98.97 0.29 95.61 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1144328558
97.22 0.09 99.15 0.00 91.00 0.36 99.72 0.07 100.00 0.00 95.89 0.00 98.97 0.00 95.80 0.18 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_alert_test.278869264
97.30 0.08 99.15 0.00 91.00 0.00 99.72 0.00 100.00 0.00 95.89 0.00 98.97 0.00 96.34 0.55 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_executable.1091839646
97.35 0.05 99.15 0.00 91.00 0.00 99.72 0.00 100.00 0.00 95.89 0.00 98.97 0.00 96.71 0.37 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.804700341
97.38 0.03 99.15 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.14 0.24 98.97 0.00 96.71 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_bijection.3936907000
97.41 0.03 99.15 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.14 0.00 98.97 0.00 96.89 0.18 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.234610180
97.44 0.03 99.15 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.14 0.00 98.97 0.00 97.07 0.18 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.4117398374
97.46 0.03 99.15 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.14 0.00 98.97 0.00 97.26 0.18 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1370017908
97.49 0.03 99.15 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.14 0.00 98.97 0.00 97.44 0.18 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.873577146
97.51 0.02 99.15 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.14 0.00 99.12 0.15 97.44 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3522951481

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3679596461
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1983507455
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3479560424
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1731955228
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3386664042
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3499025986
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2330384112
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.141032776
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3363894670
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3315516802
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3539892068
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1069674023
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4267629516
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2171742968
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1632923161
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.994076523
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1750176073
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2053224628
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.424268459
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3227048089
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.501457012
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1069540756
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1794947527
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2728094347
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3100294663
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1069825223
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3569822611
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.92605022
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1228057711
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1400966874
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1590096388
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.761638672
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2536675949
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.708950809
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2632899768
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.4009523546
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1711879607
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.929780693
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3056080663
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.354992948
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.227148955
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.933477754
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1647853894
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2564470649
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3500468288
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2508842108
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3740281877
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.132123109
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1622886031
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2492073231
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1062227551
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4177717675
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1454346305
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.897174062
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3445819477
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3004682210
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1991425080
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.391435726
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2020312316
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2371885850
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1095210861
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1635395211
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.481309422
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3046827031
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.115982392
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1592211277
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.876428394
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.278353352
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1189076665
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3775197556
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2166959321
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2997815986
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1512643113
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3535495320
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1804700310
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2037362356
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2711611066
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1233179156
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3058192232
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.265765959
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3268602935
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1843389228
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.755143912
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1516764255
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.722433718
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.4096568950
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3176589419
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/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.1331707188
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_regwen.3513084474
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_smoke.3748558788
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all.2424610361
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3307452551
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.1359802041
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.2850558798
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.3657614385
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.166583984
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.4043036174
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.1900952443
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.3895145418
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.3272195677
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.755549436
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.900033015
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.4011618200
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.3189486165
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.1067643305
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.2444674013
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.240994719
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.2544356243
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.2558167128
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.741851370
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.2240422827
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.4161092383
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.573523209
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.1747086761
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.1396176217
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.832407544
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.3330954383
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.952592684
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3885172975
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.2893998706
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.2121143465
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.2486458435
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.3761780799
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.3687355564
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.1554417029
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all.1854104506
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3294961932
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.1253139933
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.1350742875
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.7446695
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.2884218999
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.742963595
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.155022162
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.1119075826
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.1297242912
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.1497484502
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.247958707
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.3264254007
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.195810168
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.2264272116
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.4010956509
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.4084236883
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.835317291
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.2221139529
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3883721882
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.3108014346
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.3112537228



Total test records in report: 1029
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.2036193729 Sep 04 03:31:16 PM UTC 24 Sep 04 03:31:20 PM UTC 24 44470088 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.2941165671 Sep 04 03:31:18 PM UTC 24 Sep 04 03:31:21 PM UTC 24 91581780 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access.2143142064 Sep 04 03:31:15 PM UTC 24 Sep 04 03:31:26 PM UTC 24 389519992 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.3914724833 Sep 04 03:31:21 PM UTC 24 Sep 04 03:31:27 PM UTC 24 426765499 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.4125328966 Sep 04 03:31:16 PM UTC 24 Sep 04 03:31:29 PM UTC 24 767737718 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.739931756 Sep 04 03:31:20 PM UTC 24 Sep 04 03:31:31 PM UTC 24 873578854 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.499170593 Sep 04 03:31:30 PM UTC 24 Sep 04 03:31:32 PM UTC 24 14327029 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.3378467123 Sep 04 03:31:16 PM UTC 24 Sep 04 03:31:32 PM UTC 24 263423197 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.1266227469 Sep 04 03:31:28 PM UTC 24 Sep 04 03:31:34 PM UTC 24 1386761492 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_smoke.1459217530 Sep 04 03:31:32 PM UTC 24 Sep 04 03:31:37 PM UTC 24 91645369 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access.3463665086 Sep 04 03:31:38 PM UTC 24 Sep 04 03:32:08 PM UTC 24 989425338 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_smoke.650901350 Sep 04 03:31:13 PM UTC 24 Sep 04 03:32:09 PM UTC 24 107273729 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1771757496 Sep 04 03:31:22 PM UTC 24 Sep 04 03:32:23 PM UTC 24 1028427149 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.1544258434 Sep 04 03:32:10 PM UTC 24 Sep 04 03:32:23 PM UTC 24 701159601 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.1233464505 Sep 04 03:32:48 PM UTC 24 Sep 04 03:32:50 PM UTC 24 51520145 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.3649357654 Sep 04 03:32:09 PM UTC 24 Sep 04 03:32:56 PM UTC 24 221652293 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_bijection.1573140613 Sep 04 03:31:33 PM UTC 24 Sep 04 03:32:58 PM UTC 24 25485983888 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.2233035741 Sep 04 03:32:51 PM UTC 24 Sep 04 03:33:02 PM UTC 24 356357970 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.3693734884 Sep 04 03:32:57 PM UTC 24 Sep 04 03:33:06 PM UTC 24 146910673 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.1885076644 Sep 04 03:33:03 PM UTC 24 Sep 04 03:33:08 PM UTC 24 255753527 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_alert_test.278869264 Sep 04 03:33:06 PM UTC 24 Sep 04 03:33:09 PM UTC 24 29765620 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_smoke.4265917154 Sep 04 03:33:06 PM UTC 24 Sep 04 03:33:21 PM UTC 24 535650053 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.4274974421 Sep 04 03:31:58 PM UTC 24 Sep 04 03:33:23 PM UTC 24 322264462 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.873577146 Sep 04 03:32:58 PM UTC 24 Sep 04 03:33:28 PM UTC 24 311126928 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access.2691209632 Sep 04 03:33:24 PM UTC 24 Sep 04 03:33:33 PM UTC 24 296347039 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_bijection.3936907000 Sep 04 03:31:15 PM UTC 24 Sep 04 03:33:40 PM UTC 24 99465200033 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.3988213000 Sep 04 03:33:34 PM UTC 24 Sep 04 03:33:46 PM UTC 24 77690742 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.2110475849 Sep 04 03:33:41 PM UTC 24 Sep 04 03:33:47 PM UTC 24 353253721 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.2557571219 Sep 04 03:33:55 PM UTC 24 Sep 04 03:33:57 PM UTC 24 61662705 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.2709360612 Sep 04 03:33:08 PM UTC 24 Sep 04 03:34:06 PM UTC 24 8543602213 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.1791928058 Sep 04 03:33:58 PM UTC 24 Sep 04 03:34:12 PM UTC 24 525159395 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.1640687266 Sep 04 03:34:07 PM UTC 24 Sep 04 03:34:16 PM UTC 24 676151738 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.3676131859 Sep 04 03:34:27 PM UTC 24 Sep 04 03:34:34 PM UTC 24 406445207 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_alert_test.3063832080 Sep 04 03:34:35 PM UTC 24 Sep 04 03:34:37 PM UTC 24 14886346 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.4208520943 Sep 04 03:34:13 PM UTC 24 Sep 04 03:34:39 PM UTC 24 298571730 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_smoke.2426494296 Sep 04 03:34:38 PM UTC 24 Sep 04 03:34:46 PM UTC 24 345719315 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.3006690716 Sep 04 03:33:32 PM UTC 24 Sep 04 03:35:03 PM UTC 24 137756921 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access.4107942244 Sep 04 03:35:04 PM UTC 24 Sep 04 03:35:11 PM UTC 24 201779279 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_bijection.3007708355 Sep 04 03:34:41 PM UTC 24 Sep 04 03:35:14 PM UTC 24 1704559056 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_regwen.1931462544 Sep 04 03:33:53 PM UTC 24 Sep 04 03:35:14 PM UTC 24 2992243423 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.250595221 Sep 04 03:35:14 PM UTC 24 Sep 04 03:35:20 PM UTC 24 56575463 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_bijection.2057508348 Sep 04 03:33:10 PM UTC 24 Sep 04 03:35:28 PM UTC 24 21624051586 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.261294333 Sep 04 03:35:21 PM UTC 24 Sep 04 03:35:40 PM UTC 24 3225027243 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.3194236842 Sep 04 03:36:11 PM UTC 24 Sep 04 03:36:13 PM UTC 24 34034947 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.1212230819 Sep 04 03:31:15 PM UTC 24 Sep 04 03:36:17 PM UTC 24 12059984042 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.1341990914 Sep 04 03:36:13 PM UTC 24 Sep 04 03:36:24 PM UTC 24 340084501 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.1354143546 Sep 04 03:36:15 PM UTC 24 Sep 04 03:36:25 PM UTC 24 167672571 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_alert_test.2991550187 Sep 04 03:36:24 PM UTC 24 Sep 04 03:36:26 PM UTC 24 13976193 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.226543133 Sep 04 03:36:23 PM UTC 24 Sep 04 03:36:28 PM UTC 24 1950771006 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2685298775 Sep 04 03:36:15 PM UTC 24 Sep 04 03:36:28 PM UTC 24 2531715056 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.558611513 Sep 04 03:35:15 PM UTC 24 Sep 04 03:36:38 PM UTC 24 132309239 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_smoke.3782597116 Sep 04 03:36:26 PM UTC 24 Sep 04 03:36:40 PM UTC 24 549515171 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.2058774716 Sep 04 03:36:41 PM UTC 24 Sep 04 03:36:53 PM UTC 24 820271414 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.3208412041 Sep 04 03:37:00 PM UTC 24 Sep 04 03:37:02 PM UTC 24 48885606 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.4055612810 Sep 04 03:34:41 PM UTC 24 Sep 04 03:37:04 PM UTC 24 3383149509 ps
T111 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_bijection.2255393822 Sep 04 03:36:30 PM UTC 24 Sep 04 03:37:07 PM UTC 24 2157516719 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_regwen.2155466904 Sep 04 03:31:18 PM UTC 24 Sep 04 03:37:07 PM UTC 24 7727563695 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.3081284383 Sep 04 03:37:06 PM UTC 24 Sep 04 03:37:12 PM UTC 24 194494538 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.3304671811 Sep 04 03:37:03 PM UTC 24 Sep 04 03:37:14 PM UTC 24 1845146128 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_alert_test.4097187772 Sep 04 03:37:15 PM UTC 24 Sep 04 03:37:17 PM UTC 24 45927190 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.6237682 Sep 04 03:37:12 PM UTC 24 Sep 04 03:37:19 PM UTC 24 417064734 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_smoke.2009575363 Sep 04 03:37:18 PM UTC 24 Sep 04 03:37:21 PM UTC 24 31488698 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.3934982072 Sep 04 03:31:35 PM UTC 24 Sep 04 03:37:30 PM UTC 24 2944802088 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.2305407873 Sep 04 03:36:39 PM UTC 24 Sep 04 03:37:33 PM UTC 24 375552932 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access.3687256341 Sep 04 03:36:30 PM UTC 24 Sep 04 03:37:45 PM UTC 24 754502026 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.3968103645 Sep 04 03:37:37 PM UTC 24 Sep 04 03:37:52 PM UTC 24 522984321 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access.3263801073 Sep 04 03:37:32 PM UTC 24 Sep 04 03:37:56 PM UTC 24 745192123 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.1776644382 Sep 04 03:36:41 PM UTC 24 Sep 04 03:38:01 PM UTC 24 136808332 ps
T118 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.2485133333 Sep 04 03:37:53 PM UTC 24 Sep 04 03:38:03 PM UTC 24 968367546 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.1268065412 Sep 04 03:33:23 PM UTC 24 Sep 04 03:38:26 PM UTC 24 12601125236 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.370947844 Sep 04 03:38:27 PM UTC 24 Sep 04 03:38:29 PM UTC 24 43629775 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_bijection.2159573749 Sep 04 03:37:21 PM UTC 24 Sep 04 03:38:33 PM UTC 24 12017327450 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.1687975460 Sep 04 03:38:34 PM UTC 24 Sep 04 03:38:40 PM UTC 24 93618246 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.1516495738 Sep 04 03:37:08 PM UTC 24 Sep 04 03:38:44 PM UTC 24 5320785430 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.928736833 Sep 04 03:38:30 PM UTC 24 Sep 04 03:38:45 PM UTC 24 215816561 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_alert_test.2652701962 Sep 04 03:38:46 PM UTC 24 Sep 04 03:38:48 PM UTC 24 23864948 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_smoke.3748558788 Sep 04 03:38:49 PM UTC 24 Sep 04 03:38:54 PM UTC 24 292585418 ps
T132 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_executable.1390854272 Sep 04 03:32:24 PM UTC 24 Sep 04 03:38:58 PM UTC 24 15772406890 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.3080552475 Sep 04 03:37:46 PM UTC 24 Sep 04 03:39:03 PM UTC 24 531050050 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.1673927098 Sep 04 03:31:33 PM UTC 24 Sep 04 03:39:06 PM UTC 24 30401438479 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.3424674050 Sep 04 03:35:11 PM UTC 24 Sep 04 03:39:10 PM UTC 24 11336923957 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.1072661631 Sep 04 03:31:15 PM UTC 24 Sep 04 03:39:47 PM UTC 24 42302841723 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.2850558798 Sep 04 03:39:28 PM UTC 24 Sep 04 03:39:49 PM UTC 24 83069808 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.3756093356 Sep 04 03:39:48 PM UTC 24 Sep 04 03:39:55 PM UTC 24 4761451960 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.2226795000 Sep 04 03:34:47 PM UTC 24 Sep 04 03:40:05 PM UTC 24 5656355704 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.1331707188 Sep 04 03:40:06 PM UTC 24 Sep 04 03:40:08 PM UTC 24 79645315 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_bijection.3503670572 Sep 04 03:38:59 PM UTC 24 Sep 04 03:40:16 PM UTC 24 4792577957 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.2788438621 Sep 04 03:33:47 PM UTC 24 Sep 04 03:40:18 PM UTC 24 1820491169 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.1192198112 Sep 04 03:40:09 PM UTC 24 Sep 04 03:40:21 PM UTC 24 1566332644 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.63008277 Sep 04 03:39:14 PM UTC 24 Sep 04 03:40:24 PM UTC 24 130282290 ps
T134 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_executable.113552389 Sep 04 03:39:57 PM UTC 24 Sep 04 03:40:24 PM UTC 24 2219456992 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access.2448258874 Sep 04 03:39:07 PM UTC 24 Sep 04 03:40:25 PM UTC 24 1252960170 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_alert_test.1281966215 Sep 04 03:40:24 PM UTC 24 Sep 04 03:40:26 PM UTC 24 44415815 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.3212770279 Sep 04 03:40:17 PM UTC 24 Sep 04 03:40:26 PM UTC 24 753102668 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.1483437078 Sep 04 03:32:15 PM UTC 24 Sep 04 03:40:30 PM UTC 24 3238824052 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.3189486165 Sep 04 03:40:31 PM UTC 24 Sep 04 03:40:35 PM UTC 24 189905274 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.2544356243 Sep 04 03:40:25 PM UTC 24 Sep 04 03:40:39 PM UTC 24 987780500 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.3272195677 Sep 04 03:40:40 PM UTC 24 Sep 04 03:40:45 PM UTC 24 659777022 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_executable.1202950993 Sep 04 03:35:29 PM UTC 24 Sep 04 03:40:55 PM UTC 24 8911960040 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.2240422827 Sep 04 03:40:46 PM UTC 24 Sep 04 03:40:55 PM UTC 24 236052663 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.4043036174 Sep 04 03:40:27 PM UTC 24 Sep 04 03:40:55 PM UTC 24 15269484462 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.3895145418 Sep 04 03:40:56 PM UTC 24 Sep 04 03:40:59 PM UTC 24 84942945 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.2444674013 Sep 04 03:40:59 PM UTC 24 Sep 04 03:41:02 PM UTC 24 82823457 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.3634984706 Sep 04 03:33:29 PM UTC 24 Sep 04 03:41:08 PM UTC 24 15422065917 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.900033015 Sep 04 03:41:03 PM UTC 24 Sep 04 03:41:11 PM UTC 24 584310937 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.755549436 Sep 04 03:41:09 PM UTC 24 Sep 04 03:41:16 PM UTC 24 235258531 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.166583984 Sep 04 03:41:16 PM UTC 24 Sep 04 03:41:18 PM UTC 24 40480227 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.2027119724 Sep 04 03:31:15 PM UTC 24 Sep 04 03:41:26 PM UTC 24 7850762143 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.1554417029 Sep 04 03:41:19 PM UTC 24 Sep 04 03:41:39 PM UTC 24 2893778775 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.2553981967 Sep 04 03:36:30 PM UTC 24 Sep 04 03:41:52 PM UTC 24 13083488488 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.2121143465 Sep 04 03:41:53 PM UTC 24 Sep 04 03:41:57 PM UTC 24 98510676 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.1236412592 Sep 04 03:31:44 PM UTC 24 Sep 04 03:42:02 PM UTC 24 22379886311 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.3330954383 Sep 04 03:42:03 PM UTC 24 Sep 04 03:42:08 PM UTC 24 44657767 ps
T133 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_executable.1148353616 Sep 04 03:31:17 PM UTC 24 Sep 04 03:42:24 PM UTC 24 9772684157 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.832407544 Sep 04 03:42:25 PM UTC 24 Sep 04 03:42:37 PM UTC 24 585049063 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3195068623 Sep 04 03:38:41 PM UTC 24 Sep 04 03:42:38 PM UTC 24 952697534 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.1359802041 Sep 04 03:39:04 PM UTC 24 Sep 04 03:42:54 PM UTC 24 15691681465 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.3761780799 Sep 04 03:42:55 PM UTC 24 Sep 04 03:42:57 PM UTC 24 88385039 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.1747086761 Sep 04 03:41:32 PM UTC 24 Sep 04 03:43:07 PM UTC 24 6152231375 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.3687355564 Sep 04 03:42:39 PM UTC 24 Sep 04 03:43:10 PM UTC 24 3012175772 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.357592817 Sep 04 03:35:27 PM UTC 24 Sep 04 03:43:14 PM UTC 24 8873948436 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3885172975 Sep 04 03:42:58 PM UTC 24 Sep 04 03:43:14 PM UTC 24 2355746661 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.952592684 Sep 04 03:43:08 PM UTC 24 Sep 04 03:43:17 PM UTC 24 95919180 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.573523209 Sep 04 03:43:15 PM UTC 24 Sep 04 03:43:17 PM UTC 24 60082419 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.2893998706 Sep 04 03:41:27 PM UTC 24 Sep 04 03:43:19 PM UTC 24 1036971932 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.1350742875 Sep 04 03:42:08 PM UTC 24 Sep 04 03:43:28 PM UTC 24 151140093 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.835317291 Sep 04 03:43:18 PM UTC 24 Sep 04 03:43:31 PM UTC 24 561367229 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3294961932 Sep 04 03:43:11 PM UTC 24 Sep 04 03:43:33 PM UTC 24 417606768 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.742963595 Sep 04 03:43:21 PM UTC 24 Sep 04 03:43:40 PM UTC 24 953590218 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.3112537228 Sep 04 03:43:43 PM UTC 24 Sep 04 03:43:46 PM UTC 24 185407774 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.214743990 Sep 04 03:37:30 PM UTC 24 Sep 04 03:43:46 PM UTC 24 11001974658 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.1297242912 Sep 04 03:43:34 PM UTC 24 Sep 04 03:43:47 PM UTC 24 76070296 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.1119075826 Sep 04 03:43:43 PM UTC 24 Sep 04 03:43:48 PM UTC 24 291866711 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.4010956509 Sep 04 03:43:48 PM UTC 24 Sep 04 03:43:50 PM UTC 24 116001035 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.247958707 Sep 04 03:43:51 PM UTC 24 Sep 04 03:44:02 PM UTC 24 1341241540 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.1497484502 Sep 04 03:44:03 PM UTC 24 Sep 04 03:44:07 PM UTC 24 342167905 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.2413150412 Sep 04 03:37:34 PM UTC 24 Sep 04 03:44:19 PM UTC 24 17484885793 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.2884218999 Sep 04 03:44:40 PM UTC 24 Sep 04 03:44:42 PM UTC 24 48589227 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.1253139933 Sep 04 03:41:41 PM UTC 24 Sep 04 03:44:47 PM UTC 24 2058068609 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_regwen.951456694 Sep 04 03:35:41 PM UTC 24 Sep 04 03:45:06 PM UTC 24 5779064927 ps
T131 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all.3551735302 Sep 04 03:36:17 PM UTC 24 Sep 04 03:45:07 PM UTC 24 31995206080 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_smoke.2007027028 Sep 04 03:44:43 PM UTC 24 Sep 04 03:45:08 PM UTC 24 2965921442 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.195810168 Sep 04 03:43:29 PM UTC 24 Sep 04 03:45:16 PM UTC 24 236024825 ps
T212 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.741851370 Sep 04 03:40:28 PM UTC 24 Sep 04 03:45:20 PM UTC 24 50598430134 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.3030742498 Sep 04 03:45:20 PM UTC 24 Sep 04 03:45:29 PM UTC 24 367385718 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access.1104763421 Sep 04 03:45:09 PM UTC 24 Sep 04 03:45:33 PM UTC 24 609928595 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.3639803212 Sep 04 03:36:27 PM UTC 24 Sep 04 03:45:37 PM UTC 24 1580933045 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.1742845309 Sep 04 03:45:34 PM UTC 24 Sep 04 03:45:39 PM UTC 24 140172472 ps
T217 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.157177756 Sep 04 03:45:29 PM UTC 24 Sep 04 03:45:40 PM UTC 24 66280730 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_bijection.3376976724 Sep 04 03:45:07 PM UTC 24 Sep 04 03:45:57 PM UTC 24 6306541649 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.1920707689 Sep 04 03:45:58 PM UTC 24 Sep 04 03:46:00 PM UTC 24 80420945 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.3252630017 Sep 04 03:46:01 PM UTC 24 Sep 04 03:46:13 PM UTC 24 2788243147 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.1854969493 Sep 04 03:37:20 PM UTC 24 Sep 04 03:46:14 PM UTC 24 5646215595 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_alert_test.4004931191 Sep 04 03:46:19 PM UTC 24 Sep 04 03:46:21 PM UTC 24 110933292 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.1360004449 Sep 04 03:46:14 PM UTC 24 Sep 04 03:46:23 PM UTC 24 628509036 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1742345341 Sep 04 03:46:19 PM UTC 24 Sep 04 03:46:29 PM UTC 24 940062506 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3883721882 Sep 04 03:44:09 PM UTC 24 Sep 04 03:46:32 PM UTC 24 5093865470 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_smoke.562654788 Sep 04 03:46:22 PM UTC 24 Sep 04 03:46:33 PM UTC 24 372200130 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.1480080700 Sep 04 03:31:16 PM UTC 24 Sep 04 03:46:34 PM UTC 24 3231560581 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access.2951031078 Sep 04 03:46:34 PM UTC 24 Sep 04 03:46:50 PM UTC 24 451221185 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.680048193 Sep 04 03:46:51 PM UTC 24 Sep 04 03:46:55 PM UTC 24 45886899 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.2481145256 Sep 04 03:39:11 PM UTC 24 Sep 04 03:47:02 PM UTC 24 58386893358 ps
T135 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_regwen.1879534430 Sep 04 03:32:24 PM UTC 24 Sep 04 03:47:05 PM UTC 24 21965950074 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.4290401535 Sep 04 03:47:03 PM UTC 24 Sep 04 03:47:11 PM UTC 24 872664393 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_bijection.2483202012 Sep 04 03:46:30 PM UTC 24 Sep 04 03:47:23 PM UTC 24 717607547 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.3848795424 Sep 04 03:47:41 PM UTC 24 Sep 04 03:47:44 PM UTC 24 47725946 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.207940993 Sep 04 03:45:08 PM UTC 24 Sep 04 03:47:47 PM UTC 24 1491647444 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.3733817529 Sep 04 03:47:46 PM UTC 24 Sep 04 03:47:51 PM UTC 24 375395622 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.3993791314 Sep 04 03:46:56 PM UTC 24 Sep 04 03:47:53 PM UTC 24 138511565 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_alert_test.3476645913 Sep 04 03:47:54 PM UTC 24 Sep 04 03:47:56 PM UTC 24 33160068 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.2985119859 Sep 04 03:47:46 PM UTC 24 Sep 04 03:47:58 PM UTC 24 521687618 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all.3795307329 Sep 04 03:46:19 PM UTC 24 Sep 04 03:48:01 PM UTC 24 3476903236 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.1067643305 Sep 04 03:40:36 PM UTC 24 Sep 04 03:48:02 PM UTC 24 14034418656 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_smoke.1556618468 Sep 04 03:47:57 PM UTC 24 Sep 04 03:48:12 PM UTC 24 527681480 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all.1231255914 Sep 04 03:37:08 PM UTC 24 Sep 04 03:48:29 PM UTC 24 53341306870 ps
T138 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_executable.1870311442 Sep 04 03:33:48 PM UTC 24 Sep 04 03:48:39 PM UTC 24 2985693677 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.7446695 Sep 04 03:43:46 PM UTC 24 Sep 04 03:48:44 PM UTC 24 1972172399 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.2264272116 Sep 04 03:43:32 PM UTC 24 Sep 04 03:48:53 PM UTC 24 3897773701 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.1178735889 Sep 04 03:37:57 PM UTC 24 Sep 04 03:48:54 PM UTC 24 13773899721 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.84043327 Sep 04 03:48:54 PM UTC 24 Sep 04 03:48:58 PM UTC 24 927795894 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.1069697056 Sep 04 03:36:45 PM UTC 24 Sep 04 03:49:05 PM UTC 24 3198472229 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_bijection.479818960 Sep 04 03:48:01 PM UTC 24 Sep 04 03:49:08 PM UTC 24 931514943 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.2590523924 Sep 04 03:49:09 PM UTC 24 Sep 04 03:49:11 PM UTC 24 81785807 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.623515440 Sep 04 03:49:12 PM UTC 24 Sep 04 03:49:25 PM UTC 24 147325387 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.2700257749 Sep 04 03:49:26 PM UTC 24 Sep 04 03:49:35 PM UTC 24 155915111 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_regwen.3513084474 Sep 04 03:39:58 PM UTC 24 Sep 04 03:49:41 PM UTC 24 1286556414 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.3444621482 Sep 04 03:36:39 PM UTC 24 Sep 04 03:49:44 PM UTC 24 176550153994 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.3216741831 Sep 04 03:48:45 PM UTC 24 Sep 04 03:49:44 PM UTC 24 168493908 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_alert_test.4023476279 Sep 04 03:49:44 PM UTC 24 Sep 04 03:49:46 PM UTC 24 43031089 ps
T251 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.3353836878 Sep 04 03:48:40 PM UTC 24 Sep 04 03:50:00 PM UTC 24 499701111 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access.1963941657 Sep 04 03:48:13 PM UTC 24 Sep 04 03:50:09 PM UTC 24 454999944 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3307452551 Sep 04 03:40:19 PM UTC 24 Sep 04 03:50:23 PM UTC 24 3612567276 ps
T136 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_regwen.1917329050 Sep 04 03:38:04 PM UTC 24 Sep 04 03:50:28 PM UTC 24 10828488715 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.1164201776 Sep 04 03:46:35 PM UTC 24 Sep 04 03:50:38 PM UTC 24 7272482240 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.1396176217 Sep 04 03:42:38 PM UTC 24 Sep 04 03:50:41 PM UTC 24 29071233866 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.3108014346 Sep 04 03:43:27 PM UTC 24 Sep 04 03:50:41 PM UTC 24 3496241621 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.2457231529 Sep 04 03:50:41 PM UTC 24 Sep 04 03:50:46 PM UTC 24 204884358 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access.3726526481 Sep 04 03:50:24 PM UTC 24 Sep 04 03:50:54 PM UTC 24 2750708420 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_regwen.3443206165 Sep 04 03:36:53 PM UTC 24 Sep 04 03:51:12 PM UTC 24 9638403533 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.1123458686 Sep 04 03:51:22 PM UTC 24 Sep 04 03:51:24 PM UTC 24 89033644 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_smoke.3663655260 Sep 04 03:49:45 PM UTC 24 Sep 04 03:51:27 PM UTC 24 143477975 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.2269836711 Sep 04 03:51:27 PM UTC 24 Sep 04 03:51:33 PM UTC 24 572095416 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.3832072873 Sep 04 03:51:25 PM UTC 24 Sep 04 03:51:41 PM UTC 24 467320259 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1222760624 Sep 04 03:51:34 PM UTC 24 Sep 04 03:51:44 PM UTC 24 177555137 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_alert_test.3668473423 Sep 04 03:51:44 PM UTC 24 Sep 04 03:51:46 PM UTC 24 145252206 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_bijection.967804113 Sep 04 03:50:01 PM UTC 24 Sep 04 03:51:47 PM UTC 24 21690917340 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_regwen.4288258846 Sep 04 03:45:41 PM UTC 24 Sep 04 03:51:53 PM UTC 24 6251491527 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.615777270 Sep 04 03:50:41 PM UTC 24 Sep 04 03:51:56 PM UTC 24 855293716 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_smoke.204946597 Sep 04 03:51:48 PM UTC 24 Sep 04 03:51:57 PM UTC 24 708039266 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1593326202 Sep 04 03:49:36 PM UTC 24 Sep 04 03:52:01 PM UTC 24 615851452 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.825392540 Sep 04 03:50:39 PM UTC 24 Sep 04 03:52:22 PM UTC 24 586488696 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access.1495078475 Sep 04 03:51:58 PM UTC 24 Sep 04 03:52:23 PM UTC 24 3785501735 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.1086783066 Sep 04 03:52:25 PM UTC 24 Sep 04 03:52:34 PM UTC 24 1262565222 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.548176229 Sep 04 03:47:48 PM UTC 24 Sep 04 03:52:52 PM UTC 24 3501567866 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_executable.1091839646 Sep 04 03:36:48 PM UTC 24 Sep 04 03:52:54 PM UTC 24 31320076997 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.2486458435 Sep 04 03:41:58 PM UTC 24 Sep 04 03:52:54 PM UTC 24 24345968023 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.2046884518 Sep 04 03:52:55 PM UTC 24 Sep 04 03:52:57 PM UTC 24 30196614 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.3162839027 Sep 04 03:46:33 PM UTC 24 Sep 04 03:52:58 PM UTC 24 6196267892 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.2395588751 Sep 04 03:52:23 PM UTC 24 Sep 04 03:53:00 PM UTC 24 415157874 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.2375949238 Sep 04 03:52:58 PM UTC 24 Sep 04 03:53:04 PM UTC 24 66726063 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_regwen.2793806417 Sep 04 03:51:13 PM UTC 24 Sep 04 03:53:05 PM UTC 24 1220410490 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.950547531 Sep 04 03:52:56 PM UTC 24 Sep 04 03:53:07 PM UTC 24 136500410 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_alert_test.3462682543 Sep 04 03:53:05 PM UTC 24 Sep 04 03:53:07 PM UTC 24 29592581 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_smoke.2346317374 Sep 04 03:53:06 PM UTC 24 Sep 04 03:53:09 PM UTC 24 141637663 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.4011618200 Sep 04 03:40:26 PM UTC 24 Sep 04 03:53:15 PM UTC 24 47209758254 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.4161092383 Sep 04 03:42:28 PM UTC 24 Sep 04 03:53:26 PM UTC 24 3525361978 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.1540268181 Sep 04 03:53:27 PM UTC 24 Sep 04 03:53:30 PM UTC 24 121719100 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.2202497516 Sep 04 03:50:10 PM UTC 24 Sep 04 03:53:34 PM UTC 24 1631731460 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.4084236883 Sep 04 03:43:48 PM UTC 24 Sep 04 03:53:36 PM UTC 24 1521308965 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.839745525 Sep 04 03:53:35 PM UTC 24 Sep 04 03:53:48 PM UTC 24 504274978 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_bijection.2965792916 Sep 04 03:53:08 PM UTC 24 Sep 04 03:54:03 PM UTC 24 2880177565 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.4036826919 Sep 04 03:52:22 PM UTC 24 Sep 04 03:53:54 PM UTC 24 155118600 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.1059651451 Sep 04 03:54:04 PM UTC 24 Sep 04 03:54:06 PM UTC 24 29556690 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_bijection.536268867 Sep 04 03:51:55 PM UTC 24 Sep 04 03:54:10 PM UTC 24 55278108829 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.1347500201 Sep 04 03:54:07 PM UTC 24 Sep 04 03:54:14 PM UTC 24 296304430 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.1361419641 Sep 04 03:48:03 PM UTC 24 Sep 04 03:54:15 PM UTC 24 6333676098 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.3891358925 Sep 04 03:54:11 PM UTC 24 Sep 04 03:54:20 PM UTC 24 88998663 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access.2614088817 Sep 04 03:53:10 PM UTC 24 Sep 04 03:54:22 PM UTC 24 3421316104 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_alert_test.936713076 Sep 04 03:54:20 PM UTC 24 Sep 04 03:54:22 PM UTC 24 45061827 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.555326173 Sep 04 03:44:48 PM UTC 24 Sep 04 03:54:27 PM UTC 24 41953646458 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.3167866030 Sep 04 03:53:30 PM UTC 24 Sep 04 03:54:29 PM UTC 24 135439017 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.627902209 Sep 04 03:45:16 PM UTC 24 Sep 04 03:54:29 PM UTC 24 74024467550 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_smoke.3354160765 Sep 04 03:54:24 PM UTC 24 Sep 04 03:54:36 PM UTC 24 1295727117 ps
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T300 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_executable.2872443656 Sep 04 03:48:58 PM UTC 24 Sep 04 03:55:15 PM UTC 24 38663703497 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.1357702934 Sep 04 03:55:05 PM UTC 24 Sep 04 03:55:18 PM UTC 24 647391661 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.3797897409 Sep 04 03:54:42 PM UTC 24 Sep 04 03:55:19 PM UTC 24 105517634 ps
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T304 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.2024729568 Sep 04 03:55:24 PM UTC 24 Sep 04 03:55:26 PM UTC 24 77151061 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2117724617 Sep 04 03:52:59 PM UTC 24 Sep 04 03:55:27 PM UTC 24 7200184878 ps
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