Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	151312758	1			T2	1220		T3	1530		T4	4542
instr_valid_dis	115966547	1			T2	1220		T3	1530		T4	4542
instr_en	27605750	1			T22	19822		T24	23642		T17	19890

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	12065416	1			T54	18156		T36	420		T135	54992
sram_ifetch_valid_disable	115915727	1			T2	1220		T3	1530		T4	4542
sram_ifetch_enable	23331615	1			T24	23642		T54	11728		T17	63944

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	151312758	1			T2	1220		T3	1530		T4	4542
hw_debug_en_valid_off	116230497	1			T2	1220		T3	1530		T4	4542
hw_debug_en_on	24137028	1			T54	3684		T135	40098		T141	742

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	115915727	1			T2	1220		T3	1530		T4	4542
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	101209188	1			T2	1220		T3	1530		T4	4542
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	11443043	1			T22	19822		T53	3198		T141	5922
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4948618	1			T36	420		T135	34992		T18	6700
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1929790	1			T135	34992		T142	16036		T19	19378
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2162472	1			T36	420		T142	13000		T139	16682
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4779400	1			T135	20000		T141	742		T142	36442
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1994132	1			T135	20000		T141	742		T144	78004
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2203466	1			T142	36442		T137	82		T145	25472
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9634068	1			T54	3684		T135	20098		T18	3632
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3340019	1			T54	3684		T135	20098		T18	3632
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4834959	1			T142	90		T139	66168		T137	18110

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10832807	1			T24	23642		T17	19890		T53	2100
lc_exec_en	9723560	1			T18	9012		T139	14410		T137	40954
valid_exec_dis	112162680	1			T2	1220		T3	1530		T4	4542
invalid_exec_dis	35397031	1			T24	23642		T54	29884		T17	63944