Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44


Total tests in report: 1026
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
71.97 71.97 94.24 94.24 70.26 70.26 55.34 55.34 85.71 85.71 83.57 83.57 94.40 94.40 20.29 20.29 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.2148241517
85.06 13.08 97.12 2.88 75.00 4.74 93.93 38.59 100.00 14.29 90.10 6.52 94.84 0.44 44.42 24.13 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.1558489221
92.99 7.93 98.47 1.36 85.66 10.66 97.40 3.47 100.00 0.00 93.00 2.90 96.17 1.33 80.26 35.83 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.41212927
94.12 1.13 98.81 0.34 88.74 3.08 98.68 1.28 100.00 0.00 94.69 1.69 96.76 0.59 81.17 0.91 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.3002572004
94.85 0.73 98.81 0.00 89.10 0.36 98.68 0.00 100.00 0.00 94.69 0.00 96.76 0.00 85.92 4.75 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.578382188
95.46 0.61 98.81 0.00 89.45 0.36 98.68 0.00 100.00 0.00 94.93 0.24 96.76 0.00 89.58 3.66 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_regwen.1071175398
95.85 0.39 99.07 0.25 90.05 0.59 98.75 0.07 100.00 0.00 95.65 0.72 96.76 0.00 90.68 1.10 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_smoke.1687215393
96.13 0.28 99.07 0.00 90.17 0.12 98.75 0.00 100.00 0.00 95.65 0.00 96.76 0.00 92.50 1.83 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_regwen.2778608330
96.39 0.26 99.07 0.00 90.17 0.00 98.75 0.00 100.00 0.00 95.65 0.00 96.76 0.00 94.33 1.83 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.1478116643
96.64 0.25 99.07 0.00 90.40 0.24 98.75 0.00 100.00 0.00 95.65 0.00 98.08 1.33 94.52 0.18 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1775763447
96.78 0.14 99.07 0.00 90.52 0.12 98.75 0.00 100.00 0.00 96.14 0.48 98.08 0.00 94.88 0.37 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.841577836
96.91 0.13 99.15 0.08 90.52 0.00 99.58 0.83 100.00 0.00 96.14 0.00 98.08 0.00 94.88 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.1687253834
97.01 0.10 99.15 0.00 90.52 0.00 99.58 0.00 100.00 0.00 96.14 0.00 98.23 0.15 95.43 0.55 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.2641937328
97.09 0.09 99.15 0.00 90.88 0.36 99.65 0.07 100.00 0.00 96.14 0.00 98.23 0.00 95.61 0.18 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.202654064
97.17 0.08 99.15 0.00 90.88 0.00 99.65 0.00 100.00 0.00 96.14 0.00 98.23 0.00 96.16 0.55 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1594224705
97.23 0.06 99.15 0.00 90.88 0.00 99.72 0.07 100.00 0.00 96.14 0.00 98.38 0.15 96.34 0.18 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3282673067
97.28 0.05 99.15 0.00 90.88 0.00 99.72 0.00 100.00 0.00 96.14 0.00 98.38 0.00 96.71 0.37 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.628569893
97.33 0.05 99.15 0.00 90.88 0.00 99.72 0.00 100.00 0.00 96.14 0.00 98.53 0.15 96.89 0.18 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3318572390
97.37 0.04 99.15 0.00 90.88 0.00 99.72 0.00 100.00 0.00 96.14 0.00 98.82 0.29 96.89 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3385798521
97.41 0.04 99.15 0.00 91.00 0.12 99.72 0.00 100.00 0.00 96.14 0.00 98.97 0.15 96.89 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.3605890186
97.44 0.03 99.15 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.14 0.00 98.97 0.00 97.07 0.18 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3121083509
97.46 0.03 99.15 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.14 0.00 98.97 0.00 97.26 0.18 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.2603063453
97.49 0.03 99.15 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.14 0.00 98.97 0.00 97.44 0.18 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_executable.2400039510
97.51 0.02 99.15 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.14 0.00 99.12 0.15 97.44 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.4047369903

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.4011131533
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3025171134
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.405743780
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3771080170
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1716306756
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1601908654
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.496910488
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1066947305
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.4201775834
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2147711242
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2627590346
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3505249936
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3231666879
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2868146737
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.4246834885
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.676696747
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2856853576
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.480784910
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3937641327
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2983751432
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1709214355
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.513348669
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.887441607
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2114987436
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.4275788854
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3667014220
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2277383935
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2068634734
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2788654305
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1909243250
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3480173293
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3433331227
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.827736580
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.941411514
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3341608703
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1337086266
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2543995015
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1515794291
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.213704949
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.995981997
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1674600737
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.70324659
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2834917884
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.412487010
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.565552817
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.4096285204
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3744330987
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.823581477
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3360729590
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3969793356
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3998881038
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.357883179
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3650012847
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2393899285
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3441003432
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2000591216
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.851364230
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1943022557
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3616723720
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1377259260
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1857352280
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2254366961
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1527883357
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1726555958
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4268025885
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3811149029
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4067496075
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2533500673
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.4124850759
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3426705361
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2633991059
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.883652804
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2506689302
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2414886923
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.736508002
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1832234074
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2048310026
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2466554963
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2488080049
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1299564260
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1016505673
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.4154817081
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.640420078
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.393029372
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/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access.1136073962
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.859392777
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.1621729615
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_smoke.3235179266
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all.1336085888
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1616014695
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.1114705842
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.3600756137
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.3448221775
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.300616777
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.185938757
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.2888435516
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.24540069
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.4248490663
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.4253218211
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.2450176771
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.1664487000
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.302515045
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.451580525
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.3998981451
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.921728178
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.1382965388
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.3638840873
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.645329847
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.1342887638
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.60779966
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.3793766325
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.314547012
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.4268061715
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.1175961175
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.4251137596
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.2600746777
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.494025594
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3993857617
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.4132283460
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.118898088
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.2164985865
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.3040587805
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.1238104586
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.320247600
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all.1857400860
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3138655241
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.3696431993
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.3506164052
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.573784911
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.3993865637
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.77053247
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.1959803228
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.1805623759
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.3462537617
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.625949867
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.2854098147
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.1312980658
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.3480593497
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.3197091029
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3258516257
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.4108952521
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.4078398459
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.993601732
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.261414614
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.3873073081



Total test records in report: 1026
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.1687253834 Sep 09 09:10:23 PM UTC 24 Sep 09 09:10:25 PM UTC 24 180303963 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_smoke.2209821397 Sep 09 09:10:19 PM UTC 24 Sep 09 09:10:25 PM UTC 24 90476841 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.1092004785 Sep 09 09:10:21 PM UTC 24 Sep 09 09:10:26 PM UTC 24 88038016 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.1558489221 Sep 09 09:10:21 PM UTC 24 Sep 09 09:10:28 PM UTC 24 1335949875 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.2148241517 Sep 09 09:10:23 PM UTC 24 Sep 09 09:10:29 PM UTC 24 752857225 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.3788315624 Sep 09 09:10:23 PM UTC 24 Sep 09 09:10:30 PM UTC 24 763673596 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.3337937262 Sep 09 09:10:27 PM UTC 24 Sep 09 09:10:34 PM UTC 24 665418735 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.202654064 Sep 09 09:10:26 PM UTC 24 Sep 09 09:10:34 PM UTC 24 14267107 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.1052427550 Sep 09 09:10:31 PM UTC 24 Sep 09 09:10:34 PM UTC 24 34996997 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.2878247368 Sep 09 09:10:26 PM UTC 24 Sep 09 09:10:35 PM UTC 24 432080109 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.940405019 Sep 09 09:10:27 PM UTC 24 Sep 09 09:10:37 PM UTC 24 267735899 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.3605890186 Sep 09 09:10:29 PM UTC 24 Sep 09 09:10:39 PM UTC 24 1283272257 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.3785724838 Sep 09 09:10:37 PM UTC 24 Sep 09 09:10:40 PM UTC 24 104577302 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.319085447 Sep 09 09:10:31 PM UTC 24 Sep 09 09:10:40 PM UTC 24 334525689 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_alert_test.2110107342 Sep 09 09:10:36 PM UTC 24 Sep 09 09:10:41 PM UTC 24 44436189 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_alert_test.3311357645 Sep 09 09:10:40 PM UTC 24 Sep 09 09:10:42 PM UTC 24 65869507 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.3545050505 Sep 09 09:10:34 PM UTC 24 Sep 09 09:10:42 PM UTC 24 42157889 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access.2986180222 Sep 09 09:10:20 PM UTC 24 Sep 09 09:10:43 PM UTC 24 289095024 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.3175299739 Sep 09 09:10:36 PM UTC 24 Sep 09 09:10:44 PM UTC 24 333999169 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.3261758678 Sep 09 09:10:38 PM UTC 24 Sep 09 09:10:45 PM UTC 24 93577862 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.3583095074 Sep 09 09:10:37 PM UTC 24 Sep 09 09:10:46 PM UTC 24 2273162054 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.3002572004 Sep 09 09:10:40 PM UTC 24 Sep 09 09:10:46 PM UTC 24 288113328 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access.2238566811 Sep 09 09:10:36 PM UTC 24 Sep 09 09:10:47 PM UTC 24 279985643 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.298775725 Sep 09 09:10:38 PM UTC 24 Sep 09 09:10:47 PM UTC 24 138038821 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.3760682196 Sep 09 09:10:44 PM UTC 24 Sep 09 09:10:47 PM UTC 24 305149403 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access.614406105 Sep 09 09:10:27 PM UTC 24 Sep 09 09:10:49 PM UTC 24 2480884591 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.1079560564 Sep 09 09:10:47 PM UTC 24 Sep 09 09:10:49 PM UTC 24 45953582 ps
T134 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_alert_test.47574410 Sep 09 09:10:50 PM UTC 24 Sep 09 09:10:52 PM UTC 24 13222181 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.479821963 Sep 09 09:10:49 PM UTC 24 Sep 09 09:10:53 PM UTC 24 249698971 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.1830646854 Sep 09 09:10:48 PM UTC 24 Sep 09 09:10:54 PM UTC 24 62384094 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.2095965203 Sep 09 09:10:47 PM UTC 24 Sep 09 09:10:55 PM UTC 24 286754529 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access.2802364510 Sep 09 09:10:43 PM UTC 24 Sep 09 09:10:57 PM UTC 24 315401125 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_bijection.3785620898 Sep 09 09:10:36 PM UTC 24 Sep 09 09:10:58 PM UTC 24 762821805 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.2486585474 Sep 09 09:10:43 PM UTC 24 Sep 09 09:11:01 PM UTC 24 159629369 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.3868587788 Sep 09 09:10:37 PM UTC 24 Sep 09 09:11:03 PM UTC 24 180737317 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_smoke.2340072786 Sep 09 09:10:26 PM UTC 24 Sep 09 09:11:05 PM UTC 24 314411723 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.2267499285 Sep 09 09:11:03 PM UTC 24 Sep 09 09:11:06 PM UTC 24 68737781 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access.2121088413 Sep 09 09:10:57 PM UTC 24 Sep 09 09:11:06 PM UTC 24 1083301782 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.4158933013 Sep 09 09:10:37 PM UTC 24 Sep 09 09:11:06 PM UTC 24 379430869 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_bijection.600035732 Sep 09 09:10:20 PM UTC 24 Sep 09 09:11:11 PM UTC 24 1471322065 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.1987961467 Sep 09 09:11:06 PM UTC 24 Sep 09 09:11:14 PM UTC 24 410004169 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.596300728 Sep 09 09:11:12 PM UTC 24 Sep 09 09:11:14 PM UTC 24 29687393 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_smoke.1687215393 Sep 09 09:10:36 PM UTC 24 Sep 09 09:11:16 PM UTC 24 1048113351 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.841577836 Sep 09 09:10:24 PM UTC 24 Sep 09 09:11:18 PM UTC 24 2781750487 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.3593086463 Sep 09 09:11:15 PM UTC 24 Sep 09 09:11:20 PM UTC 24 329295009 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.2727333033 Sep 09 09:11:20 PM UTC 24 Sep 09 09:11:24 PM UTC 24 630106812 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_smoke.3015655161 Sep 09 09:10:41 PM UTC 24 Sep 09 09:11:25 PM UTC 24 462849360 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_bijection.3481390231 Sep 09 09:10:42 PM UTC 24 Sep 09 09:11:25 PM UTC 24 6389397087 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.1284661351 Sep 09 09:11:15 PM UTC 24 Sep 09 09:11:25 PM UTC 24 932828027 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_alert_test.636387911 Sep 09 09:11:26 PM UTC 24 Sep 09 09:11:28 PM UTC 24 20952605 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.2603063453 Sep 09 09:10:21 PM UTC 24 Sep 09 09:11:28 PM UTC 24 245904388 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_smoke.3981941544 Sep 09 09:11:26 PM UTC 24 Sep 09 09:11:29 PM UTC 24 87637244 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.2993900907 Sep 09 09:11:04 PM UTC 24 Sep 09 09:11:36 PM UTC 24 236642528 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_bijection.31719165 Sep 09 09:10:54 PM UTC 24 Sep 09 09:11:39 PM UTC 24 1814389200 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_bijection.3899411072 Sep 09 09:10:26 PM UTC 24 Sep 09 09:11:43 PM UTC 24 1019919522 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.1059285046 Sep 09 09:11:43 PM UTC 24 Sep 09 09:11:51 PM UTC 24 1552566068 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access.2044062702 Sep 09 09:11:29 PM UTC 24 Sep 09 09:11:54 PM UTC 24 1160835621 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_smoke.634252403 Sep 09 09:10:53 PM UTC 24 Sep 09 09:12:03 PM UTC 24 596492269 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.1189573496 Sep 09 09:11:40 PM UTC 24 Sep 09 09:12:20 PM UTC 24 113911037 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.1454686611 Sep 09 09:12:21 PM UTC 24 Sep 09 09:12:23 PM UTC 24 44650919 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.2101813107 Sep 09 09:10:44 PM UTC 24 Sep 09 09:12:33 PM UTC 24 150976457 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.1757834211 Sep 09 09:12:24 PM UTC 24 Sep 09 09:12:34 PM UTC 24 899406199 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.2604970390 Sep 09 09:12:29 PM UTC 24 Sep 09 09:12:35 PM UTC 24 98910249 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_alert_test.419036092 Sep 09 09:12:36 PM UTC 24 Sep 09 09:12:38 PM UTC 24 42105345 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.2641937328 Sep 09 09:10:20 PM UTC 24 Sep 09 09:12:41 PM UTC 24 1422988467 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.1523693010 Sep 09 09:11:36 PM UTC 24 Sep 09 09:12:50 PM UTC 24 247646052 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_bijection.1486887568 Sep 09 09:11:27 PM UTC 24 Sep 09 09:12:55 PM UTC 24 17164339543 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.30144720 Sep 09 09:10:48 PM UTC 24 Sep 09 09:12:58 PM UTC 24 8082723407 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_smoke.3235179266 Sep 09 09:12:39 PM UTC 24 Sep 09 09:12:59 PM UTC 24 984249873 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.41212927 Sep 09 09:10:38 PM UTC 24 Sep 09 09:13:20 PM UTC 24 5400873933 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access.1136073962 Sep 09 09:12:56 PM UTC 24 Sep 09 09:13:25 PM UTC 24 4726653680 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_bijection.3135491504 Sep 09 09:12:51 PM UTC 24 Sep 09 09:13:27 PM UTC 24 6059567152 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_executable.1339178499 Sep 09 09:10:44 PM UTC 24 Sep 09 09:13:34 PM UTC 24 4709743945 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.1674122976 Sep 09 09:13:26 PM UTC 24 Sep 09 09:13:39 PM UTC 24 696630591 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.4146288596 Sep 09 09:11:53 PM UTC 24 Sep 09 09:13:41 PM UTC 24 1724514754 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.1621729615 Sep 09 09:13:40 PM UTC 24 Sep 09 09:13:43 PM UTC 24 29092043 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_regwen.2002990910 Sep 09 09:11:07 PM UTC 24 Sep 09 09:13:50 PM UTC 24 983189229 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.1551208010 Sep 09 09:13:41 PM UTC 24 Sep 09 09:13:53 PM UTC 24 261575179 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.3892754558 Sep 09 09:13:44 PM UTC 24 Sep 09 09:13:53 PM UTC 24 765742589 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_alert_test.2154648964 Sep 09 09:13:54 PM UTC 24 Sep 09 09:13:56 PM UTC 24 21752938 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.2606281646 Sep 09 09:10:26 PM UTC 24 Sep 09 09:14:05 PM UTC 24 2042746983 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.1382965388 Sep 09 09:13:57 PM UTC 24 Sep 09 09:14:12 PM UTC 24 3918563976 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.1208757771 Sep 09 09:13:00 PM UTC 24 Sep 09 09:14:18 PM UTC 24 135835310 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.3600756137 Sep 09 09:13:21 PM UTC 24 Sep 09 09:14:34 PM UTC 24 483348723 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all.1999725843 Sep 09 09:12:35 PM UTC 24 Sep 09 09:14:34 PM UTC 24 9703291190 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.302515045 Sep 09 09:14:35 PM UTC 24 Sep 09 09:14:40 PM UTC 24 51533377 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.3827696189 Sep 09 09:10:36 PM UTC 24 Sep 09 09:14:45 PM UTC 24 7160708049 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.4248490663 Sep 09 09:14:40 PM UTC 24 Sep 09 09:14:48 PM UTC 24 185008326 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.24540069 Sep 09 09:14:49 PM UTC 24 Sep 09 09:14:53 PM UTC 24 403635339 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.185938757 Sep 09 09:14:13 PM UTC 24 Sep 09 09:15:02 PM UTC 24 1619802208 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2366680536 Sep 09 09:12:34 PM UTC 24 Sep 09 09:15:26 PM UTC 24 10562107183 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.60779966 Sep 09 09:14:46 PM UTC 24 Sep 09 09:15:29 PM UTC 24 110063896 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.3998981451 Sep 09 09:15:30 PM UTC 24 Sep 09 09:15:32 PM UTC 24 28305599 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.2450176771 Sep 09 09:15:33 PM UTC 24 Sep 09 09:15:43 PM UTC 24 516383255 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.1114705842 Sep 09 09:12:55 PM UTC 24 Sep 09 09:15:45 PM UTC 24 6437123277 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.4253218211 Sep 09 09:15:43 PM UTC 24 Sep 09 09:15:51 PM UTC 24 174625845 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.1842910800 Sep 09 09:10:55 PM UTC 24 Sep 09 09:15:52 PM UTC 24 2673259650 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.300616777 Sep 09 09:15:54 PM UTC 24 Sep 09 09:15:55 PM UTC 24 38730315 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.320247600 Sep 09 09:15:55 PM UTC 24 Sep 09 09:15:57 PM UTC 24 23012495 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1616014695 Sep 09 09:13:51 PM UTC 24 Sep 09 09:15:58 PM UTC 24 245770190 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.1795157371 Sep 09 09:10:54 PM UTC 24 Sep 09 09:16:10 PM UTC 24 9252773678 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.3371773755 Sep 09 09:10:42 PM UTC 24 Sep 09 09:16:11 PM UTC 24 55275922096 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.492496625 Sep 09 09:11:29 PM UTC 24 Sep 09 09:16:12 PM UTC 24 9516946915 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.118898088 Sep 09 09:16:11 PM UTC 24 Sep 09 09:16:15 PM UTC 24 86504160 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.2600746777 Sep 09 09:16:13 PM UTC 24 Sep 09 09:16:20 PM UTC 24 194879052 ps
T135 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_regwen.1071175398 Sep 09 09:13:35 PM UTC 24 Sep 09 09:16:29 PM UTC 24 4817869558 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.4251137596 Sep 09 09:16:21 PM UTC 24 Sep 09 09:16:34 PM UTC 24 824937486 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.2866180426 Sep 09 09:10:21 PM UTC 24 Sep 09 09:16:40 PM UTC 24 10791973148 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.1175961175 Sep 09 09:16:35 PM UTC 24 Sep 09 09:16:44 PM UTC 24 2452279676 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.1478116643 Sep 09 09:10:43 PM UTC 24 Sep 09 09:16:45 PM UTC 24 25843850787 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.4268061715 Sep 09 09:15:58 PM UTC 24 Sep 09 09:16:46 PM UTC 24 6678250335 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.3040587805 Sep 09 09:16:45 PM UTC 24 Sep 09 09:16:47 PM UTC 24 28371305 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.494025594 Sep 09 09:16:47 PM UTC 24 Sep 09 09:16:51 PM UTC 24 161158950 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.314547012 Sep 09 09:16:55 PM UTC 24 Sep 09 09:16:57 PM UTC 24 22241145 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3993857617 Sep 09 09:16:46 PM UTC 24 Sep 09 09:16:59 PM UTC 24 277995916 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.3506164052 Sep 09 09:16:15 PM UTC 24 Sep 09 09:17:00 PM UTC 24 480332347 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.3853609360 Sep 09 09:10:37 PM UTC 24 Sep 09 09:17:03 PM UTC 24 7606552683 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.4078398459 Sep 09 09:16:58 PM UTC 24 Sep 09 09:17:11 PM UTC 24 794072499 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.3480593497 Sep 09 09:17:12 PM UTC 24 Sep 09 09:17:22 PM UTC 24 1043290798 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.2162942139 Sep 09 09:10:36 PM UTC 24 Sep 09 09:17:55 PM UTC 24 56689511761 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.1805460459 Sep 09 09:10:27 PM UTC 24 Sep 09 09:18:06 PM UTC 24 17489188306 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.77053247 Sep 09 09:17:00 PM UTC 24 Sep 09 09:18:16 PM UTC 24 3543629373 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.1805623759 Sep 09 09:18:17 PM UTC 24 Sep 09 09:18:20 PM UTC 24 120464075 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.3462537617 Sep 09 09:17:56 PM UTC 24 Sep 09 09:18:26 PM UTC 24 275672320 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.1894929295 Sep 09 09:12:42 PM UTC 24 Sep 09 09:18:41 PM UTC 24 6651049030 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.1655956275 Sep 09 09:11:07 PM UTC 24 Sep 09 09:18:42 PM UTC 24 24106228597 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.1664487000 Sep 09 09:14:05 PM UTC 24 Sep 09 09:18:43 PM UTC 24 64638119281 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3258516257 Sep 09 09:18:47 PM UTC 24 Sep 09 09:18:49 PM UTC 24 33614558 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.625949867 Sep 09 09:18:48 PM UTC 24 Sep 09 09:18:57 PM UTC 24 850141129 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.2854098147 Sep 09 09:18:47 PM UTC 24 Sep 09 09:18:57 PM UTC 24 709842757 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.3993865637 Sep 09 09:18:59 PM UTC 24 Sep 09 09:19:01 PM UTC 24 14268015 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3138655241 Sep 09 09:16:48 PM UTC 24 Sep 09 09:19:04 PM UTC 24 8633400809 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.1342887638 Sep 09 09:14:19 PM UTC 24 Sep 09 09:19:05 PM UTC 24 2185526486 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_smoke.3893397048 Sep 09 09:18:59 PM UTC 24 Sep 09 09:19:19 PM UTC 24 1222549656 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.3696431993 Sep 09 09:15:59 PM UTC 24 Sep 09 09:19:28 PM UTC 24 3943388946 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.1615950680 Sep 09 09:10:20 PM UTC 24 Sep 09 09:19:30 PM UTC 24 100101442551 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access.4236200780 Sep 09 09:19:06 PM UTC 24 Sep 09 09:19:31 PM UTC 24 3403723686 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.645329847 Sep 09 09:15:45 PM UTC 24 Sep 09 09:19:34 PM UTC 24 1300353236 ps
T212 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_bijection.1592092985 Sep 09 09:19:02 PM UTC 24 Sep 09 09:19:36 PM UTC 24 367281059 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.4186329777 Sep 09 09:19:33 PM UTC 24 Sep 09 09:19:39 PM UTC 24 231296335 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.3873073081 Sep 09 09:18:07 PM UTC 24 Sep 09 09:19:54 PM UTC 24 931287779 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.233133149 Sep 09 09:19:55 PM UTC 24 Sep 09 09:19:57 PM UTC 24 74059610 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.212527155 Sep 09 09:19:32 PM UTC 24 Sep 09 09:20:02 PM UTC 24 98645059 ps
T217 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.357768202 Sep 09 09:20:03 PM UTC 24 Sep 09 09:20:09 PM UTC 24 182802986 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.4213096830 Sep 09 09:19:58 PM UTC 24 Sep 09 09:20:10 PM UTC 24 1349990368 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.1514488528 Sep 09 09:11:30 PM UTC 24 Sep 09 09:20:18 PM UTC 24 223107015944 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_alert_test.4085673293 Sep 09 09:20:18 PM UTC 24 Sep 09 09:20:20 PM UTC 24 15893776 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.250760612 Sep 09 09:11:26 PM UTC 24 Sep 09 09:21:12 PM UTC 24 8772109785 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.1505436592 Sep 09 09:19:29 PM UTC 24 Sep 09 09:21:26 PM UTC 24 168461329 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_smoke.1223457767 Sep 09 09:20:22 PM UTC 24 Sep 09 09:21:45 PM UTC 24 500212262 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.1959803228 Sep 09 09:18:21 PM UTC 24 Sep 09 09:21:48 PM UTC 24 4743610195 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access.1016732374 Sep 09 09:21:46 PM UTC 24 Sep 09 09:21:50 PM UTC 24 669103984 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.4098071231 Sep 09 09:22:05 PM UTC 24 Sep 09 09:22:07 PM UTC 24 35863366 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.1126275172 Sep 09 09:22:08 PM UTC 24 Sep 09 09:22:18 PM UTC 24 1929073331 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.62213506 Sep 09 09:10:44 PM UTC 24 Sep 09 09:22:19 PM UTC 24 22354867072 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.3448221775 Sep 09 09:14:54 PM UTC 24 Sep 09 09:22:23 PM UTC 24 2079928419 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.4228351973 Sep 09 09:10:36 PM UTC 24 Sep 09 09:22:27 PM UTC 24 37941613431 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.261414614 Sep 09 09:17:03 PM UTC 24 Sep 09 09:22:27 PM UTC 24 3184704450 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.2545211646 Sep 09 09:22:27 PM UTC 24 Sep 09 09:22:29 PM UTC 24 30366964 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.859392777 Sep 09 09:12:59 PM UTC 24 Sep 09 09:22:34 PM UTC 24 18832295413 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.1742384955 Sep 09 09:21:51 PM UTC 24 Sep 09 09:22:37 PM UTC 24 210369464 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.1429069961 Sep 09 09:22:28 PM UTC 24 Sep 09 09:22:39 PM UTC 24 188349456 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.4287731312 Sep 09 09:22:30 PM UTC 24 Sep 09 09:22:40 PM UTC 24 637967962 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_alert_test.2847064910 Sep 09 09:22:39 PM UTC 24 Sep 09 09:22:41 PM UTC 24 34333075 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.2164985865 Sep 09 09:16:12 PM UTC 24 Sep 09 09:22:42 PM UTC 24 8983375574 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_bijection.1792639259 Sep 09 09:21:27 PM UTC 24 Sep 09 09:22:44 PM UTC 24 5386913544 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.451580525 Sep 09 09:14:35 PM UTC 24 Sep 09 09:22:48 PM UTC 24 60640191851 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_smoke.4094416535 Sep 09 09:22:40 PM UTC 24 Sep 09 09:22:52 PM UTC 24 115290000 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.1312980658 Sep 09 09:17:00 PM UTC 24 Sep 09 09:23:19 PM UTC 24 5650114974 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.521597060 Sep 09 09:23:20 PM UTC 24 Sep 09 09:23:22 PM UTC 24 185499429 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_executable.545366550 Sep 09 09:10:30 PM UTC 24 Sep 09 09:23:23 PM UTC 24 4546022344 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.1415152620 Sep 09 09:22:55 PM UTC 24 Sep 09 09:23:31 PM UTC 24 107441212 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access.1787035287 Sep 09 09:22:44 PM UTC 24 Sep 09 09:23:37 PM UTC 24 287352370 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.943208832 Sep 09 09:23:37 PM UTC 24 Sep 09 09:23:39 PM UTC 24 31279902 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_bijection.1442423627 Sep 09 09:22:42 PM UTC 24 Sep 09 09:23:44 PM UTC 24 3193895114 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.3197091029 Sep 09 09:17:23 PM UTC 24 Sep 09 09:23:48 PM UTC 24 5102563956 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.1037104760 Sep 09 09:23:40 PM UTC 24 Sep 09 09:23:50 PM UTC 24 670696531 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.763449593 Sep 09 09:23:45 PM UTC 24 Sep 09 09:23:51 PM UTC 24 503804578 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_alert_test.2022347893 Sep 09 09:23:52 PM UTC 24 Sep 09 09:23:54 PM UTC 24 64703604 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_smoke.3355964096 Sep 09 09:23:55 PM UTC 24 Sep 09 09:24:03 PM UTC 24 489075433 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1436107430 Sep 09 09:20:10 PM UTC 24 Sep 09 09:24:07 PM UTC 24 4530480624 ps
T136 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_executable.133649093 Sep 09 09:22:19 PM UTC 24 Sep 09 09:24:13 PM UTC 24 3836723104 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.1231460475 Sep 09 09:19:19 PM UTC 24 Sep 09 09:24:25 PM UTC 24 6921803227 ps
T251 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.2414948059 Sep 09 09:23:03 PM UTC 24 Sep 09 09:24:38 PM UTC 24 151020759 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.3261900505 Sep 09 09:19:04 PM UTC 24 Sep 09 09:24:40 PM UTC 24 5991159677 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_regwen.2778608330 Sep 09 09:10:22 PM UTC 24 Sep 09 09:24:46 PM UTC 24 12174351759 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access.506614139 Sep 09 09:24:26 PM UTC 24 Sep 09 09:24:47 PM UTC 24 306706371 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.1238104586 Sep 09 09:16:41 PM UTC 24 Sep 09 09:24:49 PM UTC 24 6141750922 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.3403555370 Sep 09 09:24:46 PM UTC 24 Sep 09 09:24:51 PM UTC 24 755819351 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_bijection.1206322420 Sep 09 09:24:08 PM UTC 24 Sep 09 09:24:57 PM UTC 24 2121137052 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.2822946643 Sep 09 09:24:48 PM UTC 24 Sep 09 09:24:58 PM UTC 24 2977530648 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.1860173967 Sep 09 09:24:41 PM UTC 24 Sep 09 09:24:59 PM UTC 24 631221651 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.2483560248 Sep 09 09:10:29 PM UTC 24 Sep 09 09:25:00 PM UTC 24 15492568477 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.1534244339 Sep 09 09:24:58 PM UTC 24 Sep 09 09:25:00 PM UTC 24 75743743 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.343775476 Sep 09 09:23:49 PM UTC 24 Sep 09 09:25:02 PM UTC 24 3488805395 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_alert_test.3896889330 Sep 09 09:25:02 PM UTC 24 Sep 09 09:25:04 PM UTC 24 37957348 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.2949803178 Sep 09 09:25:00 PM UTC 24 Sep 09 09:25:08 PM UTC 24 174266077 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.151615012 Sep 09 09:24:59 PM UTC 24 Sep 09 09:25:08 PM UTC 24 374931420 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_smoke.1433954639 Sep 09 09:25:05 PM UTC 24 Sep 09 09:25:10 PM UTC 24 132773490 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_bijection.788661305 Sep 09 09:25:09 PM UTC 24 Sep 09 09:25:31 PM UTC 24 3644723167 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.993601732 Sep 09 09:18:54 PM UTC 24 Sep 09 09:25:35 PM UTC 24 32450467109 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.89521126 Sep 09 09:11:00 PM UTC 24 Sep 09 09:25:40 PM UTC 24 103141341315 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access.2035543299 Sep 09 09:25:32 PM UTC 24 Sep 09 09:25:42 PM UTC 24 183062459 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.4206832941 Sep 09 09:25:41 PM UTC 24 Sep 09 09:25:58 PM UTC 24 257862245 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.3280838797 Sep 09 09:25:59 PM UTC 24 Sep 09 09:26:06 PM UTC 24 778269666 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.2951389199 Sep 09 09:25:42 PM UTC 24 Sep 09 09:26:07 PM UTC 24 90584250 ps
T138 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_executable.2343055856 Sep 09 09:10:37 PM UTC 24 Sep 09 09:26:28 PM UTC 24 169425367784 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_executable.377050909 Sep 09 09:11:07 PM UTC 24 Sep 09 09:26:30 PM UTC 24 17793406788 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.816392358 Sep 09 09:26:31 PM UTC 24 Sep 09 09:26:33 PM UTC 24 82694446 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.3688242320 Sep 09 09:22:43 PM UTC 24 Sep 09 09:26:41 PM UTC 24 4438356388 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.2683853975 Sep 09 09:26:34 PM UTC 24 Sep 09 09:26:42 PM UTC 24 96968626 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_regwen.385634691 Sep 09 09:19:40 PM UTC 24 Sep 09 09:26:43 PM UTC 24 43026068809 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.3718208016 Sep 09 09:26:42 PM UTC 24 Sep 09 09:26:47 PM UTC 24 62389209 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_alert_test.771959798 Sep 09 09:26:48 PM UTC 24 Sep 09 09:26:50 PM UTC 24 13970678 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_executable.1991223220 Sep 09 09:13:34 PM UTC 24 Sep 09 09:26:56 PM UTC 24 1577230069 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_executable.1378140055 Sep 09 09:24:50 PM UTC 24 Sep 09 09:26:57 PM UTC 24 2648263467 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_smoke.2087360386 Sep 09 09:26:51 PM UTC 24 Sep 09 09:27:02 PM UTC 24 1389703418 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.3811976361 Sep 09 09:10:26 PM UTC 24 Sep 09 09:27:18 PM UTC 24 40136723939 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_executable.4074005925 Sep 09 09:11:55 PM UTC 24 Sep 09 09:27:30 PM UTC 24 42599409146 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.921728178 Sep 09 09:15:27 PM UTC 24 Sep 09 09:27:35 PM UTC 24 51401232587 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_bijection.508978817 Sep 09 09:26:56 PM UTC 24 Sep 09 09:27:39 PM UTC 24 534290401 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.3378173043 Sep 09 09:24:39 PM UTC 24 Sep 09 09:27:43 PM UTC 24 8099615424 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.2688866998 Sep 09 09:13:28 PM UTC 24 Sep 09 09:27:46 PM UTC 24 20806990469 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.2164370006 Sep 09 09:27:36 PM UTC 24 Sep 09 09:27:46 PM UTC 24 63402239 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.59476790 Sep 09 09:27:47 PM UTC 24 Sep 09 09:27:50 PM UTC 24 98791170 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.1331669048 Sep 09 09:27:40 PM UTC 24 Sep 09 09:27:50 PM UTC 24 553882491 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.2079221857 Sep 09 09:21:49 PM UTC 24 Sep 09 09:27:53 PM UTC 24 4163594079 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.4164045471 Sep 09 09:27:50 PM UTC 24 Sep 09 09:27:56 PM UTC 24 224968237 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.1845236826 Sep 09 09:27:50 PM UTC 24 Sep 09 09:28:07 PM UTC 24 587886144 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.4214255790 Sep 09 09:26:54 PM UTC 24 Sep 09 09:28:09 PM UTC 24 2822185501 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_alert_test.631389783 Sep 09 09:28:08 PM UTC 24 Sep 09 09:28:09 PM UTC 24 20593956 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access.981267456 Sep 09 09:27:03 PM UTC 24 Sep 09 09:28:12 PM UTC 24 173936221 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_smoke.1370032017 Sep 09 09:28:11 PM UTC 24 Sep 09 09:28:25 PM UTC 24 141728850 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_regwen.3021665662 Sep 09 09:26:28 PM UTC 24 Sep 09 09:28:33 PM UTC 24 1243163550 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_executable.2400039510 Sep 09 09:19:37 PM UTC 24 Sep 09 09:28:37 PM UTC 24 7044255068 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.2405813255 Sep 09 09:27:31 PM UTC 24 Sep 09 09:28:48 PM UTC 24 124925436 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_regwen.790878511 Sep 09 09:10:37 PM UTC 24 Sep 09 09:28:48 PM UTC 24 16474410744 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.628986309 Sep 09 09:22:49 PM UTC 24 Sep 09 09:28:51 PM UTC 24 8450891475 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access.2885238991 Sep 09 09:28:34 PM UTC 24 Sep 09 09:29:01 PM UTC 24 125662615 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.322602605 Sep 09 09:28:52 PM UTC 24 Sep 09 09:29:07 PM UTC 24 11770142123 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_bijection.581373596 Sep 09 09:28:13 PM UTC 24 Sep 09 09:29:17 PM UTC 24 5144677642 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.2755269724 Sep 09 09:29:17 PM UTC 24 Sep 09 09:29:19 PM UTC 24 25713797 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.2829571314 Sep 09 09:21:29 PM UTC 24 Sep 09 09:29:19 PM UTC 24 15395642437 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.3793766325 Sep 09 09:16:30 PM UTC 24 Sep 09 09:29:21 PM UTC 24 43376740151 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.3573461968 Sep 09 09:25:11 PM UTC 24 Sep 09 09:29:22 PM UTC 24 9595180393 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.269515052 Sep 09 09:29:20 PM UTC 24 Sep 09 09:29:30 PM UTC 24 1339659921 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.364287233 Sep 09 09:29:20 PM UTC 24 Sep 09 09:29:30 PM UTC 24 391235981 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_alert_test.3514425255 Sep 09 09:29:30 PM UTC 24 Sep 09 09:29:32 PM UTC 24 14296203 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_regwen.1781995622 Sep 09 09:10:46 PM UTC 24 Sep 09 09:29:37 PM UTC 24 24968966741 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.2754648777 Sep 09 09:28:49 PM UTC 24 Sep 09 09:29:38 PM UTC 24 395769187 ps
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