Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	144922168	1			T2	5886		T3	7800		T4	2114
instr_valid_dis	112622688	1			T2	5886		T3	7800		T4	2114
instr_en	24087761	1			T26	20100		T55	52		T46	4544

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11166806	1			T26	20000		T135	50554		T17	27946
sram_ifetch_valid_disable	111597839	1			T2	5886		T3	7800		T4	2114
sram_ifetch_enable	22157523	1			T27	13152		T26	26396		T25	42250

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	144922168	1			T2	5886		T3	7800		T4	2114
hw_debug_en_valid_off	112409290	1			T2	5886		T3	7800		T4	2114
hw_debug_en_on	21775816	1			T26	20000		T46	13968		T47	13499

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	111597839	1			T2	5886		T3	7800		T4	2114
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	99538439	1			T2	5886		T3	7800		T4	2114
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9058697	1			T55	52		T135	27122		T17	27386
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3737446	1			T135	13640		T17	12086		T132	23694
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1639742	1			T132	23694		T19	5998		T131	2098
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1553084	1			T17	12086		T133	48266		T157	21072
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4986818	1			T26	20000		T135	36914		T17	15860
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1800972	1			T26	20000		T132	6602		T19	11276
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2065524	1			T135	36914		T17	15860		T131	60288
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8339253	1			T46	9424		T47	6977		T135	27122
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3240281	1			T46	9424		T47	6977		T19	76632
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3702802	1			T135	27122		T133	14808		T158	21600

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10355822	1			T26	20100		T46	4544		T47	6522
lc_exec_en	8449745	1			T46	4544		T47	6522		T17	127198
valid_exec_dis	107996334	1			T2	5886		T3	7800		T4	2114
invalid_exec_dis	33324329	1			T27	13152		T26	46396		T25	42250