Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44


Total tests in report: 1012
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
62.57 62.57 90.51 90.51 63.86 63.86 50.03 50.03 23.81 23.81 78.50 78.50 93.07 93.07 38.21 38.21 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_smoke.3920041419
83.80 21.23 95.59 5.08 80.92 17.06 86.27 36.23 66.67 42.86 87.20 8.70 94.84 1.77 75.14 36.93 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.554310830
88.43 4.63 97.20 1.61 85.19 4.27 97.30 11.03 76.19 9.52 90.82 3.62 95.72 0.88 76.60 1.46 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.1631780765
92.31 3.88 98.22 1.02 85.19 0.00 97.30 0.00 100.00 23.81 92.27 1.45 96.61 0.88 76.60 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.2613348710
93.81 1.50 98.64 0.42 88.03 2.84 97.30 0.00 100.00 0.00 94.20 1.93 96.61 0.00 81.90 5.30 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_regwen.4089859289
94.69 0.87 98.81 0.17 89.69 1.66 98.61 1.32 100.00 0.00 95.17 0.97 96.61 0.00 83.91 2.01 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.2422747558
95.47 0.78 98.81 0.00 90.05 0.36 98.61 0.00 100.00 0.00 95.17 0.00 96.61 0.00 89.03 5.12 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.823265222
95.86 0.39 98.81 0.00 90.05 0.00 98.61 0.00 100.00 0.00 95.17 0.00 96.76 0.15 91.59 2.56 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.2506134251
96.12 0.26 98.81 0.00 90.28 0.24 98.68 0.07 100.00 0.00 95.17 0.00 98.08 1.33 91.77 0.18 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.4206017025
96.35 0.24 98.81 0.00 90.28 0.00 98.68 0.00 100.00 0.00 95.17 0.00 98.08 0.00 93.42 1.65 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_executable.4038220982
96.58 0.23 98.81 0.00 90.40 0.12 98.68 0.00 100.00 0.00 95.89 0.72 98.82 0.74 93.42 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.910177284
96.75 0.18 99.07 0.25 90.40 0.00 98.68 0.00 100.00 0.00 96.14 0.24 98.82 0.00 94.15 0.73 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.1500928957
96.91 0.15 99.07 0.00 90.64 0.24 98.68 0.00 100.00 0.00 96.14 0.00 99.12 0.29 94.70 0.55 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3446522283
97.04 0.13 99.15 0.08 90.64 0.00 99.51 0.83 100.00 0.00 96.14 0.00 99.12 0.00 94.70 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.2762897532
97.14 0.10 99.15 0.00 90.64 0.00 99.51 0.00 100.00 0.00 96.14 0.00 99.12 0.00 95.43 0.73 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_regwen.2901443031
97.20 0.06 99.15 0.00 91.00 0.36 99.58 0.07 100.00 0.00 96.14 0.00 99.12 0.00 95.43 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_alert_test.3931827762
97.25 0.05 99.15 0.00 91.00 0.00 99.58 0.00 100.00 0.00 96.14 0.00 99.12 0.00 95.80 0.37 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2513183758
97.31 0.05 99.15 0.00 91.00 0.00 99.58 0.00 100.00 0.00 96.14 0.00 99.12 0.00 96.16 0.37 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1301196289
97.36 0.05 99.15 0.00 91.00 0.00 99.58 0.00 100.00 0.00 96.14 0.00 99.12 0.00 96.53 0.37 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_smoke.2641312324
97.38 0.03 99.15 0.00 91.00 0.00 99.58 0.00 100.00 0.00 96.14 0.00 99.12 0.00 96.71 0.18 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3125152794
97.41 0.03 99.15 0.00 91.00 0.00 99.58 0.00 100.00 0.00 96.14 0.00 99.12 0.00 96.89 0.18 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3749481620
97.44 0.03 99.15 0.00 91.00 0.00 99.58 0.00 100.00 0.00 96.14 0.00 99.12 0.00 97.07 0.18 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_regwen.3405325091
97.46 0.03 99.15 0.00 91.00 0.00 99.58 0.00 100.00 0.00 96.14 0.00 99.12 0.00 97.26 0.18 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all.2315099018
97.49 0.03 99.15 0.00 91.00 0.00 99.58 0.00 100.00 0.00 96.14 0.00 99.12 0.00 97.44 0.18 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.2344524289
97.51 0.02 99.15 0.00 91.00 0.00 99.72 0.14 100.00 0.00 96.14 0.00 99.12 0.00 97.44 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access.3098928928

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.468182028
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3863386915
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.750659009
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2605405981
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.399492785
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.144622271
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3815635305
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1378479320
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.369246708
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.4006135341
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1807113365
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1677679361
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1542955422
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3512848856
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.184872934
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1670846745
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2064683323
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2674360027
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1565855985
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2063605074
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4056440270
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1973827751
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.4178493917
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.201573811
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3448913760
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1398677619
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2997059177
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2585096692
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1071918466
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1050617585
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3282626213
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3050061249
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1452965846
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.587104185
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2645041878
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1606894986
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3071425753
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2696895486
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.185730631
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2023854698
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.757974320
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4132286384
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2181863170
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1939616087
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1210656393
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3111921209
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2359739310
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2670761185
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.197879529
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1412851676
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.496283631
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1985845613
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3243655794
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3168480337
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1220564384
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3426980668
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1880959675
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2219070532
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3861251397
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2460794518
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1834368899
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2255974555
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.809494905
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3868113100
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3821906025
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3091842382
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1037931294
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1345144501
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1049616083
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2305359445
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1885223098
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2982974262
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2430630457
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2284790332
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1671768308
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3356188280
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.651012327
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3348109899
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1906589055
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3670137604
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1892226400
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1265211279
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/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.1338620263
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.2329476059
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.2998479240
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.277320143
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.1505183738
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.1163997893
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.281697691
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.2579955344
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.2795037840
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.3481321974
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.2653854592
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.767873637
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.880493059
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.3187858356
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3630031385
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.4172230487
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.1131790812
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.2376559382
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.132738935
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.2624792241
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.3552622164
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.3400081579
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.125040994
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.29346679
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.1589545535
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.319536098
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.1032534874
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.3388975631
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.3412345940
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.3490030507
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.1944722000
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all.2970105314
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.107801546
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.666972984
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.4160647638
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.1132096675
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.810005909
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.3997724302
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.525541869
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.3581849308
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.2228721448
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.1020204330
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.1944255706
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.414124043
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.1147310654
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.2036481783
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.2567528762
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.2175166616
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.2691339186
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.1902349719
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.4280504770



Total test records in report: 1012
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_alert_test.3931827762 Sep 11 08:40:24 AM UTC 24 Sep 11 08:40:25 AM UTC 24 16611867 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access.3098928928 Sep 11 08:40:23 AM UTC 24 Sep 11 08:40:29 AM UTC 24 213164075 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_smoke.3920041419 Sep 11 08:40:23 AM UTC 24 Sep 11 08:40:35 AM UTC 24 1650676312 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.3880509526 Sep 11 08:40:23 AM UTC 24 Sep 11 08:40:37 AM UTC 24 184325793 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_alert_test.4069419705 Sep 11 08:40:35 AM UTC 24 Sep 11 08:40:39 AM UTC 24 25167787 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.1631780765 Sep 11 08:40:32 AM UTC 24 Sep 11 08:40:45 AM UTC 24 917007820 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.2762897532 Sep 11 08:40:24 AM UTC 24 Sep 11 08:40:46 AM UTC 24 27776236 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.2431910599 Sep 11 08:40:26 AM UTC 24 Sep 11 08:40:46 AM UTC 24 38225478 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.1492350375 Sep 11 08:40:45 AM UTC 24 Sep 11 08:40:47 AM UTC 24 271880634 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.3816757256 Sep 11 08:40:45 AM UTC 24 Sep 11 08:40:47 AM UTC 24 27810879 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.3687447337 Sep 11 08:40:24 AM UTC 24 Sep 11 08:40:48 AM UTC 24 435258119 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.3292160966 Sep 11 08:40:24 AM UTC 24 Sep 11 08:40:48 AM UTC 24 432836773 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.2321562118 Sep 11 08:40:29 AM UTC 24 Sep 11 08:40:49 AM UTC 24 172340859 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_alert_test.2031983573 Sep 11 08:40:47 AM UTC 24 Sep 11 08:40:49 AM UTC 24 141006191 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.2422747558 Sep 11 08:40:25 AM UTC 24 Sep 11 08:40:50 AM UTC 24 1371541557 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.2672135320 Sep 11 08:40:46 AM UTC 24 Sep 11 08:40:51 AM UTC 24 407569513 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.136240360 Sep 11 08:40:45 AM UTC 24 Sep 11 08:40:51 AM UTC 24 56832071 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.3864438553 Sep 11 08:40:24 AM UTC 24 Sep 11 08:40:51 AM UTC 24 599804779 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.1266044941 Sep 11 08:40:24 AM UTC 24 Sep 11 08:40:51 AM UTC 24 298300047 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.3168922838 Sep 11 08:40:24 AM UTC 24 Sep 11 08:40:52 AM UTC 24 480961777 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.554310830 Sep 11 08:40:24 AM UTC 24 Sep 11 08:40:52 AM UTC 24 194855315 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_bijection.3541216283 Sep 11 08:40:23 AM UTC 24 Sep 11 08:40:53 AM UTC 24 7825868700 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.690312191 Sep 11 08:40:45 AM UTC 24 Sep 11 08:40:54 AM UTC 24 873966876 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.3348236227 Sep 11 08:40:27 AM UTC 24 Sep 11 08:40:54 AM UTC 24 217247580 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_bijection.82921643 Sep 11 08:40:48 AM UTC 24 Sep 11 08:41:59 AM UTC 24 1030078676 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access.2047721653 Sep 11 08:40:25 AM UTC 24 Sep 11 08:40:54 AM UTC 24 2150083196 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.3558654881 Sep 11 08:40:52 AM UTC 24 Sep 11 08:40:55 AM UTC 24 30132938 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.3630943165 Sep 11 08:40:45 AM UTC 24 Sep 11 08:40:55 AM UTC 24 645794329 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.3059426290 Sep 11 08:40:45 AM UTC 24 Sep 11 08:40:56 AM UTC 24 7940410094 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_smoke.2641312324 Sep 11 08:40:35 AM UTC 24 Sep 11 08:40:58 AM UTC 24 526465944 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.2810738458 Sep 11 08:40:53 AM UTC 24 Sep 11 08:40:58 AM UTC 24 86608494 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.1761008524 Sep 11 08:40:25 AM UTC 24 Sep 11 08:40:59 AM UTC 24 71156856 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.1922359533 Sep 11 08:40:50 AM UTC 24 Sep 11 08:41:01 AM UTC 24 592528462 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_regwen.4253496271 Sep 11 08:40:25 AM UTC 24 Sep 11 08:41:03 AM UTC 24 1501317729 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.1762239783 Sep 11 08:40:52 AM UTC 24 Sep 11 08:41:04 AM UTC 24 1833851759 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access.8802026 Sep 11 08:40:45 AM UTC 24 Sep 11 08:41:05 AM UTC 24 975419892 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.910177284 Sep 11 08:40:54 AM UTC 24 Sep 11 08:41:06 AM UTC 24 1022801024 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access.3209698590 Sep 11 08:40:48 AM UTC 24 Sep 11 08:41:06 AM UTC 24 382228292 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_smoke.2622690921 Sep 11 08:40:47 AM UTC 24 Sep 11 08:41:07 AM UTC 24 1942507905 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.217604351 Sep 11 08:41:07 AM UTC 24 Sep 11 08:41:10 AM UTC 24 27156672 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3446522283 Sep 11 08:40:46 AM UTC 24 Sep 11 08:41:12 AM UTC 24 246772112 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.2138510811 Sep 11 08:40:49 AM UTC 24 Sep 11 08:41:13 AM UTC 24 108955089 ps
T111 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.4203327862 Sep 11 08:40:24 AM UTC 24 Sep 11 08:41:17 AM UTC 24 405217546 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_alert_test.2339398506 Sep 11 08:40:55 AM UTC 24 Sep 11 08:41:17 AM UTC 24 43638126 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.1293595038 Sep 11 08:40:55 AM UTC 24 Sep 11 08:41:20 AM UTC 24 679518188 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access.1328008915 Sep 11 08:40:59 AM UTC 24 Sep 11 08:41:20 AM UTC 24 803859964 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.3509836834 Sep 11 08:41:03 AM UTC 24 Sep 11 08:41:20 AM UTC 24 279304157 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_alert_test.3534323500 Sep 11 08:41:18 AM UTC 24 Sep 11 08:41:20 AM UTC 24 19574937 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.3304858950 Sep 11 08:41:11 AM UTC 24 Sep 11 08:41:23 AM UTC 24 94808839 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_smoke.1401598634 Sep 11 08:41:18 AM UTC 24 Sep 11 08:41:24 AM UTC 24 161318051 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_executable.1518695610 Sep 11 08:40:45 AM UTC 24 Sep 11 08:41:27 AM UTC 24 28238229344 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_smoke.4238662786 Sep 11 08:40:55 AM UTC 24 Sep 11 08:41:31 AM UTC 24 644040710 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.3286935621 Sep 11 08:40:50 AM UTC 24 Sep 11 08:41:31 AM UTC 24 455533272 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.494102814 Sep 11 08:41:08 AM UTC 24 Sep 11 08:41:33 AM UTC 24 686647120 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.515333257 Sep 11 08:41:25 AM UTC 24 Sep 11 08:41:36 AM UTC 24 112686283 ps
T118 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.2405524408 Sep 11 08:41:32 AM UTC 24 Sep 11 08:41:40 AM UTC 24 606047025 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.1500928957 Sep 11 08:40:25 AM UTC 24 Sep 11 08:41:40 AM UTC 24 250414460 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_bijection.409095690 Sep 11 08:40:25 AM UTC 24 Sep 11 08:41:43 AM UTC 24 2323207873 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.1456045234 Sep 11 08:41:41 AM UTC 24 Sep 11 08:41:44 AM UTC 24 96161260 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_bijection.3459723818 Sep 11 08:40:38 AM UTC 24 Sep 11 08:41:46 AM UTC 24 6275816417 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.4242574742 Sep 11 08:41:00 AM UTC 24 Sep 11 08:41:47 AM UTC 24 360065726 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access.1238245065 Sep 11 08:41:22 AM UTC 24 Sep 11 08:41:48 AM UTC 24 1288169542 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.1399338146 Sep 11 08:41:01 AM UTC 24 Sep 11 08:41:48 AM UTC 24 151542407 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_alert_test.4026670397 Sep 11 08:41:48 AM UTC 24 Sep 11 08:41:50 AM UTC 24 59008520 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.3515159739 Sep 11 08:41:44 AM UTC 24 Sep 11 08:41:52 AM UTC 24 64714981 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.3316819027 Sep 11 08:41:41 AM UTC 24 Sep 11 08:41:54 AM UTC 24 268575839 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.3322715160 Sep 11 08:41:28 AM UTC 24 Sep 11 08:41:58 AM UTC 24 175991011 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_bijection.2263806393 Sep 11 08:40:56 AM UTC 24 Sep 11 08:42:07 AM UTC 24 3523100549 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_bijection.1345854612 Sep 11 08:41:20 AM UTC 24 Sep 11 08:42:08 AM UTC 24 1454682372 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.2795037840 Sep 11 08:41:55 AM UTC 24 Sep 11 08:42:09 AM UTC 24 182377788 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_smoke.3266262864 Sep 11 08:40:24 AM UTC 24 Sep 11 08:42:09 AM UTC 24 205829851 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_executable.494440838 Sep 11 08:40:24 AM UTC 24 Sep 11 08:42:11 AM UTC 24 2586556602 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.1505183738 Sep 11 08:42:00 AM UTC 24 Sep 11 08:42:11 AM UTC 24 66158754 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.2653854592 Sep 11 08:42:13 AM UTC 24 Sep 11 08:42:15 AM UTC 24 27769487 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.277320143 Sep 11 08:42:09 AM UTC 24 Sep 11 08:42:15 AM UTC 24 311882994 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.281697691 Sep 11 08:42:16 AM UTC 24 Sep 11 08:42:24 AM UTC 24 95619695 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.1163997893 Sep 11 08:42:16 AM UTC 24 Sep 11 08:42:24 AM UTC 24 1024059912 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access.235683986 Sep 11 08:40:23 AM UTC 24 Sep 11 08:42:26 AM UTC 24 1068501188 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.1338620263 Sep 11 08:42:26 AM UTC 24 Sep 11 08:42:28 AM UTC 24 11583226 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.1944722000 Sep 11 08:42:29 AM UTC 24 Sep 11 08:42:41 AM UTC 24 237638548 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all.2782060888 Sep 11 08:40:55 AM UTC 24 Sep 11 08:42:58 AM UTC 24 2431689356 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_executable.278398198 Sep 11 08:40:51 AM UTC 24 Sep 11 08:43:01 AM UTC 24 2100105800 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.1032534874 Sep 11 08:43:02 AM UTC 24 Sep 11 08:43:09 AM UTC 24 204028512 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.2329476059 Sep 11 08:41:51 AM UTC 24 Sep 11 08:43:23 AM UTC 24 3468853969 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.3597725976 Sep 11 08:41:20 AM UTC 24 Sep 11 08:43:25 AM UTC 24 2606781945 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.3877393270 Sep 11 08:40:25 AM UTC 24 Sep 11 08:43:33 AM UTC 24 3669982410 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.3400081579 Sep 11 08:43:34 AM UTC 24 Sep 11 08:43:40 AM UTC 24 826411686 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.844010772 Sep 11 08:40:40 AM UTC 24 Sep 11 08:43:40 AM UTC 24 7117996623 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.1131790812 Sep 11 08:42:08 AM UTC 24 Sep 11 08:43:46 AM UTC 24 533002450 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.880493059 Sep 11 08:41:49 AM UTC 24 Sep 11 08:43:53 AM UTC 24 2867777270 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.3412345940 Sep 11 08:43:54 AM UTC 24 Sep 11 08:43:56 AM UTC 24 38090973 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.2624792241 Sep 11 08:42:43 AM UTC 24 Sep 11 08:44:00 AM UTC 24 3805174422 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.4264668365 Sep 11 08:42:10 AM UTC 24 Sep 11 08:44:02 AM UTC 24 434028030 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.1589545535 Sep 11 08:43:57 AM UTC 24 Sep 11 08:44:06 AM UTC 24 486065934 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.29346679 Sep 11 08:44:01 AM UTC 24 Sep 11 08:44:07 AM UTC 24 88245265 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.132738935 Sep 11 08:44:08 AM UTC 24 Sep 11 08:44:10 AM UTC 24 93029490 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.2175166616 Sep 11 08:44:11 AM UTC 24 Sep 11 08:44:27 AM UTC 24 540643276 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.4160647638 Sep 11 08:43:27 AM UTC 24 Sep 11 08:44:31 AM UTC 24 494754014 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.125040994 Sep 11 08:43:24 AM UTC 24 Sep 11 08:44:43 AM UTC 24 134104048 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.102423564 Sep 11 08:40:48 AM UTC 24 Sep 11 08:44:49 AM UTC 24 3864160882 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3630031385 Sep 11 08:42:25 AM UTC 24 Sep 11 08:44:50 AM UTC 24 1129671634 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3527649324 Sep 11 08:41:13 AM UTC 24 Sep 11 08:45:04 AM UTC 24 4081506588 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.414124043 Sep 11 08:44:49 AM UTC 24 Sep 11 08:45:10 AM UTC 24 1489596197 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.2506134251 Sep 11 08:40:23 AM UTC 24 Sep 11 08:45:21 AM UTC 24 11591886435 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.3581849308 Sep 11 08:45:22 AM UTC 24 Sep 11 08:45:29 AM UTC 24 596972370 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.88498296 Sep 11 08:40:59 AM UTC 24 Sep 11 08:45:29 AM UTC 24 3766842001 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.4280504770 Sep 11 08:45:10 AM UTC 24 Sep 11 08:45:40 AM UTC 24 104975373 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.2228721448 Sep 11 08:45:05 AM UTC 24 Sep 11 08:45:47 AM UTC 24 102367385 ps
T135 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_executable.443829555 Sep 11 08:41:33 AM UTC 24 Sep 11 08:45:48 AM UTC 24 4599841770 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.2036481783 Sep 11 08:45:48 AM UTC 24 Sep 11 08:45:50 AM UTC 24 110674184 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.3997724302 Sep 11 08:44:32 AM UTC 24 Sep 11 08:45:52 AM UTC 24 1757993240 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.3972774124 Sep 11 08:40:49 AM UTC 24 Sep 11 08:45:53 AM UTC 24 4149338942 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.2613348710 Sep 11 08:45:51 AM UTC 24 Sep 11 08:45:57 AM UTC 24 199032757 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.810005909 Sep 11 08:45:58 AM UTC 24 Sep 11 08:46:00 AM UTC 24 44171321 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.1020204330 Sep 11 08:45:49 AM UTC 24 Sep 11 08:46:01 AM UTC 24 583359709 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_smoke.2568467965 Sep 11 08:46:01 AM UTC 24 Sep 11 08:46:05 AM UTC 24 240705917 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.1233059468 Sep 11 08:41:24 AM UTC 24 Sep 11 08:46:14 AM UTC 24 29330632979 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.1321646630 Sep 11 08:40:23 AM UTC 24 Sep 11 08:46:41 AM UTC 24 3696212407 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.666972984 Sep 11 08:42:59 AM UTC 24 Sep 11 08:46:45 AM UTC 24 3515968574 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.272773041 Sep 11 08:40:23 AM UTC 24 Sep 11 08:46:48 AM UTC 24 14947586577 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.107801546 Sep 11 08:44:02 AM UTC 24 Sep 11 08:46:51 AM UTC 24 4426990425 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access.528517635 Sep 11 08:46:42 AM UTC 24 Sep 11 08:46:51 AM UTC 24 4343354516 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.4172230487 Sep 11 08:41:53 AM UTC 24 Sep 11 08:46:56 AM UTC 24 5442643676 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.2537052237 Sep 11 08:46:51 AM UTC 24 Sep 11 08:46:57 AM UTC 24 190703466 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.3425769845 Sep 11 08:40:23 AM UTC 24 Sep 11 08:46:57 AM UTC 24 4815183571 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.2344524289 Sep 11 08:46:52 AM UTC 24 Sep 11 08:46:59 AM UTC 24 3167557261 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.808423462 Sep 11 08:40:45 AM UTC 24 Sep 11 08:47:01 AM UTC 24 4571767699 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.2691385756 Sep 11 08:47:00 AM UTC 24 Sep 11 08:47:02 AM UTC 24 80070514 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.268350998 Sep 11 08:47:03 AM UTC 24 Sep 11 08:47:08 AM UTC 24 110991264 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.3781608472 Sep 11 08:46:49 AM UTC 24 Sep 11 08:47:09 AM UTC 24 258128754 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_regwen.4089859289 Sep 11 08:41:07 AM UTC 24 Sep 11 08:49:46 AM UTC 24 40446288697 ps
T212 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_bijection.3946587885 Sep 11 08:46:05 AM UTC 24 Sep 11 08:47:17 AM UTC 24 1880535588 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.583755722 Sep 11 08:47:02 AM UTC 24 Sep 11 08:47:18 AM UTC 24 695421797 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.202445099 Sep 11 08:40:30 AM UTC 24 Sep 11 08:47:19 AM UTC 24 2009381478 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_alert_test.1396126058 Sep 11 08:47:18 AM UTC 24 Sep 11 08:47:20 AM UTC 24 22753774 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_smoke.1639952103 Sep 11 08:47:18 AM UTC 24 Sep 11 08:47:21 AM UTC 24 61757463 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access.4223300512 Sep 11 08:47:21 AM UTC 24 Sep 11 08:47:35 AM UTC 24 5022051557 ps
T217 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.3581645489 Sep 11 08:40:57 AM UTC 24 Sep 11 08:47:38 AM UTC 24 3333376571 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.1372940621 Sep 11 08:47:38 AM UTC 24 Sep 11 08:47:44 AM UTC 24 55065915 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.1055526944 Sep 11 08:47:35 AM UTC 24 Sep 11 08:47:56 AM UTC 24 76050242 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.1489775008 Sep 11 08:47:45 AM UTC 24 Sep 11 08:48:02 AM UTC 24 1996265872 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_bijection.2393401650 Sep 11 08:47:20 AM UTC 24 Sep 11 08:48:08 AM UTC 24 703095470 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.2579955344 Sep 11 08:41:49 AM UTC 24 Sep 11 08:48:22 AM UTC 24 2925174895 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.607670732 Sep 11 08:48:23 AM UTC 24 Sep 11 08:48:25 AM UTC 24 34981246 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.814174179 Sep 11 08:48:26 AM UTC 24 Sep 11 08:48:49 AM UTC 24 6564518036 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.2029473391 Sep 11 08:48:49 AM UTC 24 Sep 11 08:48:56 AM UTC 24 360727460 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2777225233 Sep 11 08:41:45 AM UTC 24 Sep 11 08:49:08 AM UTC 24 3959249455 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.624704159 Sep 11 08:41:20 AM UTC 24 Sep 11 08:49:17 AM UTC 24 42783504795 ps
T132 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_regwen.3096127697 Sep 11 08:40:52 AM UTC 24 Sep 11 08:49:19 AM UTC 24 14728035945 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_alert_test.3524896110 Sep 11 08:49:18 AM UTC 24 Sep 11 08:49:20 AM UTC 24 61186879 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.1902349719 Sep 11 08:44:44 AM UTC 24 Sep 11 08:49:20 AM UTC 24 10496251020 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.4194415652 Sep 11 08:46:46 AM UTC 24 Sep 11 08:49:25 AM UTC 24 11960145333 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.3073591689 Sep 11 08:40:25 AM UTC 24 Sep 11 08:49:34 AM UTC 24 2196835090 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.767873637 Sep 11 08:42:12 AM UTC 24 Sep 11 08:52:16 AM UTC 24 9491616599 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_smoke.2855848902 Sep 11 08:49:20 AM UTC 24 Sep 11 08:49:36 AM UTC 24 482883354 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_bijection.3933075319 Sep 11 08:49:21 AM UTC 24 Sep 11 08:49:48 AM UTC 24 370175226 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.1880086979 Sep 11 08:49:46 AM UTC 24 Sep 11 08:49:52 AM UTC 24 182243777 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.1246980358 Sep 11 08:49:54 AM UTC 24 Sep 11 08:50:03 AM UTC 24 1025424789 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.4294201540 Sep 11 08:40:24 AM UTC 24 Sep 11 08:50:03 AM UTC 24 43678138048 ps
T131 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_executable.4038220982 Sep 11 08:41:06 AM UTC 24 Sep 11 08:50:04 AM UTC 24 2888648571 ps
T133 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.3490030507 Sep 11 08:43:47 AM UTC 24 Sep 11 08:50:04 AM UTC 24 4591663475 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.956320700 Sep 11 08:40:36 AM UTC 24 Sep 11 08:50:04 AM UTC 24 12669941890 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.448922916 Sep 11 08:50:05 AM UTC 24 Sep 11 08:50:08 AM UTC 24 27338648 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.1935680728 Sep 11 08:41:04 AM UTC 24 Sep 11 08:50:16 AM UTC 24 5462239987 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.1406030503 Sep 11 08:50:09 AM UTC 24 Sep 11 08:50:17 AM UTC 24 200021890 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_alert_test.1996452762 Sep 11 08:50:18 AM UTC 24 Sep 11 08:50:20 AM UTC 24 58018243 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.2344402635 Sep 11 08:50:05 AM UTC 24 Sep 11 08:50:23 AM UTC 24 662457893 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.415143857 Sep 11 08:49:49 AM UTC 24 Sep 11 08:50:29 AM UTC 24 351339647 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.391205786 Sep 11 08:47:57 AM UTC 24 Sep 11 08:50:32 AM UTC 24 1428549008 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_smoke.2789906962 Sep 11 08:50:21 AM UTC 24 Sep 11 08:50:35 AM UTC 24 1804400469 ps
T134 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_regwen.2027407234 Sep 11 08:41:37 AM UTC 24 Sep 11 08:50:42 AM UTC 24 40141608774 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.2997446745 Sep 11 08:40:23 AM UTC 24 Sep 11 08:50:47 AM UTC 24 5714137230 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.952513995 Sep 11 08:48:58 AM UTC 24 Sep 11 08:50:48 AM UTC 24 2218951600 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access.3189091473 Sep 11 08:50:36 AM UTC 24 Sep 11 08:50:49 AM UTC 24 8719959668 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.1147310654 Sep 11 08:44:51 AM UTC 24 Sep 11 08:50:52 AM UTC 24 58449140908 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.3234170782 Sep 11 08:50:49 AM UTC 24 Sep 11 08:50:54 AM UTC 24 207076373 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access.2509312182 Sep 11 08:49:34 AM UTC 24 Sep 11 08:50:54 AM UTC 24 199991672 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.3442599656 Sep 11 08:50:48 AM UTC 24 Sep 11 08:50:54 AM UTC 24 167232727 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.340177022 Sep 11 08:50:49 AM UTC 24 Sep 11 08:50:55 AM UTC 24 1919965620 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_bijection.1138788964 Sep 11 08:50:30 AM UTC 24 Sep 11 08:50:57 AM UTC 24 5855027992 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.1321007173 Sep 11 08:50:56 AM UTC 24 Sep 11 08:50:58 AM UTC 24 33123697 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.3827814679 Sep 11 08:40:25 AM UTC 24 Sep 11 08:50:59 AM UTC 24 76357087910 ps
T251 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.809633508 Sep 11 08:46:15 AM UTC 24 Sep 11 08:51:04 AM UTC 24 2651448948 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.1691564108 Sep 11 08:50:56 AM UTC 24 Sep 11 08:51:06 AM UTC 24 831237988 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_alert_test.863363374 Sep 11 08:51:04 AM UTC 24 Sep 11 08:51:06 AM UTC 24 11902723 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.988531163 Sep 11 08:50:58 AM UTC 24 Sep 11 08:51:07 AM UTC 24 1119480158 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.4033532756 Sep 11 08:50:59 AM UTC 24 Sep 11 08:51:13 AM UTC 24 1134552267 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.3388975631 Sep 11 08:43:10 AM UTC 24 Sep 11 08:51:31 AM UTC 24 24509815808 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.3645857755 Sep 11 08:47:22 AM UTC 24 Sep 11 08:51:31 AM UTC 24 3564566288 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_smoke.2518006191 Sep 11 08:51:06 AM UTC 24 Sep 11 08:51:38 AM UTC 24 870071634 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.3652604020 Sep 11 08:46:02 AM UTC 24 Sep 11 08:51:51 AM UTC 24 11458159722 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.1927102807 Sep 11 08:51:39 AM UTC 24 Sep 11 08:51:58 AM UTC 24 214645532 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_bijection.752313431 Sep 11 08:51:09 AM UTC 24 Sep 11 08:51:58 AM UTC 24 626333022 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.1484803302 Sep 11 08:51:52 AM UTC 24 Sep 11 08:51:59 AM UTC 24 57475396 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.3820990020 Sep 11 08:51:58 AM UTC 24 Sep 11 08:52:05 AM UTC 24 380568479 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3823061964 Sep 11 08:47:09 AM UTC 24 Sep 11 08:52:13 AM UTC 24 7691993622 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.2740427427 Sep 11 08:52:14 AM UTC 24 Sep 11 08:52:16 AM UTC 24 90024494 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.3552622164 Sep 11 08:43:41 AM UTC 24 Sep 11 08:52:22 AM UTC 24 46484677676 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.1775701791 Sep 11 08:52:17 AM UTC 24 Sep 11 08:52:25 AM UTC 24 226700851 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.975656077 Sep 11 08:52:17 AM UTC 24 Sep 11 08:52:25 AM UTC 24 586652703 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_alert_test.3763101878 Sep 11 08:52:26 AM UTC 24 Sep 11 08:52:28 AM UTC 24 22144419 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.3481321974 Sep 11 08:41:59 AM UTC 24 Sep 11 08:52:39 AM UTC 24 39519630395 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_smoke.1114141000 Sep 11 08:52:26 AM UTC 24 Sep 11 08:52:42 AM UTC 24 793370264 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.4097062442 Sep 11 08:47:21 AM UTC 24 Sep 11 08:52:45 AM UTC 24 6641982742 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.851105613 Sep 11 08:49:21 AM UTC 24 Sep 11 08:52:45 AM UTC 24 10312542928 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.1511499186 Sep 11 08:49:26 AM UTC 24 Sep 11 08:52:57 AM UTC 24 1998840978 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access.304123030 Sep 11 08:51:32 AM UTC 24 Sep 11 08:52:58 AM UTC 24 540754237 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.750487232 Sep 11 08:52:57 AM UTC 24 Sep 11 08:53:07 AM UTC 24 57958797 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.318242320 Sep 11 08:50:33 AM UTC 24 Sep 11 08:53:07 AM UTC 24 6375896409 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.2716807303 Sep 11 08:40:51 AM UTC 24 Sep 11 08:53:14 AM UTC 24 5786413584 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.2634195493 Sep 11 08:53:08 AM UTC 24 Sep 11 08:53:20 AM UTC 24 1106244602 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_executable.1374680093 Sep 11 08:46:59 AM UTC 24 Sep 11 08:53:31 AM UTC 24 1750166478 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.2197826404 Sep 11 08:40:45 AM UTC 24 Sep 11 08:53:33 AM UTC 24 10377900625 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.2937883268 Sep 11 08:53:32 AM UTC 24 Sep 11 08:53:34 AM UTC 24 49688383 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.758866980 Sep 11 08:53:35 AM UTC 24 Sep 11 08:53:41 AM UTC 24 96678578 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.2537120131 Sep 11 08:53:33 AM UTC 24 Sep 11 08:53:43 AM UTC 24 370071981 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.999619167 Sep 11 08:54:38 AM UTC 24 Sep 11 08:55:03 AM UTC 24 177925662 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access.3341295858 Sep 11 08:52:45 AM UTC 24 Sep 11 08:53:43 AM UTC 24 207008844 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_alert_test.473154913 Sep 11 08:53:44 AM UTC 24 Sep 11 08:53:46 AM UTC 24 18240156 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_bijection.551400788 Sep 11 08:52:40 AM UTC 24 Sep 11 08:54:02 AM UTC 24 4517132236 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.3305756901 Sep 11 08:52:59 AM UTC 24 Sep 11 08:54:08 AM UTC 24 640767383 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.2252135233 Sep 11 08:50:53 AM UTC 24 Sep 11 08:54:21 AM UTC 24 1151407945 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.3611834589 Sep 11 08:51:14 AM UTC 24 Sep 11 08:54:26 AM UTC 24 7064856208 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access.3514310613 Sep 11 08:54:27 AM UTC 24 Sep 11 08:54:34 AM UTC 24 152260641 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.2833584904 Sep 11 08:49:37 AM UTC 24 Sep 11 08:54:36 AM UTC 24 47259634294 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.319536098 Sep 11 08:42:42 AM UTC 24 Sep 11 08:54:38 AM UTC 24 6410568514 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1001452397 Sep 11 08:50:12 AM UTC 24 Sep 11 08:54:57 AM UTC 24 1050293578 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.1075841776 Sep 11 08:54:58 AM UTC 24 Sep 11 08:55:01 AM UTC 24 190286957 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.2883910488 Sep 11 08:41:32 AM UTC 24 Sep 11 08:55:12 AM UTC 24 2728782365 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.1607748500 Sep 11 08:55:13 AM UTC 24 Sep 11 08:55:16 AM UTC 24 27854060 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.1944255706 Sep 11 08:44:28 AM UTC 24 Sep 11 08:55:20 AM UTC 24 9698760719 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_smoke.342992768 Sep 11 08:53:47 AM UTC 24 Sep 11 08:55:20 AM UTC 24 747205738 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.3810763741 Sep 11 08:40:24 AM UTC 24 Sep 11 08:55:22 AM UTC 24 3339759320 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_bijection.1290052585 Sep 11 08:54:09 AM UTC 24 Sep 11 08:55:23 AM UTC 24 21666981301 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_alert_test.3262693751 Sep 11 08:55:23 AM UTC 24 Sep 11 08:55:25 AM UTC 24 19821066 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.2942701108 Sep 11 08:55:17 AM UTC 24 Sep 11 08:55:26 AM UTC 24 2690009195 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.874890484 Sep 11 08:55:15 AM UTC 24 Sep 11 08:55:29 AM UTC 24 696159229 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.2376559382 Sep 11 08:43:40 AM UTC 24 Sep 11 08:55:32 AM UTC 24 5988834376 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access.1686705188 Sep 11 08:55:33 AM UTC 24 Sep 11 08:55:39 AM UTC 24 108933453 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_smoke.3454377868 Sep 11 08:55:24 AM UTC 24 Sep 11 08:55:40 AM UTC 24 188006867 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.2102806100 Sep 11 08:46:56 AM UTC 24 Sep 11 08:55:43 AM UTC 24 8457117337 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.3810494308 Sep 11 08:55:41 AM UTC 24 Sep 11 08:55:45 AM UTC 24 175553098 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.793076965 Sep 11 08:55:46 AM UTC 24 Sep 11 08:55:58 AM UTC 24 1913105594 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_executable.1859628957 Sep 11 08:50:55 AM UTC 24 Sep 11 08:56:11 AM UTC 24 1646206930 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.2265009983 Sep 11 08:54:39 AM UTC 24 Sep 11 08:56:16 AM UTC 24 1628892723 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all.2140476238 Sep 11 08:41:47 AM UTC 24 Sep 11 08:56:18 AM UTC 24 9151947868 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.1132096675 Sep 11 08:45:30 AM UTC 24 Sep 11 08:56:18 AM UTC 24 12415287675 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.3420361478 Sep 11 08:56:19 AM UTC 24 Sep 11 08:56:21 AM UTC 24 41629377 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.1898218365 Sep 11 08:56:22 AM UTC 24 Sep 11 08:56:29 AM UTC 24 64369469 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.2875609196 Sep 11 08:56:19 AM UTC 24 Sep 11 08:56:33 AM UTC 24 461289780 ps
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