Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::key_seed_valid_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::key_seed_valid_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::key_seed_valid_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::key_seed_valid_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
escalated_cp	2	0	2	100.00	100	1	1	2
key_seed_valid_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::key_seed_valid_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
key_seed_valid_cross	4	0	4	100.00	100	1	1	0

Summary for Variable escalated_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for escalated_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8559

1

T2

1

T3

2

T12

1

auto[1]

913

1

T8

14

T9

18

T10

17

---

Summary for Variable key_seed_valid_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_seed_valid_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4765

1

T3

2

T13

1

T7

1

auto[1]

4707

1

T2

1

T12

1

T7

1

---

Summary for Cross key_seed_valid_cross

Samples crossed: key_seed_valid_cp escalated_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key_seed_valid_cross

Bins

key_seed_valid_cp

escalated_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

4314

1

T3

2

T13

1

T7

1

auto[0]

auto[1]

451

1

T8

6

T9

11

T10

10

auto[1]

auto[0]

4245

1

T2

1

T12

1

T7

1

auto[1]

auto[1]

462

1

T8

8

T9

7

T10

7