Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	152975394	1			T2	1484		T4	2090		T5	3786
instr_valid_dis	119561092	1			T2	1484		T4	2090		T5	3786
instr_en	22688033	1			T27	33272		T41	55036		T42	167590

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	12262175	1			T25	308		T27	18446		T129	22456
sram_ifetch_valid_disable	117239228	1			T2	1484		T4	2090		T5	3786
sram_ifetch_enable	23473991	1			T27	37144		T26	18092		T41	23698

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	152975394	1			T2	1484		T4	2090		T5	3786
hw_debug_en_valid_off	116715892	1			T2	1484		T4	2090		T5	3786
hw_debug_en_on	23925951	1			T25	15172		T27	44006		T26	18092

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	117239228	1			T2	1484		T4	2090		T5	3786
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	103797263	1			T2	1484		T4	2090		T5	3786
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9016251	1			T27	68		T41	55036		T42	148762
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4633317	1			T27	18446		T129	9392		T130	10342
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1911038	1			T129	9392		T130	10342		T134	33826
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1798879	1			T27	18446		T131	40000		T65	2569
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4682266	1			T25	308		T129	13064		T19	36170
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2101030	1			T52	50420		T138	40352		T66	20036
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1705534	1			T19	36170		T131	12018		T148	2246
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8692224	1			T25	14864		T27	22418		T41	55036
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4048184	1			T27	17824		T52	1890		T64	9614
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3008734	1			T27	68		T41	55036		T42	128392

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8638078	1			T27	14758		T42	18828		T129	23506
lc_exec_en	10551461	1			T27	21588		T26	18092		T41	11936
valid_exec_dis	114126026	1			T2	1484		T4	2090		T5	3786
invalid_exec_dis	35736166	1			T25	308		T27	55590		T26	18092