Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.93 99.13 94.27 99.72 100.00 95.81 99.12 97.44


Total tests in report: 1014
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
73.46 73.46 91.74 91.74 74.64 74.64 95.15 95.15 33.33 33.33 81.50 81.50 93.41 93.41 44.42 44.42 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.4034856180
90.43 16.97 98.00 6.26 84.72 10.07 96.74 1.60 100.00 66.67 91.50 10.00 96.05 2.64 66.00 21.57 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3845005500
93.20 2.77 98.17 0.17 86.37 1.66 97.57 0.83 100.00 0.00 92.50 1.00 96.05 0.00 81.72 15.72 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2856653244
94.20 1.00 98.35 0.17 86.97 0.59 97.78 0.21 100.00 0.00 93.25 0.75 96.05 0.00 87.02 5.30 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3875487763
95.06 0.85 98.87 0.52 88.03 1.07 97.85 0.07 100.00 0.00 94.75 1.50 97.22 1.17 88.67 1.65 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.4115637579
95.80 0.74 99.04 0.17 90.05 2.01 98.61 0.76 100.00 0.00 95.50 0.75 97.80 0.59 89.58 0.91 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.1910844806
96.29 0.49 99.04 0.00 90.17 0.12 98.61 0.00 100.00 0.00 95.50 0.00 97.80 0.00 92.87 3.29 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_regwen.252544532
96.50 0.21 99.04 0.00 90.40 0.24 98.68 0.07 100.00 0.00 95.50 0.00 98.98 1.17 92.87 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3876146002
96.71 0.21 99.04 0.00 90.40 0.00 98.68 0.00 100.00 0.00 95.50 0.00 98.98 0.00 94.33 1.46 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.1686268105
96.86 0.16 99.04 0.00 90.40 0.00 98.68 0.00 100.00 0.00 95.50 0.00 98.98 0.00 95.43 1.10 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_regwen.3150760885
96.99 0.13 99.13 0.09 90.40 0.00 99.51 0.83 100.00 0.00 95.50 0.00 98.98 0.00 95.43 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.408240026
97.12 0.12 99.13 0.00 90.40 0.00 99.65 0.14 100.00 0.00 95.50 0.00 98.98 0.00 96.16 0.73 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.28060057
97.21 0.09 99.13 0.00 90.52 0.12 99.65 0.00 100.00 0.00 96.00 0.50 98.98 0.00 96.16 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1451340901
97.28 0.08 99.13 0.00 90.52 0.00 99.65 0.00 100.00 0.00 96.00 0.00 98.98 0.00 96.71 0.55 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.411570657
97.34 0.06 99.13 0.00 90.88 0.36 99.72 0.07 100.00 0.00 96.00 0.00 98.98 0.00 96.71 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.3020185713
97.40 0.05 99.13 0.00 90.88 0.00 99.72 0.00 100.00 0.00 96.00 0.00 98.98 0.00 97.07 0.37 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.4200448257
97.44 0.04 99.13 0.00 91.00 0.12 99.72 0.00 100.00 0.00 96.00 0.00 98.98 0.00 97.26 0.18 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.2438676910
97.47 0.03 99.13 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.00 0.00 98.98 0.00 97.44 0.18 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2607289383
97.49 0.02 99.13 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.00 0.00 99.12 0.15 97.44 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.424097279

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.119520606
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2912482982
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.518453484
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3960173007
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2761473848
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.4185707305
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.4068546933
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.915168486
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2845976093
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2070708647
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3959327345
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1763977557
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.752052868
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.664179607
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.928754592
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.524179018
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1906664998
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1335521488
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3601501944
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.857025882
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3959814578
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.689162858
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3595239121
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2638254589
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3819635127
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2980409469
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3558590160
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.30946532
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.418919394
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1334845700
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3875736711
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.554929443
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1000741536
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3952304343
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.86167087
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.486399628
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2861088547
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3229597391
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1219540029
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3329147671
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.4234809795
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3493177964
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1147342669
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2577509761
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.931134148
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1261315102
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.895736536
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1526700517
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1938281047
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1512870470
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1643429458
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2785203547
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1352025589
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3198464411
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1547127230
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1206535395
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.227730606
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.605134685
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2047922105
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2860720328
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.390667620
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3336355523
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.4232243847
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1351150074
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4193028357
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1230866140
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1955180075
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3768855026
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2733353762
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2950480462
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.4074402747
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2509446619
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2814813104
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3730562819
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2909540271
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.402940463
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3250214165
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3965348728
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3650621494
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.335497063
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.815155293
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.829578499
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3507134293
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.4171681907
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2713021768
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2617462923
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2512759768
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.303161130
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.771360730
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2791369011
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1196425478
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1693282272
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/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.745720983
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.1691121748
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.767037459
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.2821821579
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.3430670630
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.1410360791
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.4076790
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.818627123
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.1574936874
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.1291959252
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.109647176
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.2315035868
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.1059393535
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.3829157867
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.1502788751
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.19656514
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.769799486
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.731176691
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.63939072
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.418710986
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.4271488330
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.367246572
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.2093436625
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all.3857441593
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1658284068
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.1152170558
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.3290415887
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.1600107753
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.1619846552
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.2234147071
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.143079936
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.2327816940
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.2720798964
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.3803938580
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.1176195677
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.336151122
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.2484571010
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.2146614112
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3106053712
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.2144922680
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.1759603513
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.3310913425
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2906340285
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.2942880266
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.3930019820



Total test records in report: 1014
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.408240026 Sep 18 08:23:44 AM UTC 24 Sep 18 08:23:46 AM UTC 24 27465781 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.1193755673 Sep 18 08:23:43 AM UTC 24 Sep 18 08:23:47 AM UTC 24 408128629 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.3020185713 Sep 18 08:23:47 AM UTC 24 Sep 18 08:23:49 AM UTC 24 29742562 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.1910844806 Sep 18 08:23:46 AM UTC 24 Sep 18 08:23:50 AM UTC 24 246680089 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.3289130457 Sep 18 08:23:44 AM UTC 24 Sep 18 08:23:53 AM UTC 24 91369942 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.1999911930 Sep 18 08:23:54 AM UTC 24 Sep 18 08:23:56 AM UTC 24 28659281 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_smoke.2706498141 Sep 18 08:23:43 AM UTC 24 Sep 18 08:23:58 AM UTC 24 981745327 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.4034856180 Sep 18 08:23:49 AM UTC 24 Sep 18 08:24:00 AM UTC 24 465807203 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.2982444666 Sep 18 08:23:55 AM UTC 24 Sep 18 08:24:01 AM UTC 24 75745702 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.1292706055 Sep 18 08:23:44 AM UTC 24 Sep 18 08:24:01 AM UTC 24 455663017 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_alert_test.518734222 Sep 18 08:24:00 AM UTC 24 Sep 18 08:24:02 AM UTC 24 22708996 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.1306684393 Sep 18 08:24:00 AM UTC 24 Sep 18 08:24:04 AM UTC 24 361990082 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.4115637579 Sep 18 08:23:56 AM UTC 24 Sep 18 08:24:04 AM UTC 24 832211158 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_smoke.1621454103 Sep 18 08:24:01 AM UTC 24 Sep 18 08:24:05 AM UTC 24 49181550 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.3200928771 Sep 18 08:24:07 AM UTC 24 Sep 18 08:24:10 AM UTC 24 516814751 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.1140474458 Sep 18 08:24:04 AM UTC 24 Sep 18 08:24:24 AM UTC 24 142591992 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_bijection.466773746 Sep 18 08:23:47 AM UTC 24 Sep 18 08:24:25 AM UTC 24 1904917213 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.2476069673 Sep 18 08:24:25 AM UTC 24 Sep 18 08:24:27 AM UTC 24 30584394 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.18826112 Sep 18 08:24:26 AM UTC 24 Sep 18 08:24:33 AM UTC 24 102533681 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.3019343662 Sep 18 08:24:28 AM UTC 24 Sep 18 08:24:34 AM UTC 24 97424273 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access.1525826569 Sep 18 08:23:48 AM UTC 24 Sep 18 08:24:38 AM UTC 24 137814632 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_smoke.1910479210 Sep 18 08:23:47 AM UTC 24 Sep 18 08:24:43 AM UTC 24 1047425251 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.1663792734 Sep 18 08:24:38 AM UTC 24 Sep 18 08:24:44 AM UTC 24 372407450 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.3393889947 Sep 18 08:24:04 AM UTC 24 Sep 18 08:24:44 AM UTC 24 108580774 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_alert_test.3991952025 Sep 18 08:24:45 AM UTC 24 Sep 18 08:24:47 AM UTC 24 38719355 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_smoke.1283853987 Sep 18 08:24:45 AM UTC 24 Sep 18 08:24:52 AM UTC 24 181184981 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.2891119097 Sep 18 08:23:43 AM UTC 24 Sep 18 08:24:54 AM UTC 24 1350513186 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_bijection.2739965022 Sep 18 08:24:02 AM UTC 24 Sep 18 08:24:58 AM UTC 24 1043889023 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.463101633 Sep 18 08:23:49 AM UTC 24 Sep 18 08:25:01 AM UTC 24 131313988 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_bijection.2463976747 Sep 18 08:23:43 AM UTC 24 Sep 18 08:25:03 AM UTC 24 4286146203 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access.371783430 Sep 18 08:23:43 AM UTC 24 Sep 18 08:25:08 AM UTC 24 1511902548 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.4059923966 Sep 18 08:25:03 AM UTC 24 Sep 18 08:25:09 AM UTC 24 53284681 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.3056678349 Sep 18 08:25:06 AM UTC 24 Sep 18 08:25:10 AM UTC 24 1344937747 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.2695254423 Sep 18 08:23:49 AM UTC 24 Sep 18 08:25:25 AM UTC 24 619687797 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.3759390297 Sep 18 08:25:27 AM UTC 24 Sep 18 08:25:29 AM UTC 24 57179996 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.1767684724 Sep 18 08:23:43 AM UTC 24 Sep 18 08:25:31 AM UTC 24 1161536576 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.1690164446 Sep 18 08:25:30 AM UTC 24 Sep 18 08:25:36 AM UTC 24 147924375 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.2655216868 Sep 18 08:25:32 AM UTC 24 Sep 18 08:25:38 AM UTC 24 189572750 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access.1332128378 Sep 18 08:24:55 AM UTC 24 Sep 18 08:25:42 AM UTC 24 2102962725 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.1763169131 Sep 18 08:25:39 AM UTC 24 Sep 18 08:25:43 AM UTC 24 435558674 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_alert_test.547928645 Sep 18 08:25:43 AM UTC 24 Sep 18 08:25:45 AM UTC 24 16761956 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2856653244 Sep 18 08:23:57 AM UTC 24 Sep 18 08:25:59 AM UTC 24 4004513137 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_smoke.2901821254 Sep 18 08:25:43 AM UTC 24 Sep 18 08:26:10 AM UTC 24 2488523794 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access.3003158993 Sep 18 08:24:02 AM UTC 24 Sep 18 08:26:16 AM UTC 24 267777393 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.209539547 Sep 18 08:25:02 AM UTC 24 Sep 18 08:26:17 AM UTC 24 132834190 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.303868363 Sep 18 08:26:10 AM UTC 24 Sep 18 08:26:17 AM UTC 24 333747360 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_bijection.2762518349 Sep 18 08:24:48 AM UTC 24 Sep 18 08:26:21 AM UTC 24 22754285636 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.2878760376 Sep 18 08:23:43 AM UTC 24 Sep 18 08:26:21 AM UTC 24 1357978719 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.825090958 Sep 18 08:26:21 AM UTC 24 Sep 18 08:26:23 AM UTC 24 29805713 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.2325448170 Sep 18 08:26:17 AM UTC 24 Sep 18 08:26:26 AM UTC 24 716111273 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.1567031636 Sep 18 08:26:11 AM UTC 24 Sep 18 08:26:27 AM UTC 24 716197427 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.443695404 Sep 18 08:26:27 AM UTC 24 Sep 18 08:26:34 AM UTC 24 98978145 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.1844180260 Sep 18 08:23:52 AM UTC 24 Sep 18 08:26:35 AM UTC 24 1227900747 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access.701837307 Sep 18 08:26:08 AM UTC 24 Sep 18 08:26:36 AM UTC 24 3259930778 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_alert_test.402379901 Sep 18 08:26:35 AM UTC 24 Sep 18 08:26:36 AM UTC 24 38044598 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.2391440809 Sep 18 08:26:24 AM UTC 24 Sep 18 08:26:39 AM UTC 24 879934883 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.3912323627 Sep 18 08:26:34 AM UTC 24 Sep 18 08:26:39 AM UTC 24 240059400 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_bijection.3209382555 Sep 18 08:25:58 AM UTC 24 Sep 18 08:26:40 AM UTC 24 538754311 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access.1816436190 Sep 18 08:26:40 AM UTC 24 Sep 18 08:26:55 AM UTC 24 1797816413 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_executable.2309038321 Sep 18 08:25:09 AM UTC 24 Sep 18 08:26:57 AM UTC 24 7949332594 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3845005500 Sep 18 08:23:46 AM UTC 24 Sep 18 08:27:01 AM UTC 24 13207962917 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.2630613252 Sep 18 08:26:56 AM UTC 24 Sep 18 08:27:03 AM UTC 24 163056570 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.1351856088 Sep 18 08:26:57 AM UTC 24 Sep 18 08:27:07 AM UTC 24 458296202 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.3605787783 Sep 18 08:23:48 AM UTC 24 Sep 18 08:27:08 AM UTC 24 3805866670 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.3464429218 Sep 18 08:27:08 AM UTC 24 Sep 18 08:27:10 AM UTC 24 30650385 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.3592909935 Sep 18 08:26:44 AM UTC 24 Sep 18 08:27:11 AM UTC 24 88871871 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_smoke.3227819235 Sep 18 08:26:36 AM UTC 24 Sep 18 08:27:11 AM UTC 24 2828117210 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.1485316657 Sep 18 08:27:12 AM UTC 24 Sep 18 08:27:16 AM UTC 24 67797899 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_alert_test.3735511079 Sep 18 08:27:17 AM UTC 24 Sep 18 08:27:19 AM UTC 24 14591879 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.3299496081 Sep 18 08:27:09 AM UTC 24 Sep 18 08:27:20 AM UTC 24 1542372863 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_smoke.1742245503 Sep 18 08:27:21 AM UTC 24 Sep 18 08:27:33 AM UTC 24 585185244 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.28060057 Sep 18 08:24:53 AM UTC 24 Sep 18 08:27:42 AM UTC 24 5265924015 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_bijection.3981043659 Sep 18 08:26:37 AM UTC 24 Sep 18 08:27:58 AM UTC 24 2629116774 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access.3739420279 Sep 18 08:27:43 AM UTC 24 Sep 18 08:28:04 AM UTC 24 263768956 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_executable.1281709055 Sep 18 08:24:11 AM UTC 24 Sep 18 08:28:10 AM UTC 24 18002166883 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.3292838037 Sep 18 08:28:00 AM UTC 24 Sep 18 08:28:13 AM UTC 24 74879082 ps
T117 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.2607777067 Sep 18 08:28:11 AM UTC 24 Sep 18 08:28:17 AM UTC 24 536418231 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_regwen.40731741 Sep 18 08:23:54 AM UTC 24 Sep 18 08:28:26 AM UTC 24 11750675255 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.3959867822 Sep 18 08:28:26 AM UTC 24 Sep 18 08:28:28 AM UTC 24 48655944 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.1430127283 Sep 18 08:28:29 AM UTC 24 Sep 18 08:28:36 AM UTC 24 534947539 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_executable.1445195865 Sep 18 08:26:18 AM UTC 24 Sep 18 08:28:40 AM UTC 24 1153379374 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.639827518 Sep 18 08:28:37 AM UTC 24 Sep 18 08:28:44 AM UTC 24 1246307617 ps
T132 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_executable.3748980061 Sep 18 08:27:02 AM UTC 24 Sep 18 08:28:49 AM UTC 24 600077309 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_alert_test.2390798686 Sep 18 08:28:48 AM UTC 24 Sep 18 08:28:51 AM UTC 24 78995832 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.3430670630 Sep 18 08:28:50 AM UTC 24 Sep 18 08:28:55 AM UTC 24 304455112 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_regwen.423481682 Sep 18 08:23:44 AM UTC 24 Sep 18 08:29:00 AM UTC 24 5227712307 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.4060415922 Sep 18 08:26:01 AM UTC 24 Sep 18 08:29:16 AM UTC 24 7512246515 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.812977781 Sep 18 08:28:40 AM UTC 24 Sep 18 08:29:21 AM UTC 24 1952878355 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.1014024401 Sep 18 08:26:37 AM UTC 24 Sep 18 08:29:24 AM UTC 24 2434593710 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.458305350 Sep 18 08:29:25 AM UTC 24 Sep 18 08:29:35 AM UTC 24 57615548 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.3225181468 Sep 18 08:24:10 AM UTC 24 Sep 18 08:29:41 AM UTC 24 1824410050 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_regwen.2400212848 Sep 18 08:27:04 AM UTC 24 Sep 18 08:29:44 AM UTC 24 4890058837 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.1075989577 Sep 18 08:28:06 AM UTC 24 Sep 18 08:29:45 AM UTC 24 152951865 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_bijection.1516374910 Sep 18 08:27:33 AM UTC 24 Sep 18 08:29:45 AM UTC 24 10231967806 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.2959376834 Sep 18 08:24:01 AM UTC 24 Sep 18 08:29:46 AM UTC 24 16278124208 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.4072624124 Sep 18 08:29:36 AM UTC 24 Sep 18 08:29:46 AM UTC 24 401417274 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.767037459 Sep 18 08:29:47 AM UTC 24 Sep 18 08:29:49 AM UTC 24 76705868 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.800146742 Sep 18 08:29:48 AM UTC 24 Sep 18 08:29:55 AM UTC 24 95203018 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.987813527 Sep 18 08:29:47 AM UTC 24 Sep 18 08:29:59 AM UTC 24 522267465 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all.547705402 Sep 18 08:27:13 AM UTC 24 Sep 18 08:30:02 AM UTC 24 18547304632 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.3632764390 Sep 18 08:30:00 AM UTC 24 Sep 18 08:30:02 AM UTC 24 12934140 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.4285662025 Sep 18 08:26:27 AM UTC 24 Sep 18 08:30:06 AM UTC 24 5082672174 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.1935074396 Sep 18 08:28:56 AM UTC 24 Sep 18 08:30:07 AM UTC 24 3903725176 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.1574936874 Sep 18 08:29:33 AM UTC 24 Sep 18 08:30:12 AM UTC 24 645894468 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.4076790 Sep 18 08:29:50 AM UTC 24 Sep 18 08:30:12 AM UTC 24 686156031 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.63939072 Sep 18 08:30:12 AM UTC 24 Sep 18 08:30:21 AM UTC 24 144845491 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.2093436625 Sep 18 08:30:02 AM UTC 24 Sep 18 08:30:22 AM UTC 24 865970928 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.1502788751 Sep 18 08:30:22 AM UTC 24 Sep 18 08:30:25 AM UTC 24 73854647 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.3290415887 Sep 18 08:30:23 AM UTC 24 Sep 18 08:30:30 AM UTC 24 236098221 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.3829157867 Sep 18 08:30:26 AM UTC 24 Sep 18 08:30:34 AM UTC 24 617031947 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.745720983 Sep 18 08:29:17 AM UTC 24 Sep 18 08:31:08 AM UTC 24 2700149970 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.2685894442 Sep 18 08:24:02 AM UTC 24 Sep 18 08:31:10 AM UTC 24 3349812668 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.4271488330 Sep 18 08:31:11 AM UTC 24 Sep 18 08:31:13 AM UTC 24 187039685 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.2315035868 Sep 18 08:30:07 AM UTC 24 Sep 18 08:31:15 AM UTC 24 2055668781 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.19656514 Sep 18 08:31:15 AM UTC 24 Sep 18 08:31:21 AM UTC 24 396300818 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.769799486 Sep 18 08:31:14 AM UTC 24 Sep 18 08:31:22 AM UTC 24 100611310 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.3215121577 Sep 18 08:26:40 AM UTC 24 Sep 18 08:31:40 AM UTC 24 10112303012 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.109647176 Sep 18 08:31:41 AM UTC 24 Sep 18 08:31:43 AM UTC 24 14823627 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.3033128776 Sep 18 08:27:21 AM UTC 24 Sep 18 08:31:48 AM UTC 24 14535574141 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.2813113092 Sep 18 08:24:03 AM UTC 24 Sep 18 08:31:49 AM UTC 24 61288433747 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.1158307828 Sep 18 08:26:09 AM UTC 24 Sep 18 08:32:04 AM UTC 24 18657153655 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.1759603513 Sep 18 08:31:44 AM UTC 24 Sep 18 08:32:05 AM UTC 24 226224664 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.1291959252 Sep 18 08:30:31 AM UTC 24 Sep 18 08:32:08 AM UTC 24 175891856 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.818627123 Sep 18 08:29:01 AM UTC 24 Sep 18 08:32:23 AM UTC 24 2079943562 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.3930019820 Sep 18 08:32:24 AM UTC 24 Sep 18 08:32:42 AM UTC 24 495781438 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.3414719203 Sep 18 08:23:48 AM UTC 24 Sep 18 08:32:42 AM UTC 24 11829291820 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1658284068 Sep 18 08:31:21 AM UTC 24 Sep 18 08:32:55 AM UTC 24 1268625928 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.2327816940 Sep 18 08:32:43 AM UTC 24 Sep 18 08:32:56 AM UTC 24 2772959505 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.2720798964 Sep 18 08:32:11 AM UTC 24 Sep 18 08:33:03 AM UTC 24 121140006 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3106053712 Sep 18 08:33:04 AM UTC 24 Sep 18 08:33:06 AM UTC 24 84545122 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.1236807188 Sep 18 08:27:49 AM UTC 24 Sep 18 08:33:19 AM UTC 24 16370679240 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.1176195677 Sep 18 08:33:07 AM UTC 24 Sep 18 08:33:22 AM UTC 24 1812445692 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.1691121748 Sep 18 08:29:22 AM UTC 24 Sep 18 08:33:22 AM UTC 24 6114143634 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.418710986 Sep 18 08:30:12 AM UTC 24 Sep 18 08:33:25 AM UTC 24 2358609086 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.1619846552 Sep 18 08:33:23 AM UTC 24 Sep 18 08:33:25 AM UTC 24 38195712 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.3803938580 Sep 18 08:33:19 AM UTC 24 Sep 18 08:33:28 AM UTC 24 183657496 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.2484571010 Sep 18 08:32:05 AM UTC 24 Sep 18 08:33:29 AM UTC 24 691853511 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_smoke.2574281685 Sep 18 08:33:25 AM UTC 24 Sep 18 08:33:37 AM UTC 24 718987583 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access.499683981 Sep 18 08:33:38 AM UTC 24 Sep 18 08:33:41 AM UTC 24 56412171 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.731176691 Sep 18 08:30:03 AM UTC 24 Sep 18 08:33:46 AM UTC 24 2867957070 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.2234147071 Sep 18 08:31:50 AM UTC 24 Sep 18 08:33:48 AM UTC 24 54185092663 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.2294245643 Sep 18 08:23:47 AM UTC 24 Sep 18 08:33:55 AM UTC 24 13812653552 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.3875109627 Sep 18 08:33:47 AM UTC 24 Sep 18 08:34:05 AM UTC 24 125283388 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.288581368 Sep 18 08:33:55 AM UTC 24 Sep 18 08:34:06 AM UTC 24 665144671 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.2618782902 Sep 18 08:28:52 AM UTC 24 Sep 18 08:34:17 AM UTC 24 6632574991 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.2893423036 Sep 18 08:24:59 AM UTC 24 Sep 18 08:34:22 AM UTC 24 179920223317 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.3832845490 Sep 18 08:34:22 AM UTC 24 Sep 18 08:34:25 AM UTC 24 71926801 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.1686268105 Sep 18 08:23:43 AM UTC 24 Sep 18 08:34:27 AM UTC 24 85459470806 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.885105604 Sep 18 08:26:17 AM UTC 24 Sep 18 08:34:29 AM UTC 24 2646623205 ps
T212 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.1227884752 Sep 18 08:34:26 AM UTC 24 Sep 18 08:34:33 AM UTC 24 189066777 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.1541695234 Sep 18 08:34:28 AM UTC 24 Sep 18 08:34:34 AM UTC 24 175761738 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_bijection.1742432457 Sep 18 08:33:30 AM UTC 24 Sep 18 08:34:35 AM UTC 24 2861338669 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_alert_test.2063576504 Sep 18 08:34:35 AM UTC 24 Sep 18 08:34:37 AM UTC 24 21632925 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.451871416 Sep 18 08:27:41 AM UTC 24 Sep 18 08:34:41 AM UTC 24 3788686375 ps
T217 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.528000955 Sep 18 08:26:40 AM UTC 24 Sep 18 08:34:55 AM UTC 24 73441883528 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_smoke.2623225586 Sep 18 08:34:36 AM UTC 24 Sep 18 08:34:57 AM UTC 24 1674221804 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.2353052075 Sep 18 08:33:49 AM UTC 24 Sep 18 08:35:03 AM UTC 24 279846008 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3937845594 Sep 18 08:34:30 AM UTC 24 Sep 18 08:35:04 AM UTC 24 554351763 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.2208973958 Sep 18 08:35:05 AM UTC 24 Sep 18 08:35:08 AM UTC 24 344726789 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.1869241278 Sep 18 08:35:17 AM UTC 24 Sep 18 08:35:25 AM UTC 24 1619977453 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_bijection.3319179707 Sep 18 08:34:41 AM UTC 24 Sep 18 08:35:59 AM UTC 24 1926903018 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access.1319048603 Sep 18 08:34:57 AM UTC 24 Sep 18 08:36:28 AM UTC 24 1159800916 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.365362044 Sep 18 08:35:09 AM UTC 24 Sep 18 08:36:39 AM UTC 24 458079703 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.2205639275 Sep 18 08:36:39 AM UTC 24 Sep 18 08:36:41 AM UTC 24 102126254 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.3436269539 Sep 18 08:36:42 AM UTC 24 Sep 18 08:36:50 AM UTC 24 79374272 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.2942880266 Sep 18 08:32:04 AM UTC 24 Sep 18 08:36:52 AM UTC 24 3061598836 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.1009951906 Sep 18 08:36:50 AM UTC 24 Sep 18 08:36:55 AM UTC 24 645071810 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.2984399990 Sep 18 08:25:46 AM UTC 24 Sep 18 08:36:57 AM UTC 24 12964708558 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_alert_test.1604494915 Sep 18 08:36:58 AM UTC 24 Sep 18 08:36:59 AM UTC 24 18411107 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.3918571868 Sep 18 08:33:31 AM UTC 24 Sep 18 08:37:12 AM UTC 24 15915088832 ps
T133 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_regwen.4270990651 Sep 18 08:24:19 AM UTC 24 Sep 18 08:37:15 AM UTC 24 10325668788 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.1152170558 Sep 18 08:30:07 AM UTC 24 Sep 18 08:37:33 AM UTC 24 64864002218 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.3231237016 Sep 18 08:23:44 AM UTC 24 Sep 18 08:37:34 AM UTC 24 5336493905 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access.77841953 Sep 18 08:37:35 AM UTC 24 Sep 18 08:37:49 AM UTC 24 1578512542 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_smoke.560861890 Sep 18 08:37:00 AM UTC 24 Sep 18 08:38:08 AM UTC 24 414709925 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.3739665353 Sep 18 08:27:00 AM UTC 24 Sep 18 08:38:09 AM UTC 24 2401078783 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_bijection.2861356145 Sep 18 08:37:16 AM UTC 24 Sep 18 08:38:14 AM UTC 24 760469868 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.2250842546 Sep 18 08:38:09 AM UTC 24 Sep 18 08:38:15 AM UTC 24 199120634 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.2438676910 Sep 18 08:38:15 AM UTC 24 Sep 18 08:38:28 AM UTC 24 747257841 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.402288053 Sep 18 08:38:08 AM UTC 24 Sep 18 08:38:43 AM UTC 24 171026906 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2906340285 Sep 18 08:33:23 AM UTC 24 Sep 18 08:38:45 AM UTC 24 1299596531 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.1064652166 Sep 18 08:38:46 AM UTC 24 Sep 18 08:38:48 AM UTC 24 93101930 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.188834827 Sep 18 08:38:49 AM UTC 24 Sep 18 08:39:02 AM UTC 24 139033756 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.3627032958 Sep 18 08:39:03 AM UTC 24 Sep 18 08:39:08 AM UTC 24 312665518 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_alert_test.1341584642 Sep 18 08:39:41 AM UTC 24 Sep 18 08:39:43 AM UTC 24 22984866 ps
T131 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_regwen.252544532 Sep 18 08:25:11 AM UTC 24 Sep 18 08:39:52 AM UTC 24 3806421699 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_smoke.2088793794 Sep 18 08:39:44 AM UTC 24 Sep 18 08:39:59 AM UTC 24 1824918298 ps
T138 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_regwen.119201262 Sep 18 08:34:17 AM UTC 24 Sep 18 08:40:01 AM UTC 24 1971351233 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.4057634785 Sep 18 08:36:53 AM UTC 24 Sep 18 08:40:02 AM UTC 24 3660995718 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.3526009253 Sep 18 08:34:56 AM UTC 24 Sep 18 08:40:04 AM UTC 24 8691635776 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access.211518026 Sep 18 08:40:03 AM UTC 24 Sep 18 08:40:08 AM UTC 24 1508178511 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.1042419037 Sep 18 08:29:42 AM UTC 24 Sep 18 08:40:13 AM UTC 24 3840332286 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.958954349 Sep 18 08:40:09 AM UTC 24 Sep 18 08:40:17 AM UTC 24 64071672 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.1570888716 Sep 18 08:40:18 AM UTC 24 Sep 18 08:40:21 AM UTC 24 206497119 ps
T251 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_bijection.4117633139 Sep 18 08:40:01 AM UTC 24 Sep 18 08:40:34 AM UTC 24 5691940029 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.2603994582 Sep 18 08:40:14 AM UTC 24 Sep 18 08:40:50 AM UTC 24 466471545 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3384889590 Sep 18 08:27:13 AM UTC 24 Sep 18 08:40:51 AM UTC 24 10033543990 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.4124603287 Sep 18 08:40:52 AM UTC 24 Sep 18 08:40:54 AM UTC 24 27981090 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3291288550 Sep 18 08:39:08 AM UTC 24 Sep 18 08:41:00 AM UTC 24 7965830510 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.2424970037 Sep 18 08:28:11 AM UTC 24 Sep 18 08:41:04 AM UTC 24 9582584819 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.3787701505 Sep 18 08:40:55 AM UTC 24 Sep 18 08:41:08 AM UTC 24 899400707 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.1106201653 Sep 18 08:41:02 AM UTC 24 Sep 18 08:41:11 AM UTC 24 1190063256 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_alert_test.3018673443 Sep 18 08:41:12 AM UTC 24 Sep 18 08:41:14 AM UTC 24 51200398 ps
T134 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.1410360791 Sep 18 08:29:56 AM UTC 24 Sep 18 08:41:19 AM UTC 24 5520211551 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.2032759041 Sep 18 08:24:46 AM UTC 24 Sep 18 08:41:25 AM UTC 24 12853925560 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_smoke.691573982 Sep 18 08:41:15 AM UTC 24 Sep 18 08:41:25 AM UTC 24 63975555 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.3149774412 Sep 18 08:34:38 AM UTC 24 Sep 18 08:41:38 AM UTC 24 2040342212 ps
T135 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_regwen.3150760885 Sep 18 08:26:21 AM UTC 24 Sep 18 08:41:49 AM UTC 24 4043651343 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_executable.2409628770 Sep 18 08:34:07 AM UTC 24 Sep 18 08:41:59 AM UTC 24 7651928179 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_executable.3467175780 Sep 18 08:36:00 AM UTC 24 Sep 18 08:42:01 AM UTC 24 5651807639 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.1244192470 Sep 18 08:25:09 AM UTC 24 Sep 18 08:42:16 AM UTC 24 15809265236 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.3205434555 Sep 18 08:42:02 AM UTC 24 Sep 18 08:42:20 AM UTC 24 642488167 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.3983309479 Sep 18 08:42:17 AM UTC 24 Sep 18 08:42:23 AM UTC 24 658341827 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.34482074 Sep 18 08:23:43 AM UTC 24 Sep 18 08:42:23 AM UTC 24 11733791849 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_bijection.2566801661 Sep 18 08:41:25 AM UTC 24 Sep 18 08:42:25 AM UTC 24 2319279238 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.890292425 Sep 18 08:42:26 AM UTC 24 Sep 18 08:42:28 AM UTC 24 78806975 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.3717430588 Sep 18 08:42:29 AM UTC 24 Sep 18 08:42:37 AM UTC 24 519766165 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.2972864742 Sep 18 08:42:38 AM UTC 24 Sep 18 08:42:47 AM UTC 24 577411384 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_executable.3224403353 Sep 18 08:28:14 AM UTC 24 Sep 18 08:42:49 AM UTC 24 16761334176 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.1600107753 Sep 18 08:32:43 AM UTC 24 Sep 18 08:42:50 AM UTC 24 49270128246 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.398974346 Sep 18 08:35:03 AM UTC 24 Sep 18 08:42:50 AM UTC 24 11103191268 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_alert_test.4002237084 Sep 18 08:42:50 AM UTC 24 Sep 18 08:42:52 AM UTC 24 15286128 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.2146614112 Sep 18 08:32:09 AM UTC 24 Sep 18 08:42:54 AM UTC 24 34245384444 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.221159866 Sep 18 08:37:34 AM UTC 24 Sep 18 08:42:57 AM UTC 24 7877107808 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.3165404518 Sep 18 08:33:42 AM UTC 24 Sep 18 08:42:59 AM UTC 24 8220634725 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_smoke.1524254268 Sep 18 08:42:51 AM UTC 24 Sep 18 08:43:02 AM UTC 24 295837513 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.714210020 Sep 18 08:42:01 AM UTC 24 Sep 18 08:43:09 AM UTC 24 134171576 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access.3172780933 Sep 18 08:41:38 AM UTC 24 Sep 18 08:43:09 AM UTC 24 4091412519 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.2336988391 Sep 18 08:43:11 AM UTC 24 Sep 18 08:43:22 AM UTC 24 1532084738 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access.1834408475 Sep 18 08:42:57 AM UTC 24 Sep 18 08:43:28 AM UTC 24 1261046689 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_bijection.500120791 Sep 18 08:42:52 AM UTC 24 Sep 18 08:43:34 AM UTC 24 6944953430 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.367246572 Sep 18 08:31:09 AM UTC 24 Sep 18 08:48:21 AM UTC 24 21944341414 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.1879305602 Sep 18 08:43:02 AM UTC 24 Sep 18 08:43:48 AM UTC 24 119668214 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.407943916 Sep 18 08:43:49 AM UTC 24 Sep 18 08:43:51 AM UTC 24 25687001 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.2574595215 Sep 18 08:40:02 AM UTC 24 Sep 18 08:44:05 AM UTC 24 3910415740 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.3589295733 Sep 18 08:34:05 AM UTC 24 Sep 18 08:44:08 AM UTC 24 12895354054 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.601424659 Sep 18 08:43:52 AM UTC 24 Sep 18 08:44:09 AM UTC 24 254211074 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_executable.320532188 Sep 18 08:38:29 AM UTC 24 Sep 18 08:44:10 AM UTC 24 26699613211 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.1799644893 Sep 18 08:44:05 AM UTC 24 Sep 18 08:44:11 AM UTC 24 92416449 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_alert_test.2232507599 Sep 18 08:44:11 AM UTC 24 Sep 18 08:44:13 AM UTC 24 41144596 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.1896446029 Sep 18 08:43:10 AM UTC 24 Sep 18 08:44:21 AM UTC 24 279836928 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3341430610 Sep 18 08:44:08 AM UTC 24 Sep 18 08:44:21 AM UTC 24 439574631 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.2911990414 Sep 18 08:40:05 AM UTC 24 Sep 18 08:44:22 AM UTC 24 31588213945 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_smoke.3680085984 Sep 18 08:44:12 AM UTC 24 Sep 18 08:44:31 AM UTC 24 675664774 ps
T136 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.1059393535 Sep 18 08:30:35 AM UTC 24 Sep 18 08:44:34 AM UTC 24 39295643158 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access.1891931392 Sep 18 08:44:23 AM UTC 24 Sep 18 08:44:41 AM UTC 24 2463057448 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_regwen.2672106464 Sep 18 08:42:24 AM UTC 24 Sep 18 08:44:44 AM UTC 24 3781998831 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.3765770679 Sep 18 08:44:45 AM UTC 24 Sep 18 08:44:53 AM UTC 24 1648657976 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.3250390925 Sep 18 08:44:42 AM UTC 24 Sep 18 08:44:57 AM UTC 24 116824763 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.3217061068 Sep 18 08:40:22 AM UTC 24 Sep 18 08:45:02 AM UTC 24 1482122453 ps
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