Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	151991162	1			T1	1448		T2	110224		T4	112
instr_valid_dis	118854350	1			T1	1448		T2	110224		T4	112
instr_en	25198579	1			T16	684		T21	1504		T22	103674

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10821499	1			T21	1504		T22	66		T18	19640
sram_ifetch_valid_disable	118551014	1			T1	1448		T2	110224		T4	112
sram_ifetch_enable	22618649	1			T16	684		T137	18666		T47	17252

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	151991162	1			T1	1448		T2	110224		T4	112
hw_debug_en_valid_off	118435638	1			T1	1448		T2	110224		T4	112
hw_debug_en_on	23133182	1			T16	684		T17	40076		T22	115792

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	118551014	1			T1	1448		T2	110224		T4	112
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	104977650	1			T1	1448		T2	110224		T4	112
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	10517006	1			T22	103674		T137	8778		T43	19658
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4277008	1			T18	19640		T106	5536		T146	14580
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2051254	1			T18	19640		T106	5536		T146	14580
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1687324	1			T143	18634		T138	95128		T161	38782
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4657157	1			T22	66		T43	56338		T102	6446
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1578220	1			T22	66		T43	56338		T142	9466
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2639847	1			T140	13974		T148	30630		T162	25566
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9133878	1			T17	40076		T22	115726		T137	44938
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3453056	1			T17	40076		T22	12052		T102	28704
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4482396	1			T22	103674		T140	200		T148	11018

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9448384	1			T16	684		T45	19220		T142	24602
lc_exec_en	9342147	1			T16	684		T43	13484		T45	43525
valid_exec_dis	114249428	1			T1	1448		T2	110224		T4	112
invalid_exec_dis	33440148	1			T16	684		T21	1504		T22	66