Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.29 99.22 95.11 99.72 100.00 96.31 99.12 98.54


Total tests in report: 1031
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
68.99 68.99 89.48 89.48 68.25 68.25 89.29 89.29 23.81 23.81 77.50 77.50 93.27 93.27 41.32 41.32 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.371318538
88.63 19.64 95.74 6.26 81.52 13.27 91.99 2.70 90.48 66.67 88.00 10.50 95.17 1.90 77.51 36.20 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.1106228158
92.52 3.89 98.00 2.26 85.19 3.67 96.60 4.61 100.00 9.52 92.50 4.50 95.46 0.29 79.89 2.38 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.1922410114
93.78 1.26 98.26 0.26 87.68 2.49 96.60 0.00 100.00 0.00 94.00 1.50 95.46 0.00 84.46 4.57 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_regwen.4231368000
94.74 0.96 98.61 0.35 89.93 2.25 97.71 1.11 100.00 0.00 95.50 1.50 96.05 0.59 85.37 0.91 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.3641516007
95.48 0.74 98.61 0.00 90.52 0.59 97.71 0.00 100.00 0.00 95.50 0.00 96.05 0.00 89.95 4.57 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2864052326
96.10 0.63 99.13 0.52 91.35 0.83 97.78 0.07 100.00 0.00 96.50 1.00 96.93 0.88 91.04 1.10 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.1944639996
96.44 0.34 99.13 0.00 91.47 0.12 98.75 0.97 100.00 0.00 96.50 0.00 96.93 0.00 92.32 1.28 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.67335417
96.68 0.24 99.13 0.00 91.47 0.00 98.75 0.00 100.00 0.00 96.50 0.00 96.93 0.00 93.97 1.65 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.385315981
96.88 0.20 99.13 0.00 91.47 0.00 98.75 0.00 100.00 0.00 96.50 0.00 97.07 0.15 95.25 1.28 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.2605003053
97.06 0.18 99.13 0.00 91.47 0.00 98.82 0.07 100.00 0.00 96.50 0.00 98.24 1.17 95.25 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.4222016656
97.22 0.16 99.13 0.00 91.47 0.00 98.82 0.00 100.00 0.00 96.50 0.00 98.24 0.00 96.34 1.10 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2575039272
97.35 0.13 99.22 0.09 91.47 0.00 99.65 0.83 100.00 0.00 96.50 0.00 98.24 0.00 96.34 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.2748242790
97.48 0.13 99.22 0.00 91.47 0.00 99.65 0.00 100.00 0.00 96.50 0.00 98.98 0.73 96.53 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1406947379
97.58 0.10 99.22 0.00 91.47 0.00 99.65 0.00 100.00 0.00 96.50 0.00 98.98 0.00 97.26 0.73 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.4027880133
97.66 0.08 99.22 0.00 91.47 0.00 99.65 0.00 100.00 0.00 96.50 0.00 98.98 0.00 97.81 0.55 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_executable.2629235839
97.72 0.06 99.22 0.00 91.82 0.36 99.72 0.07 100.00 0.00 96.50 0.00 98.98 0.00 97.81 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.2443287095
97.77 0.05 99.22 0.00 91.82 0.00 99.72 0.00 100.00 0.00 96.50 0.00 98.98 0.00 98.17 0.37 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2331616180
97.80 0.03 99.22 0.00 91.82 0.00 99.72 0.00 100.00 0.00 96.50 0.00 98.98 0.00 98.35 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1076483679
97.83 0.03 99.22 0.00 91.82 0.00 99.72 0.00 100.00 0.00 96.50 0.00 98.98 0.00 98.54 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3833591680
97.85 0.02 99.22 0.00 91.82 0.00 99.72 0.00 100.00 0.00 96.50 0.00 99.12 0.15 98.54 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3059334385

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3481338895
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3969328343
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3456022612
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1265423314
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1675578614
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2759839307
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1401890809
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3997048850
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3717868072
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.191782051
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3975689791
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.32929644
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1767453108
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3536491799
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1361867890
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3309308441
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3964303058
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2285684959
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.42797146
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.67764612
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1422994081
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3800313395
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2491049706
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3149537946
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4148270804
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3834914431
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1972530740
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2765124241
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.368833802
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1186297649
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.380264126
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3454109891
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.98135161
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.4254705574
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1898314089
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.998819507
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2294740298
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3057913225
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.419822596
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1969300043
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3174444778
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1958281412
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3791469518
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1271131893
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2661909803
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3645742802
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1178008132
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3596438350
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2618219088
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4119952498
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.418641325
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4066733884
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.764261008
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2372405440
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1202085607
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.739685060
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.146270015
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2865105101
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3111757635
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1822767891
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.4020069886
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.320397910
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2139980568
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2800867178
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2460317200
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2603374187
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.504518128
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3130664838
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2425692283
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2918323403
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2339878850
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.672433323
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3350781437
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1281140646
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.967294089
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2340959481
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3599179372
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.164929857
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.701059684
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.4062447328
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1492168223
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2566472231
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.833518936
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2361321064
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.507247774
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.624238356
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2808736035
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.921575996
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3308404651
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/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.2697796925
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/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.1149512504
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/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.1346944053
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/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.343897960
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.4166075053
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.843688679
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.3999469420
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.3347105880
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/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.680757339
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/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.4037508662
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.703439113
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/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.3359514724
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.1589909306



Total test records in report: 1031
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.2465514969 Sep 24 09:39:43 PM UTC 24 Sep 24 09:39:46 PM UTC 24 410908931 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.371318538 Sep 24 09:39:42 PM UTC 24 Sep 24 09:43:19 PM UTC 24 8489372684 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.2748242790 Sep 24 09:39:50 PM UTC 24 Sep 24 09:39:52 PM UTC 24 28259394 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.2443287095 Sep 24 09:39:50 PM UTC 24 Sep 24 09:39:52 PM UTC 24 44174941 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.3769226457 Sep 24 09:39:51 PM UTC 24 Sep 24 09:39:53 PM UTC 24 167833761 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.3222372376 Sep 24 09:39:51 PM UTC 24 Sep 24 09:39:53 PM UTC 24 98212919 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_smoke.1260883056 Sep 24 09:39:42 PM UTC 24 Sep 24 09:39:54 PM UTC 24 168427498 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.657850758 Sep 24 09:39:50 PM UTC 24 Sep 24 09:39:55 PM UTC 24 422995198 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_alert_test.4167142141 Sep 24 09:39:54 PM UTC 24 Sep 24 09:39:57 PM UTC 24 71047982 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.2461074756 Sep 24 09:39:50 PM UTC 24 Sep 24 09:39:58 PM UTC 24 174944667 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.1944639996 Sep 24 09:39:54 PM UTC 24 Sep 24 09:40:00 PM UTC 24 100836541 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.965596624 Sep 24 09:39:54 PM UTC 24 Sep 24 09:40:00 PM UTC 24 1196477546 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.1922410114 Sep 24 09:39:51 PM UTC 24 Sep 24 09:40:00 PM UTC 24 960483992 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1947964955 Sep 24 09:39:50 PM UTC 24 Sep 24 09:40:01 PM UTC 24 229735173 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.1119257054 Sep 24 09:39:51 PM UTC 24 Sep 24 09:40:02 PM UTC 24 134192871 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.3163050823 Sep 24 09:39:56 PM UTC 24 Sep 24 09:40:02 PM UTC 24 1027942217 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.2705138472 Sep 24 09:40:01 PM UTC 24 Sep 24 09:40:04 PM UTC 24 46316295 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access.2729179348 Sep 24 09:39:56 PM UTC 24 Sep 24 09:40:08 PM UTC 24 368709105 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.660775682 Sep 24 09:39:50 PM UTC 24 Sep 24 09:40:08 PM UTC 24 3268188196 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.3157510430 Sep 24 09:40:02 PM UTC 24 Sep 24 09:40:08 PM UTC 24 100666927 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access.382064251 Sep 24 09:39:51 PM UTC 24 Sep 24 09:40:09 PM UTC 24 307107687 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_alert_test.1305804102 Sep 24 09:40:09 PM UTC 24 Sep 24 09:40:11 PM UTC 24 30631774 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.3290043215 Sep 24 09:39:51 PM UTC 24 Sep 24 09:40:12 PM UTC 24 83136363 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.3384231719 Sep 24 09:40:09 PM UTC 24 Sep 24 09:40:13 PM UTC 24 402436242 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.4164392565 Sep 24 09:39:56 PM UTC 24 Sep 24 09:40:13 PM UTC 24 88014934 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.1778441451 Sep 24 09:39:43 PM UTC 24 Sep 24 09:40:14 PM UTC 24 426451669 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.2281146647 Sep 24 09:40:01 PM UTC 24 Sep 24 09:40:17 PM UTC 24 350083409 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_smoke.557189330 Sep 24 09:40:09 PM UTC 24 Sep 24 09:40:19 PM UTC 24 245038215 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.2838131655 Sep 24 09:43:10 PM UTC 24 Sep 24 09:43:12 PM UTC 24 86939397 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.680780928 Sep 24 09:40:13 PM UTC 24 Sep 24 09:40:20 PM UTC 24 112774362 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.1220567512 Sep 24 09:40:12 PM UTC 24 Sep 24 09:40:20 PM UTC 24 52964910 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access.3741954386 Sep 24 09:39:43 PM UTC 24 Sep 24 09:40:21 PM UTC 24 456826756 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.2094950130 Sep 24 09:40:19 PM UTC 24 Sep 24 09:40:22 PM UTC 24 89015190 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.1847847323 Sep 24 09:40:14 PM UTC 24 Sep 24 09:40:27 PM UTC 24 2248088163 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.4219754877 Sep 24 09:40:23 PM UTC 24 Sep 24 09:40:28 PM UTC 24 330448043 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.2369980572 Sep 24 09:40:24 PM UTC 24 Sep 24 09:40:29 PM UTC 24 441479896 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_alert_test.1894763152 Sep 24 09:40:28 PM UTC 24 Sep 24 09:40:31 PM UTC 24 81787898 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.1563945531 Sep 24 09:40:23 PM UTC 24 Sep 24 09:40:33 PM UTC 24 251463935 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_smoke.1090249059 Sep 24 09:39:50 PM UTC 24 Sep 24 09:40:33 PM UTC 24 1999641098 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_smoke.1298559557 Sep 24 09:40:28 PM UTC 24 Sep 24 09:40:40 PM UTC 24 706378700 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.3373403330 Sep 24 09:39:56 PM UTC 24 Sep 24 09:40:44 PM UTC 24 1461105890 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.3574246654 Sep 24 09:39:43 PM UTC 24 Sep 24 09:40:52 PM UTC 24 134601605 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.2384585925 Sep 24 09:40:44 PM UTC 24 Sep 24 09:40:52 PM UTC 24 1156474001 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1406947379 Sep 24 09:39:54 PM UTC 24 Sep 24 09:41:03 PM UTC 24 1102239828 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_bijection.1348351739 Sep 24 09:39:42 PM UTC 24 Sep 24 09:41:05 PM UTC 24 18000237296 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_bijection.484958161 Sep 24 09:39:54 PM UTC 24 Sep 24 09:41:06 PM UTC 24 1057832720 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.4241829837 Sep 24 09:41:07 PM UTC 24 Sep 24 09:41:09 PM UTC 24 54892081 ps
T117 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access.3691644216 Sep 24 09:40:10 PM UTC 24 Sep 24 09:41:11 PM UTC 24 625062242 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.3857450692 Sep 24 09:41:07 PM UTC 24 Sep 24 09:41:16 PM UTC 24 733493723 ps
T118 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_bijection.3451371747 Sep 24 09:40:10 PM UTC 24 Sep 24 09:41:16 PM UTC 24 9417253963 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.129036086 Sep 24 09:41:10 PM UTC 24 Sep 24 09:41:16 PM UTC 24 783293265 ps
T119 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_bijection.1902346688 Sep 24 09:39:50 PM UTC 24 Sep 24 09:41:17 PM UTC 24 15951645226 ps
T120 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_alert_test.2689062959 Sep 24 09:41:17 PM UTC 24 Sep 24 09:41:19 PM UTC 24 14524434 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.3641516007 Sep 24 09:41:17 PM UTC 24 Sep 24 09:41:22 PM UTC 24 483487237 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.1106228158 Sep 24 09:40:23 PM UTC 24 Sep 24 09:41:22 PM UTC 24 5368824890 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_smoke.4286655793 Sep 24 09:41:18 PM UTC 24 Sep 24 09:41:24 PM UTC 24 78916708 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access.3451652471 Sep 24 09:41:24 PM UTC 24 Sep 24 09:41:31 PM UTC 24 893608941 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_smoke.1435282278 Sep 24 09:39:54 PM UTC 24 Sep 24 09:41:38 PM UTC 24 812096117 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_bijection.1841928513 Sep 24 09:40:31 PM UTC 24 Sep 24 09:41:43 PM UTC 24 2894064809 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.526759107 Sep 24 09:41:39 PM UTC 24 Sep 24 09:41:46 PM UTC 24 262857965 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_regwen.3691977720 Sep 24 09:39:51 PM UTC 24 Sep 24 09:41:53 PM UTC 24 2132779929 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access.3964825953 Sep 24 09:40:35 PM UTC 24 Sep 24 09:42:00 PM UTC 24 966921971 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.1751147773 Sep 24 09:42:00 PM UTC 24 Sep 24 09:42:03 PM UTC 24 44665530 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_executable.3539085628 Sep 24 09:39:59 PM UTC 24 Sep 24 09:42:09 PM UTC 24 5092615959 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_bijection.1077596403 Sep 24 09:41:22 PM UTC 24 Sep 24 09:42:10 PM UTC 24 550815441 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.3707446658 Sep 24 09:42:03 PM UTC 24 Sep 24 09:42:11 PM UTC 24 301507625 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.4027880133 Sep 24 09:40:41 PM UTC 24 Sep 24 09:42:12 PM UTC 24 170639592 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.4175135425 Sep 24 09:41:32 PM UTC 24 Sep 24 09:42:14 PM UTC 24 188853236 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_alert_test.2159064364 Sep 24 09:42:13 PM UTC 24 Sep 24 09:42:15 PM UTC 24 14154675 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.3726200800 Sep 24 09:42:09 PM UTC 24 Sep 24 09:42:15 PM UTC 24 1831265761 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.1251081975 Sep 24 09:40:41 PM UTC 24 Sep 24 09:42:17 PM UTC 24 142303092 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_smoke.469662464 Sep 24 09:42:15 PM UTC 24 Sep 24 09:42:26 PM UTC 24 499769113 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_executable.4234577882 Sep 24 09:39:51 PM UTC 24 Sep 24 09:42:29 PM UTC 24 11739122978 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access.1720201509 Sep 24 09:42:25 PM UTC 24 Sep 24 09:42:34 PM UTC 24 893224726 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.1801215346 Sep 24 09:40:14 PM UTC 24 Sep 24 09:42:41 PM UTC 24 1367079995 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.2907381198 Sep 24 09:42:38 PM UTC 24 Sep 24 09:42:43 PM UTC 24 1427683437 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_regwen.3615345849 Sep 24 09:41:54 PM UTC 24 Sep 24 09:42:45 PM UTC 24 24670007793 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.845060700 Sep 24 09:42:29 PM UTC 24 Sep 24 09:43:09 PM UTC 24 102483350 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_bijection.1615500029 Sep 24 09:42:16 PM UTC 24 Sep 24 09:43:15 PM UTC 24 3791658974 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.803301191 Sep 24 09:41:35 PM UTC 24 Sep 24 09:43:16 PM UTC 24 603767064 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.3565257356 Sep 24 09:43:13 PM UTC 24 Sep 24 09:43:23 PM UTC 24 1369218388 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.1579872763 Sep 24 09:43:16 PM UTC 24 Sep 24 09:43:25 PM UTC 24 156980062 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_alert_test.2652159965 Sep 24 09:43:25 PM UTC 24 Sep 24 09:43:27 PM UTC 24 52816901 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2171425367 Sep 24 09:43:16 PM UTC 24 Sep 24 09:43:41 PM UTC 24 665212790 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.4219881408 Sep 24 09:39:42 PM UTC 24 Sep 24 09:43:42 PM UTC 24 23510471753 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.3563962720 Sep 24 09:39:56 PM UTC 24 Sep 24 09:43:43 PM UTC 24 4156766333 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.290858939 Sep 24 09:43:27 PM UTC 24 Sep 24 09:43:46 PM UTC 24 309505337 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2952929060 Sep 24 09:42:11 PM UTC 24 Sep 24 09:43:47 PM UTC 24 884996484 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.3956951859 Sep 24 09:41:20 PM UTC 24 Sep 24 09:43:48 PM UTC 24 577119932 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.2577802323 Sep 24 09:43:48 PM UTC 24 Sep 24 09:43:51 PM UTC 24 114623647 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.85031375 Sep 24 09:39:51 PM UTC 24 Sep 24 09:43:53 PM UTC 24 2833110874 ps
T124 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.3937713375 Sep 24 09:43:48 PM UTC 24 Sep 24 09:43:59 PM UTC 24 2546338128 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.1618240169 Sep 24 09:42:35 PM UTC 24 Sep 24 09:44:07 PM UTC 24 144469163 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2041999297 Sep 24 09:40:02 PM UTC 24 Sep 24 09:44:08 PM UTC 24 1001465524 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.163848421 Sep 24 09:44:08 PM UTC 24 Sep 24 09:44:10 PM UTC 24 91343980 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.3488801054 Sep 24 09:43:43 PM UTC 24 Sep 24 09:44:13 PM UTC 24 992131099 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.1130535648 Sep 24 09:44:09 PM UTC 24 Sep 24 09:44:18 PM UTC 24 479251832 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.2953082923 Sep 24 09:44:11 PM UTC 24 Sep 24 09:44:21 PM UTC 24 174650124 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.3684495655 Sep 24 09:43:47 PM UTC 24 Sep 24 09:44:22 PM UTC 24 93925643 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.377166075 Sep 24 09:44:21 PM UTC 24 Sep 24 09:44:23 PM UTC 24 18919919 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.834422244 Sep 24 09:40:10 PM UTC 24 Sep 24 09:44:33 PM UTC 24 8672218583 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.1536539786 Sep 24 09:44:01 PM UTC 24 Sep 24 09:44:41 PM UTC 24 6685648927 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.67335417 Sep 24 09:41:12 PM UTC 24 Sep 24 09:44:42 PM UTC 24 3036882368 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.68708039 Sep 24 09:43:42 PM UTC 24 Sep 24 09:44:48 PM UTC 24 13757154834 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.3091867445 Sep 24 09:40:35 PM UTC 24 Sep 24 09:45:11 PM UTC 24 12635578918 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.2828347431 Sep 24 09:44:44 PM UTC 24 Sep 24 09:45:15 PM UTC 24 2053549758 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.843688679 Sep 24 09:44:33 PM UTC 24 Sep 24 09:45:18 PM UTC 24 474170440 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.3999469420 Sep 24 09:45:16 PM UTC 24 Sep 24 09:45:24 PM UTC 24 1047406942 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.4148120553 Sep 24 09:39:43 PM UTC 24 Sep 24 09:45:26 PM UTC 24 49732737977 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.3347105880 Sep 24 09:44:52 PM UTC 24 Sep 24 09:45:31 PM UTC 24 102258230 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.3799235504 Sep 24 09:44:22 PM UTC 24 Sep 24 09:45:32 PM UTC 24 2439459803 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.4024349631 Sep 24 09:45:32 PM UTC 24 Sep 24 09:45:34 PM UTC 24 101809448 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.2848972172 Sep 24 09:45:33 PM UTC 24 Sep 24 09:45:40 PM UTC 24 138960086 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.2605003053 Sep 24 09:40:10 PM UTC 24 Sep 24 09:45:45 PM UTC 24 29721016021 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.640007651 Sep 24 09:44:14 PM UTC 24 Sep 24 09:45:45 PM UTC 24 1410331311 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.4155259142 Sep 24 09:45:35 PM UTC 24 Sep 24 09:45:45 PM UTC 24 185722317 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.4285990602 Sep 24 09:39:43 PM UTC 24 Sep 24 09:45:46 PM UTC 24 4409502912 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.4166075053 Sep 24 09:45:46 PM UTC 24 Sep 24 09:45:48 PM UTC 24 30199994 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.703439113 Sep 24 09:45:46 PM UTC 24 Sep 24 09:45:51 PM UTC 24 117938808 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.2515397065 Sep 24 09:40:31 PM UTC 24 Sep 24 09:46:00 PM UTC 24 11361099252 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.3645494206 Sep 24 09:41:27 PM UTC 24 Sep 24 09:46:09 PM UTC 24 36012040478 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.680757339 Sep 24 09:45:59 PM UTC 24 Sep 24 09:46:11 PM UTC 24 456181651 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3222856392 Sep 24 09:45:41 PM UTC 24 Sep 24 09:46:20 PM UTC 24 3703640941 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.3922381602 Sep 24 09:45:12 PM UTC 24 Sep 24 09:46:24 PM UTC 24 201301544 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.3469747857 Sep 24 09:46:21 PM UTC 24 Sep 24 09:46:27 PM UTC 24 487169532 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.4241486917 Sep 24 09:39:54 PM UTC 24 Sep 24 09:46:45 PM UTC 24 11401298413 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.1589909306 Sep 24 09:46:12 PM UTC 24 Sep 24 09:46:50 PM UTC 24 1022045712 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.959017185 Sep 24 09:46:51 PM UTC 24 Sep 24 09:46:53 PM UTC 24 50506945 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.4100399048 Sep 24 09:41:23 PM UTC 24 Sep 24 09:46:56 PM UTC 24 16026557924 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.441580068 Sep 24 09:46:54 PM UTC 24 Sep 24 09:47:03 PM UTC 24 229692637 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.2534612557 Sep 24 09:46:57 PM UTC 24 Sep 24 09:47:05 PM UTC 24 716834713 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.1345759756 Sep 24 09:45:49 PM UTC 24 Sep 24 09:47:06 PM UTC 24 2107456012 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.1800240807 Sep 24 09:47:06 PM UTC 24 Sep 24 09:47:08 PM UTC 24 18639594 ps
T212 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_smoke.879285315 Sep 24 09:47:09 PM UTC 24 Sep 24 09:47:12 PM UTC 24 42461346 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.2633430012 Sep 24 09:40:33 PM UTC 24 Sep 24 09:47:20 PM UTC 24 3668356354 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.4185878771 Sep 24 09:39:50 PM UTC 24 Sep 24 09:47:31 PM UTC 24 7539364844 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_executable.1157155964 Sep 24 09:41:47 PM UTC 24 Sep 24 09:47:39 PM UTC 24 844901005 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.2721952683 Sep 24 09:39:51 PM UTC 24 Sep 24 09:47:46 PM UTC 24 3643883815 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.222506296 Sep 24 09:39:56 PM UTC 24 Sep 24 09:47:49 PM UTC 24 33687488312 ps
T217 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_bijection.349820685 Sep 24 09:47:21 PM UTC 24 Sep 24 09:47:51 PM UTC 24 6112490802 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.1617998107 Sep 24 09:47:50 PM UTC 24 Sep 24 09:47:53 PM UTC 24 126436325 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.1598995363 Sep 24 09:46:10 PM UTC 24 Sep 24 09:47:59 PM UTC 24 677093782 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.1309441891 Sep 24 09:47:52 PM UTC 24 Sep 24 09:47:59 PM UTC 24 103395389 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.1884646625 Sep 24 09:47:54 PM UTC 24 Sep 24 09:48:06 PM UTC 24 1595953528 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.486522737 Sep 24 09:45:28 PM UTC 24 Sep 24 09:48:14 PM UTC 24 5457233942 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.1801203399 Sep 24 09:45:47 PM UTC 24 Sep 24 09:48:15 PM UTC 24 3119807314 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.3627376278 Sep 24 09:48:16 PM UTC 24 Sep 24 09:48:18 PM UTC 24 29714166 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.1149512504 Sep 24 09:43:53 PM UTC 24 Sep 24 09:48:20 PM UTC 24 14396279097 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.1691294524 Sep 24 09:48:16 PM UTC 24 Sep 24 09:48:25 PM UTC 24 1308174328 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.1053084187 Sep 24 09:48:19 PM UTC 24 Sep 24 09:48:28 PM UTC 24 159217271 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_alert_test.2566413263 Sep 24 09:48:28 PM UTC 24 Sep 24 09:48:30 PM UTC 24 14667027 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_smoke.742954726 Sep 24 09:48:31 PM UTC 24 Sep 24 09:48:34 PM UTC 24 34812666 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access.1317740393 Sep 24 09:47:40 PM UTC 24 Sep 24 09:48:59 PM UTC 24 702139228 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.3359514724 Sep 24 09:45:52 PM UTC 24 Sep 24 09:49:03 PM UTC 24 1676173893 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.70695693 Sep 24 09:42:42 PM UTC 24 Sep 24 09:49:13 PM UTC 24 11345104021 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.852668530 Sep 24 09:43:43 PM UTC 24 Sep 24 09:49:16 PM UTC 24 2509859203 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.853318188 Sep 24 09:47:04 PM UTC 24 Sep 24 09:49:29 PM UTC 24 7456619034 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.2618221627 Sep 24 09:47:59 PM UTC 24 Sep 24 09:49:35 PM UTC 24 377808874 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.2039062063 Sep 24 09:40:52 PM UTC 24 Sep 24 09:49:39 PM UTC 24 3212443972 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.1349155475 Sep 24 09:42:26 PM UTC 24 Sep 24 09:49:46 PM UTC 24 32055411999 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.4270026274 Sep 24 09:42:17 PM UTC 24 Sep 24 09:49:48 PM UTC 24 7813025930 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.550798404 Sep 24 09:49:40 PM UTC 24 Sep 24 09:49:48 PM UTC 24 528471922 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.3270031577 Sep 24 09:49:49 PM UTC 24 Sep 24 09:49:51 PM UTC 24 36524158 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access.1270157346 Sep 24 09:49:15 PM UTC 24 Sep 24 09:49:57 PM UTC 24 1311869983 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_bijection.3751210284 Sep 24 09:55:52 PM UTC 24 Sep 24 09:56:36 PM UTC 24 537389069 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.1818662722 Sep 24 09:49:52 PM UTC 24 Sep 24 09:50:00 PM UTC 24 1244224162 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.1841221751 Sep 24 09:49:36 PM UTC 24 Sep 24 09:50:02 PM UTC 24 212878480 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.2067648567 Sep 24 09:49:58 PM UTC 24 Sep 24 09:50:03 PM UTC 24 373797023 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_alert_test.2876789090 Sep 24 09:50:04 PM UTC 24 Sep 24 09:50:06 PM UTC 24 26581498 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_smoke.590169897 Sep 24 09:50:07 PM UTC 24 Sep 24 09:50:15 PM UTC 24 1092555253 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.250080153 Sep 24 09:43:28 PM UTC 24 Sep 24 09:50:17 PM UTC 24 17637812568 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3613431184 Sep 24 09:50:00 PM UTC 24 Sep 24 09:50:29 PM UTC 24 1908058829 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_bijection.3983400143 Sep 24 09:48:59 PM UTC 24 Sep 24 09:50:39 PM UTC 24 5716894599 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_bijection.1318392804 Sep 24 09:50:18 PM UTC 24 Sep 24 09:50:44 PM UTC 24 4735636835 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access.839707586 Sep 24 09:50:40 PM UTC 24 Sep 24 09:50:53 PM UTC 24 1565454686 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.1269887171 Sep 24 09:47:32 PM UTC 24 Sep 24 09:50:54 PM UTC 24 36926664625 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.3295460860 Sep 24 09:50:55 PM UTC 24 Sep 24 09:51:01 PM UTC 24 63180459 ps
T251 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.1102888723 Sep 24 09:49:30 PM UTC 24 Sep 24 09:51:11 PM UTC 24 499688160 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.1999741666 Sep 24 09:51:01 PM UTC 24 Sep 24 09:51:13 PM UTC 24 657327086 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.10836108 Sep 24 09:48:21 PM UTC 24 Sep 24 09:51:17 PM UTC 24 2842897836 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.2164544565 Sep 24 09:40:10 PM UTC 24 Sep 24 09:51:17 PM UTC 24 28911090474 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.3683104985 Sep 24 09:51:18 PM UTC 24 Sep 24 09:51:20 PM UTC 24 130336371 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.3884973073 Sep 24 09:44:42 PM UTC 24 Sep 24 09:51:22 PM UTC 24 7460241242 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.1069021199 Sep 24 09:51:21 PM UTC 24 Sep 24 09:51:31 PM UTC 24 344153618 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.3440419856 Sep 24 09:51:23 PM UTC 24 Sep 24 09:51:31 PM UTC 24 176684419 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.1289080440 Sep 24 09:51:11 PM UTC 24 Sep 24 09:51:38 PM UTC 24 1933989516 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_alert_test.2072989580 Sep 24 09:51:39 PM UTC 24 Sep 24 09:51:41 PM UTC 24 44360327 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.2553587663 Sep 24 09:50:54 PM UTC 24 Sep 24 09:51:45 PM UTC 24 393471245 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_regwen.3374596358 Sep 24 09:42:46 PM UTC 24 Sep 24 09:51:52 PM UTC 24 1803191310 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_smoke.822594223 Sep 24 09:51:42 PM UTC 24 Sep 24 09:51:59 PM UTC 24 81626726 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_regwen.4231368000 Sep 24 09:39:50 PM UTC 24 Sep 24 09:51:59 PM UTC 24 8690850446 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.171744543 Sep 24 09:51:32 PM UTC 24 Sep 24 09:52:05 PM UTC 24 504336169 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.3191362200 Sep 24 09:43:44 PM UTC 24 Sep 24 09:52:09 PM UTC 24 36362662051 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.2427939062 Sep 24 09:52:11 PM UTC 24 Sep 24 09:52:14 PM UTC 24 35333766 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_bijection.2961639618 Sep 24 09:51:53 PM UTC 24 Sep 24 09:52:25 PM UTC 24 1369852316 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.2537218423 Sep 24 09:52:15 PM UTC 24 Sep 24 09:52:28 PM UTC 24 577443403 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.1203642447 Sep 24 09:52:15 PM UTC 24 Sep 24 09:52:30 PM UTC 24 981845205 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_executable.3454484445 Sep 24 09:42:44 PM UTC 24 Sep 24 09:53:18 PM UTC 24 12089606392 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.3662924243 Sep 24 09:53:19 PM UTC 24 Sep 24 09:53:21 PM UTC 24 31327109 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_regwen.2840235273 Sep 24 09:49:49 PM UTC 24 Sep 24 09:53:29 PM UTC 24 7803797496 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.2527918341 Sep 24 09:53:22 PM UTC 24 Sep 24 09:53:29 PM UTC 24 71578567 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.2258304455 Sep 24 09:44:49 PM UTC 24 Sep 24 09:53:30 PM UTC 24 21984504658 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.4181379418 Sep 24 09:53:29 PM UTC 24 Sep 24 09:53:36 PM UTC 24 258589564 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_alert_test.3412622145 Sep 24 09:53:37 PM UTC 24 Sep 24 09:53:39 PM UTC 24 18268466 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.1196842573 Sep 24 09:47:47 PM UTC 24 Sep 24 09:53:47 PM UTC 24 27353134715 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.3685290653 Sep 24 09:39:57 PM UTC 24 Sep 24 09:53:47 PM UTC 24 5429748728 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access.1745657599 Sep 24 09:52:00 PM UTC 24 Sep 24 09:53:58 PM UTC 24 690121670 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.4274820243 Sep 24 09:46:01 PM UTC 24 Sep 24 09:54:10 PM UTC 24 13989989944 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_smoke.643978967 Sep 24 09:53:40 PM UTC 24 Sep 24 09:54:22 PM UTC 24 1559735593 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access.947234793 Sep 24 09:54:10 PM UTC 24 Sep 24 09:54:28 PM UTC 24 631879284 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_executable.1229572793 Sep 24 09:47:59 PM UTC 24 Sep 24 09:54:40 PM UTC 24 4265604383 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.100822136 Sep 24 09:49:05 PM UTC 24 Sep 24 09:54:59 PM UTC 24 6984100336 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_bijection.4003965500 Sep 24 09:53:48 PM UTC 24 Sep 24 09:54:59 PM UTC 24 2094953454 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.487024292 Sep 24 09:52:00 PM UTC 24 Sep 24 09:55:01 PM UTC 24 1322207495 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.884215880 Sep 24 09:49:17 PM UTC 24 Sep 24 09:55:09 PM UTC 24 3679612243 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.4199147701 Sep 24 09:55:00 PM UTC 24 Sep 24 09:55:15 PM UTC 24 3360902435 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.1642202997 Sep 24 09:55:16 PM UTC 24 Sep 24 09:55:19 PM UTC 24 52048311 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_executable.2550480739 Sep 24 09:39:50 PM UTC 24 Sep 24 09:55:28 PM UTC 24 2916064173 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.2896481363 Sep 24 09:54:30 PM UTC 24 Sep 24 09:55:33 PM UTC 24 429130879 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.3232133 Sep 24 09:55:19 PM UTC 24 Sep 24 09:55:35 PM UTC 24 1171283042 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.2710139476 Sep 24 09:55:29 PM UTC 24 Sep 24 09:55:38 PM UTC 24 767044708 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_alert_test.2603377217 Sep 24 09:55:39 PM UTC 24 Sep 24 09:55:41 PM UTC 24 184094398 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.4016969979 Sep 24 09:53:59 PM UTC 24 Sep 24 09:55:45 PM UTC 24 6500654126 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.2390318957 Sep 24 09:50:15 PM UTC 24 Sep 24 09:55:51 PM UTC 24 3626805762 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_smoke.552893371 Sep 24 09:55:42 PM UTC 24 Sep 24 09:55:57 PM UTC 24 262991751 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.1157976320 Sep 24 09:54:41 PM UTC 24 Sep 24 09:56:06 PM UTC 24 151163017 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.1500577951 Sep 24 09:50:31 PM UTC 24 Sep 24 09:56:28 PM UTC 24 3019963676 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.1942073594 Sep 24 09:44:24 PM UTC 24 Sep 24 09:56:32 PM UTC 24 15274969319 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.3073689613 Sep 24 09:42:16 PM UTC 24 Sep 24 09:56:33 PM UTC 24 9535572383 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access.1482102221 Sep 24 09:56:07 PM UTC 24 Sep 24 09:56:35 PM UTC 24 633893743 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_executable.105525104 Sep 24 09:52:28 PM UTC 24 Sep 24 09:56:37 PM UTC 24 1989458761 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.401360908 Sep 24 09:56:34 PM UTC 24 Sep 24 09:56:45 PM UTC 24 121420460 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.2720191823 Sep 24 09:56:36 PM UTC 24 Sep 24 09:56:52 PM UTC 24 750925427 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.295240878 Sep 24 09:56:52 PM UTC 24 Sep 24 09:56:55 PM UTC 24 41662866 ps
T138 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.385315981 Sep 24 09:45:26 PM UTC 24 Sep 24 09:57:01 PM UTC 24 78615011104 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.3397902373 Sep 24 09:57:02 PM UTC 24 Sep 24 09:57:10 PM UTC 24 93779322 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.1543742279 Sep 24 09:56:56 PM UTC 24 Sep 24 09:57:10 PM UTC 24 194648927 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.4200216004 Sep 24 09:56:33 PM UTC 24 Sep 24 09:57:12 PM UTC 24 217012878 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_regwen.3945512692 Sep 24 09:48:08 PM UTC 24 Sep 24 09:57:15 PM UTC 24 8796418516 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_alert_test.3468209916 Sep 24 09:57:13 PM UTC 24 Sep 24 09:57:15 PM UTC 24 16369424 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2702906824 Sep 24 09:57:11 PM UTC 24 Sep 24 09:57:20 PM UTC 24 271959307 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_smoke.2742861097 Sep 24 09:57:16 PM UTC 24 Sep 24 09:57:38 PM UTC 24 1179202652 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_bijection.669183481 Sep 24 09:57:21 PM UTC 24 Sep 24 09:58:01 PM UTC 24 3637546463 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access.4002572321 Sep 24 09:57:59 PM UTC 24 Sep 24 09:58:06 PM UTC 24 78500441 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.2760457342 Sep 24 09:54:22 PM UTC 24 Sep 24 09:58:09 PM UTC 24 5134243085 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.240840660 Sep 24 09:58:10 PM UTC 24 Sep 24 09:58:13 PM UTC 24 176877569 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.4047785329 Sep 24 09:41:44 PM UTC 24 Sep 24 09:58:15 PM UTC 24 12195082449 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.2827043757 Sep 24 09:58:13 PM UTC 24 Sep 24 09:58:20 PM UTC 24 352581694 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.590006617 Sep 24 09:52:26 PM UTC 24 Sep 24 09:58:47 PM UTC 24 1618671235 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.849997199 Sep 24 09:58:53 PM UTC 24 Sep 24 09:58:55 PM UTC 24 244887772 ps