Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	150185744	1			T1	1364		T4	1022		T5	4008
instr_valid_dis	118288741	1			T1	1364		T4	1022		T5	4008
instr_en	22993968	1			T26	9506		T27	6414		T18	382

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11583916	1			T26	6382		T27	6414		T29	5144
sram_ifetch_valid_disable	118172866	1			T1	1364		T4	1022		T5	4008
sram_ifetch_enable	20428962	1			T26	9506		T27	46		T28	19506

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	150185744	1			T1	1364		T4	1022		T5	4008
hw_debug_en_valid_off	116827417	1			T1	1364		T4	1022		T5	4008
hw_debug_en_on	23037323	1			T25	10348		T27	64590		T28	19506

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	118172866	1			T1	1364		T4	1022		T5	4008
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	104674143	1			T1	1364		T4	1022		T5	4008
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	10123730	1			T18	382		T19	41402		T20	62260
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4742724	1			T27	6414		T20	44550		T135	8588
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1878714	1			T143	3144		T140	117278		T156	170
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2117222	1			T27	6414		T20	44550		T135	8588
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4744071	1			T29	5144		T20	32616		T139	41562
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1794469	1			T140	23964		T157	88		T137	12362
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2137858	1			T29	5144		T20	32616		T139	41562
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9596889	1			T25	10348		T27	64544		T29	20446
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4414042	1			T25	10348		T27	64544		T29	20446
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3758917	1			T19	8550		T20	43436		T135	26680

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	7887137	1			T26	9506		T29	44044		T141	15270
lc_exec_en	8696363	1			T27	46		T28	19506		T29	90230
valid_exec_dis	113261644	1			T1	1364		T4	1022		T5	4008
invalid_exec_dis	32012878	1			T26	15888		T27	6460		T28	19506