Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.31 99.22 95.11 99.72 100.00 96.31 99.12 98.72


Total tests in report: 1031
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
70.41 70.41 92.00 92.00 67.30 67.30 83.84 83.84 33.33 33.33 81.50 81.50 93.56 93.56 41.32 41.32 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.337120951
84.89 14.48 96.70 4.70 79.27 11.97 85.44 1.60 71.43 38.10 88.25 6.75 95.46 1.90 77.70 36.38 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2028009400
90.64 5.75 98.00 1.30 84.12 4.86 96.39 10.96 90.48 19.05 91.25 3.00 95.46 0.00 78.79 1.10 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.2503263268
92.78 2.14 98.70 0.70 85.78 1.66 96.39 0.00 100.00 9.52 93.25 2.00 95.46 0.00 79.89 1.10 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1233632755
93.81 1.02 99.04 0.35 88.15 2.37 97.85 1.46 100.00 0.00 94.75 1.50 96.05 0.59 80.80 0.91 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.1044036681
94.77 0.96 99.13 0.09 89.45 1.30 98.27 0.42 100.00 0.00 95.50 0.75 96.19 0.15 84.83 4.02 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_regwen.2120034562
95.55 0.78 99.13 0.00 89.81 0.36 98.27 0.00 100.00 0.00 95.50 0.00 96.19 0.00 89.95 5.12 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2272108232
96.04 0.49 99.13 0.00 91.11 1.30 98.61 0.35 100.00 0.00 96.00 0.50 96.19 0.00 91.22 1.28 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.1921938538
96.35 0.31 99.13 0.00 91.11 0.00 98.61 0.00 100.00 0.00 96.00 0.00 96.19 0.00 93.42 2.19 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.2896846703
96.61 0.25 99.13 0.00 91.35 0.24 98.61 0.00 100.00 0.00 96.00 0.00 97.36 1.17 93.78 0.37 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.698911521
96.84 0.24 99.13 0.00 91.35 0.00 98.61 0.00 100.00 0.00 96.00 0.00 97.36 0.00 95.43 1.65 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_executable.2881891188
97.07 0.22 99.13 0.00 91.35 0.00 98.61 0.00 100.00 0.00 96.00 0.00 98.39 1.02 95.98 0.55 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.3302743595
97.24 0.17 99.13 0.00 91.47 0.12 98.61 0.00 100.00 0.00 96.50 0.50 98.98 0.59 95.98 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1788002811
97.37 0.13 99.22 0.09 91.47 0.00 99.45 0.83 100.00 0.00 96.50 0.00 98.98 0.00 95.98 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.48826429
97.47 0.10 99.22 0.00 91.47 0.00 99.45 0.00 100.00 0.00 96.50 0.00 98.98 0.00 96.71 0.73 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_executable.3645717590
97.56 0.09 99.22 0.00 91.82 0.36 99.51 0.07 100.00 0.00 96.50 0.00 98.98 0.00 96.89 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.1875330677
97.64 0.08 99.22 0.00 91.82 0.00 99.51 0.00 100.00 0.00 96.50 0.00 98.98 0.00 97.44 0.55 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1835256321
97.69 0.05 99.22 0.00 91.82 0.00 99.51 0.00 100.00 0.00 96.50 0.00 98.98 0.00 97.81 0.37 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2328015917
97.74 0.05 99.22 0.00 91.82 0.00 99.51 0.00 100.00 0.00 96.50 0.00 98.98 0.00 98.17 0.37 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1463789118
97.78 0.04 99.22 0.00 91.82 0.00 99.58 0.07 100.00 0.00 96.50 0.00 98.98 0.00 98.35 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2608769040
97.81 0.03 99.22 0.00 91.82 0.00 99.58 0.00 100.00 0.00 96.50 0.00 98.98 0.00 98.54 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.2516687557
97.83 0.03 99.22 0.00 91.82 0.00 99.58 0.00 100.00 0.00 96.50 0.00 98.98 0.00 98.72 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3742846147
97.85 0.02 99.22 0.00 91.82 0.00 99.58 0.00 100.00 0.00 96.50 0.00 99.12 0.15 98.72 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3982725571
97.87 0.02 99.22 0.00 91.82 0.00 99.72 0.14 100.00 0.00 96.50 0.00 99.12 0.00 98.72 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_bijection.1829681664

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.610265315
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3120701293
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3429450253
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3786140641
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.822888358
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2748312931
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1297196979
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.210021249
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.596126278
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2722381984
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.770542569
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.212967472
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2462304129
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.330674654
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1583683193
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3323939552
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.690995652
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3693165361
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.123009340
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.4108858981
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.733295358
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3957909019
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.4016159670
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2500787814
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.515740083
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.459561571
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.4069426529
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3510425818
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3212243467
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.4285989484
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2026571531
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3873878242
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3381383381
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1704999227
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1062478066
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3605044
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1952781086
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3340295742
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.635414736
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3213285665
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2286972112
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4237366668
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.921629946
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3614797012
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.978795248
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.593312653
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3880208342
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.429932592
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.199441215
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3823661580
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3049588838
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3377816189
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1193417767
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.949966189
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1692108872
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.4287497020
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.445656230
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.157416725
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.4239088906
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1758045136
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.937667685
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2236204937
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2241589870
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1151029850
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2752148218
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2153277505
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4005655633
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3942383770
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3458746434
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.510690511
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.4130786641
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.846241353
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2578398908
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2873613649
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.4265853934
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2703286602
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1661213618
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.653455718
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2458612137
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.4055932902
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.465310454
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2963262062
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2681501945
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2944053480
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/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.2029865892
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/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.1920240350
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.3981416200
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_smoke.1419586600
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all.1609015887
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.4109433028
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.1334071729
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.1377563586
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.1022115713
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.18712438
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.1905276736
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.2833209702
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.4283991603
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.1691170998
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.3487377091
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.2718041520
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.2876003252
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.3518346058
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.251114452
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.1842198195
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.18614040
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.3789455401
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.2228512236
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1907828694
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.3582800175
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.1761126317
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.3469985004
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.3540403151
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.3652737212
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.2353766171
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.4225934797
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.1761922380
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.566216590
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3226780935
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.2008564611
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.2932251075
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.3894154882
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.3020297794
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.248732971
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.4291558850
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all.3865048599
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2973308115
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.3771938519
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.1231261998
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.476748604
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.530617792
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.1023936477
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.2169208751
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.2603267916
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.3734274682
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.2551996597
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.576083219
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.1961363276
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.615687815
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.566699960
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3203957465
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.3986409785
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.3017557908
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.2218611495
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1427905841
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.1192438096
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.4294161244



Total test records in report: 1031
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.531121547 Oct 03 11:45:34 AM UTC 24 Oct 03 11:45:38 AM UTC 24 141834590 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.48826429 Oct 03 11:45:36 AM UTC 24 Oct 03 11:45:38 AM UTC 24 50915830 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.1875330677 Oct 03 11:45:41 AM UTC 24 Oct 03 11:45:43 AM UTC 24 74810116 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.1044036681 Oct 03 11:45:40 AM UTC 24 Oct 03 11:45:43 AM UTC 24 185179297 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.3302743595 Oct 03 11:45:39 AM UTC 24 Oct 03 11:45:44 AM UTC 24 123061429 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.2503263268 Oct 03 11:45:37 AM UTC 24 Oct 03 11:45:53 AM UTC 24 592991625 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_smoke.487135890 Oct 03 11:45:41 AM UTC 24 Oct 03 11:45:53 AM UTC 24 236319653 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_smoke.2600090004 Oct 03 11:45:31 AM UTC 24 Oct 03 11:45:53 AM UTC 24 499337462 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.2297896132 Oct 03 11:45:53 AM UTC 24 Oct 03 11:45:56 AM UTC 24 74990095 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.337120951 Oct 03 11:45:48 AM UTC 24 Oct 03 11:46:00 AM UTC 24 647336235 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.525624264 Oct 03 11:45:54 AM UTC 24 Oct 03 11:46:01 AM UTC 24 347368096 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.3119727505 Oct 03 11:45:34 AM UTC 24 Oct 03 11:46:02 AM UTC 24 324205051 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_alert_test.2346517468 Oct 03 11:46:03 AM UTC 24 Oct 03 11:46:05 AM UTC 24 21096903 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.3886787842 Oct 03 11:45:46 AM UTC 24 Oct 03 11:46:05 AM UTC 24 80751754 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access.527125251 Oct 03 11:45:46 AM UTC 24 Oct 03 11:46:07 AM UTC 24 1160444623 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.1841025722 Oct 03 11:46:02 AM UTC 24 Oct 03 11:46:09 AM UTC 24 636123297 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.4156801437 Oct 03 11:45:53 AM UTC 24 Oct 03 11:46:12 AM UTC 24 1224527244 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_bijection.4005773003 Oct 03 11:45:32 AM UTC 24 Oct 03 11:46:14 AM UTC 24 1839037510 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_smoke.2462183476 Oct 03 11:46:06 AM UTC 24 Oct 03 11:46:25 AM UTC 24 284854008 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.3386562531 Oct 03 11:46:26 AM UTC 24 Oct 03 11:46:34 AM UTC 24 55178893 ps
T107 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_bijection.2629820543 Oct 03 11:46:07 AM UTC 24 Oct 03 11:46:35 AM UTC 24 297706404 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.2039612352 Oct 03 11:45:34 AM UTC 24 Oct 03 11:46:36 AM UTC 24 547306952 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.1921938538 Oct 03 11:46:31 AM UTC 24 Oct 03 11:46:40 AM UTC 24 421089544 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.2938292628 Oct 03 11:46:42 AM UTC 24 Oct 03 11:46:44 AM UTC 24 27646911 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access.1950497450 Oct 03 11:45:32 AM UTC 24 Oct 03 11:46:45 AM UTC 24 619048926 ps
T159 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access.3889046009 Oct 03 11:46:13 AM UTC 24 Oct 03 11:46:48 AM UTC 24 5234607760 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.697647690 Oct 03 11:46:46 AM UTC 24 Oct 03 11:46:52 AM UTC 24 203228020 ps
T153 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.3930443443 Oct 03 11:45:48 AM UTC 24 Oct 03 11:46:53 AM UTC 24 527886969 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.3490402541 Oct 03 11:46:45 AM UTC 24 Oct 03 11:46:55 AM UTC 24 751710212 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_alert_test.1904725911 Oct 03 11:46:54 AM UTC 24 Oct 03 11:46:56 AM UTC 24 18373398 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.813559480 Oct 03 11:46:52 AM UTC 24 Oct 03 11:46:57 AM UTC 24 241282891 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2957171577 Oct 03 11:46:47 AM UTC 24 Oct 03 11:46:59 AM UTC 24 521990571 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access.322896884 Oct 03 11:47:02 AM UTC 24 Oct 03 11:47:11 AM UTC 24 332904699 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_smoke.2918112493 Oct 03 11:46:55 AM UTC 24 Oct 03 11:47:13 AM UTC 24 80851876 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.901793940 Oct 03 11:47:17 AM UTC 24 Oct 03 11:47:27 AM UTC 24 2026251267 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_bijection.1829681664 Oct 03 11:45:45 AM UTC 24 Oct 03 11:47:35 AM UTC 24 95161043433 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.1025599498 Oct 03 11:47:16 AM UTC 24 Oct 03 11:47:36 AM UTC 24 87230391 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.229707853 Oct 03 11:47:37 AM UTC 24 Oct 03 11:47:39 AM UTC 24 117191821 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.2981403708 Oct 03 11:46:18 AM UTC 24 Oct 03 11:47:39 AM UTC 24 484538569 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.1700720105 Oct 03 11:47:40 AM UTC 24 Oct 03 11:47:47 AM UTC 24 395550345 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.123986018 Oct 03 11:47:14 AM UTC 24 Oct 03 11:47:49 AM UTC 24 91430190 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.3700397997 Oct 03 11:47:48 AM UTC 24 Oct 03 11:47:52 AM UTC 24 230602676 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_alert_test.2169056828 Oct 03 11:47:50 AM UTC 24 Oct 03 11:47:52 AM UTC 24 50723806 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.1370809503 Oct 03 11:47:37 AM UTC 24 Oct 03 11:47:56 AM UTC 24 2353607132 ps
T158 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_bijection.2853279176 Oct 03 11:46:58 AM UTC 24 Oct 03 11:47:56 AM UTC 24 721799431 ps
T163 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_smoke.1438877451 Oct 03 11:47:53 AM UTC 24 Oct 03 11:48:03 AM UTC 24 183905488 ps
T162 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access.787421186 Oct 03 11:47:58 AM UTC 24 Oct 03 11:48:12 AM UTC 24 518499077 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.3572973397 Oct 03 11:48:07 AM UTC 24 Oct 03 11:48:21 AM UTC 24 2076288031 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2028009400 Oct 03 11:45:39 AM UTC 24 Oct 03 11:48:21 AM UTC 24 25629567843 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3742846147 Oct 03 11:45:57 AM UTC 24 Oct 03 11:48:25 AM UTC 24 3674734444 ps
T164 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.2594236019 Oct 03 11:48:25 AM UTC 24 Oct 03 11:48:27 AM UTC 24 28400557 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.2731670854 Oct 03 11:48:28 AM UTC 24 Oct 03 11:48:33 AM UTC 24 239526061 ps
T165 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_alert_test.2091887263 Oct 03 11:48:34 AM UTC 24 Oct 03 11:48:36 AM UTC 24 45605190 ps
T166 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.3536162171 Oct 03 11:48:26 AM UTC 24 Oct 03 11:48:38 AM UTC 24 279063103 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.1219853860 Oct 03 11:48:34 AM UTC 24 Oct 03 11:48:38 AM UTC 24 569840315 ps
T167 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_bijection.3870793822 Oct 03 11:47:56 AM UTC 24 Oct 03 11:48:39 AM UTC 24 4270529251 ps
T101 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.2516687557 Oct 03 11:45:32 AM UTC 24 Oct 03 11:48:42 AM UTC 24 4581505159 ps
T168 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_smoke.3434175401 Oct 03 11:48:37 AM UTC 24 Oct 03 11:48:43 AM UTC 24 181839008 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_executable.4074186151 Oct 03 11:45:48 AM UTC 24 Oct 03 11:48:47 AM UTC 24 630421487 ps
T151 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access.2561088983 Oct 03 11:48:43 AM UTC 24 Oct 03 11:48:47 AM UTC 24 57192766 ps
T160 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.956339529 Oct 03 11:48:48 AM UTC 24 Oct 03 11:48:55 AM UTC 24 683604198 ps
T169 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.1479756945 Oct 03 11:48:04 AM UTC 24 Oct 03 11:49:10 AM UTC 24 555146794 ps
T170 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.235396656 Oct 03 11:48:44 AM UTC 24 Oct 03 11:49:20 AM UTC 24 182898900 ps
T171 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.3304647811 Oct 03 11:49:21 AM UTC 24 Oct 03 11:49:23 AM UTC 24 74810532 ps
T172 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_bijection.2486585035 Oct 03 11:48:39 AM UTC 24 Oct 03 11:49:34 AM UTC 24 1102960418 ps
T161 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.1106433013 Oct 03 11:48:03 AM UTC 24 Oct 03 11:49:35 AM UTC 24 138022309 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.3937690888 Oct 03 11:49:24 AM UTC 24 Oct 03 11:49:37 AM UTC 24 925870718 ps
T85 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.1955659565 Oct 03 11:49:35 AM UTC 24 Oct 03 11:49:39 AM UTC 24 709366205 ps
T173 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_alert_test.4108045188 Oct 03 11:49:40 AM UTC 24 Oct 03 11:49:42 AM UTC 24 42224198 ps
T174 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.3088087664 Oct 03 11:48:48 AM UTC 24 Oct 03 11:49:46 AM UTC 24 433443427 ps
T175 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_smoke.1419586600 Oct 03 11:49:43 AM UTC 24 Oct 03 11:49:55 AM UTC 24 531178022 ps
T102 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.1506104354 Oct 03 11:46:14 AM UTC 24 Oct 03 11:50:02 AM UTC 24 10233744724 ps
T103 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.810007549 Oct 03 11:46:09 AM UTC 24 Oct 03 11:50:07 AM UTC 24 8366887040 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access.3282166666 Oct 03 11:49:56 AM UTC 24 Oct 03 11:50:08 AM UTC 24 81641821 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_bijection.2970040883 Oct 03 11:49:50 AM UTC 24 Oct 03 11:50:15 AM UTC 24 1061936274 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2057881823 Oct 03 11:47:40 AM UTC 24 Oct 03 11:50:18 AM UTC 24 1492125987 ps
T178 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.2588381791 Oct 03 11:50:09 AM UTC 24 Oct 03 11:50:20 AM UTC 24 2267538848 ps
T104 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.2605751634 Oct 03 11:45:32 AM UTC 24 Oct 03 11:50:20 AM UTC 24 2338950950 ps
T179 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.1377563586 Oct 03 11:50:08 AM UTC 24 Oct 03 11:50:20 AM UTC 24 149324604 ps
T180 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.3981416200 Oct 03 11:50:20 AM UTC 24 Oct 03 11:50:23 AM UTC 24 76243438 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.4098245114 Oct 03 11:50:22 AM UTC 24 Oct 03 11:50:31 AM UTC 24 849027624 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.782095234 Oct 03 11:49:36 AM UTC 24 Oct 03 11:50:32 AM UTC 24 586347341 ps
T181 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_alert_test.4243182415 Oct 03 11:50:33 AM UTC 24 Oct 03 11:50:35 AM UTC 24 17831061 ps
T182 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.640771448 Oct 03 11:50:22 AM UTC 24 Oct 03 11:50:38 AM UTC 24 1701757981 ps
T183 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.1875887352 Oct 03 11:47:00 AM UTC 24 Oct 03 11:50:41 AM UTC 24 3953223385 ps
T184 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.3789455401 Oct 03 11:50:36 AM UTC 24 Oct 03 11:50:44 AM UTC 24 305163013 ps
T148 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.1531622283 Oct 03 11:45:46 AM UTC 24 Oct 03 11:50:47 AM UTC 24 10645722590 ps
T185 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.2029865892 Oct 03 11:50:03 AM UTC 24 Oct 03 11:50:56 AM UTC 24 111406598 ps
T186 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.3518346058 Oct 03 11:50:48 AM UTC 24 Oct 03 11:50:56 AM UTC 24 280176778 ps
T152 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.455133541 Oct 03 11:45:45 AM UTC 24 Oct 03 11:51:01 AM UTC 24 6292556438 ps
T187 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.1761126317 Oct 03 11:51:02 AM UTC 24 Oct 03 11:51:06 AM UTC 24 84137730 ps
T188 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.4283991603 Oct 03 11:51:02 AM UTC 24 Oct 03 11:51:07 AM UTC 24 143337378 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_executable.1228540211 Oct 03 11:48:21 AM UTC 24 Oct 03 11:51:14 AM UTC 24 688862859 ps
T189 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.1842198195 Oct 03 11:51:15 AM UTC 24 Oct 03 11:51:17 AM UTC 24 126587445 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_executable.3427708088 Oct 03 11:46:35 AM UTC 24 Oct 03 11:51:20 AM UTC 24 14195524297 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.3487377091 Oct 03 11:51:21 AM UTC 24 Oct 03 11:51:26 AM UTC 24 62228857 ps
T190 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.2718041520 Oct 03 11:51:18 AM UTC 24 Oct 03 11:51:26 AM UTC 24 280977253 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.1962891339 Oct 03 11:45:34 AM UTC 24 Oct 03 11:51:27 AM UTC 24 1213338579 ps
T141 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_executable.1259773360 Oct 03 11:47:26 AM UTC 24 Oct 03 11:51:28 AM UTC 24 4153319539 ps
T191 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.1905276736 Oct 03 11:50:41 AM UTC 24 Oct 03 11:51:29 AM UTC 24 733651445 ps
T192 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.18712438 Oct 03 11:51:28 AM UTC 24 Oct 03 11:51:30 AM UTC 24 17034666 ps
T193 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.4291558850 Oct 03 11:51:29 AM UTC 24 Oct 03 11:51:46 AM UTC 24 994396714 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_regwen.244966595 Oct 03 11:45:50 AM UTC 24 Oct 03 11:51:50 AM UTC 24 31622535675 ps
T194 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.2646488998 Oct 03 11:47:58 AM UTC 24 Oct 03 11:51:53 AM UTC 24 6024583710 ps
T195 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.2365236749 Oct 03 11:45:45 AM UTC 24 Oct 03 11:52:01 AM UTC 24 3644223314 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.4109433028 Oct 03 11:50:24 AM UTC 24 Oct 03 11:52:01 AM UTC 24 727963558 ps
T120 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.4225934797 Oct 03 11:52:01 AM UTC 24 Oct 03 11:52:06 AM UTC 24 156206084 ps
T196 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.2932251075 Oct 03 11:51:44 AM UTC 24 Oct 03 11:52:13 AM UTC 24 4157855790 ps
T197 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.1691170998 Oct 03 11:50:58 AM UTC 24 Oct 03 11:52:17 AM UTC 24 119744106 ps
T198 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.3020297794 Oct 03 11:52:15 AM UTC 24 Oct 03 11:52:17 AM UTC 24 27047858 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.566216590 Oct 03 11:52:18 AM UTC 24 Oct 03 11:52:24 AM UTC 24 118780282 ps
T199 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.3652737212 Oct 03 11:51:31 AM UTC 24 Oct 03 11:52:26 AM UTC 24 3167301048 ps
T200 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.1761922380 Oct 03 11:51:51 AM UTC 24 Oct 03 11:52:28 AM UTC 24 132921659 ps
T201 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.3540403151 Oct 03 11:52:28 AM UTC 24 Oct 03 11:52:31 AM UTC 24 25510497 ps
T202 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3226780935 Oct 03 11:52:18 AM UTC 24 Oct 03 11:52:32 AM UTC 24 1901092004 ps
T203 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.3017557908 Oct 03 11:52:31 AM UTC 24 Oct 03 11:52:39 AM UTC 24 55613090 ps
T204 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.1231261998 Oct 03 11:51:54 AM UTC 24 Oct 03 11:52:50 AM UTC 24 118520599 ps
T205 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.615687815 Oct 03 11:52:50 AM UTC 24 Oct 03 11:52:54 AM UTC 24 530337078 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.1969338952 Oct 03 11:48:13 AM UTC 24 Oct 03 11:53:00 AM UTC 24 1082477863 ps
T149 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.1625566595 Oct 03 11:47:12 AM UTC 24 Oct 03 11:53:07 AM UTC 24 149560230203 ps
T206 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.318886737 Oct 03 11:47:59 AM UTC 24 Oct 03 11:53:10 AM UTC 24 3973518029 ps
T207 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.2603267916 Oct 03 11:53:11 AM UTC 24 Oct 03 11:53:19 AM UTC 24 1791842042 ps
T208 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.4076499589 Oct 03 11:48:40 AM UTC 24 Oct 03 11:53:22 AM UTC 24 2765900228 ps
T209 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.1023936477 Oct 03 11:52:35 AM UTC 24 Oct 03 11:53:32 AM UTC 24 3272994645 ps
T210 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.4294161244 Oct 03 11:53:09 AM UTC 24 Oct 03 11:53:37 AM UTC 24 111095576 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.2496493902 Oct 03 11:48:39 AM UTC 24 Oct 03 11:53:38 AM UTC 24 2486259147 ps
T212 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3203957465 Oct 03 11:53:38 AM UTC 24 Oct 03 11:53:40 AM UTC 24 29328064 ps
T213 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.3734274682 Oct 03 11:53:00 AM UTC 24 Oct 03 11:53:47 AM UTC 24 109349636 ps
T214 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.2551996597 Oct 03 11:53:41 AM UTC 24 Oct 03 11:53:47 AM UTC 24 204330990 ps
T215 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.576083219 Oct 03 11:53:39 AM UTC 24 Oct 03 11:53:48 AM UTC 24 891972824 ps
T216 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.530617792 Oct 03 11:53:48 AM UTC 24 Oct 03 11:53:50 AM UTC 24 67915643 ps
T217 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.2766866683 Oct 03 11:46:58 AM UTC 24 Oct 03 11:53:53 AM UTC 24 1940405912 ps
T218 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_smoke.3225834475 Oct 03 11:53:51 AM UTC 24 Oct 03 11:54:00 AM UTC 24 189893241 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_regwen.2120034562 Oct 03 11:50:18 AM UTC 24 Oct 03 11:54:02 AM UTC 24 5311154428 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1907828694 Oct 03 11:51:27 AM UTC 24 Oct 03 11:54:49 AM UTC 24 12612415983 ps
T219 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access.3974636755 Oct 03 11:54:49 AM UTC 24 Oct 03 11:55:07 AM UTC 24 322510896 ps
T220 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.1920240350 Oct 03 11:49:57 AM UTC 24 Oct 03 11:55:12 AM UTC 24 20832062101 ps
T221 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_bijection.3561524064 Oct 03 11:54:01 AM UTC 24 Oct 03 11:55:14 AM UTC 24 9883901405 ps
T222 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.3771938519 Oct 03 11:51:44 AM UTC 24 Oct 03 11:55:20 AM UTC 24 1999430127 ps
T223 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.2077172098 Oct 03 11:55:20 AM UTC 24 Oct 03 11:55:28 AM UTC 24 560107228 ps
T150 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.2896846703 Oct 03 11:48:43 AM UTC 24 Oct 03 11:55:40 AM UTC 24 176509715416 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.1022115713 Oct 03 11:51:06 AM UTC 24 Oct 03 11:55:46 AM UTC 24 976800908 ps
T224 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.3582800175 Oct 03 11:50:45 AM UTC 24 Oct 03 11:55:51 AM UTC 24 11137818629 ps
T225 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.3091494650 Oct 03 11:55:52 AM UTC 24 Oct 03 11:55:54 AM UTC 24 30041406 ps
T226 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.1334071729 Oct 03 11:49:53 AM UTC 24 Oct 03 11:56:04 AM UTC 24 12633130325 ps
T227 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.817472333 Oct 03 11:55:55 AM UTC 24 Oct 03 11:56:05 AM UTC 24 591488680 ps
T228 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.3874404036 Oct 03 11:55:14 AM UTC 24 Oct 03 11:56:07 AM UTC 24 433770763 ps
T229 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.1094075236 Oct 03 11:55:13 AM UTC 24 Oct 03 11:56:07 AM UTC 24 490304029 ps
T230 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_alert_test.992503882 Oct 03 11:56:08 AM UTC 24 Oct 03 11:56:10 AM UTC 24 44605912 ps
T231 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.2740691661 Oct 03 11:56:04 AM UTC 24 Oct 03 11:56:14 AM UTC 24 193906626 ps
T232 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.589259469 Oct 03 11:53:54 AM UTC 24 Oct 03 11:56:27 AM UTC 24 3421486064 ps
T134 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_regwen.1434817778 Oct 03 11:48:22 AM UTC 24 Oct 03 11:56:40 AM UTC 24 39642889555 ps
T233 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_bijection.340749514 Oct 03 11:56:15 AM UTC 24 Oct 03 11:57:01 AM UTC 24 2354346720 ps
T234 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.2662441467 Oct 03 11:46:35 AM UTC 24 Oct 03 11:57:06 AM UTC 24 12986397416 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.217920838 Oct 03 11:57:09 AM UTC 24 Oct 03 11:57:25 AM UTC 24 2354946119 ps
T235 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.3353286180 Oct 03 11:45:48 AM UTC 24 Oct 03 11:57:06 AM UTC 24 2492826171 ps
T236 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access.3908199363 Oct 03 11:56:40 AM UTC 24 Oct 03 11:57:08 AM UTC 24 249562535 ps
T154 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_smoke.912394452 Oct 03 11:56:09 AM UTC 24 Oct 03 11:57:36 AM UTC 24 659797719 ps
T135 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_regwen.1184873311 Oct 03 11:47:27 AM UTC 24 Oct 03 11:57:58 AM UTC 24 7676011993 ps
T237 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.1044015632 Oct 03 11:57:59 AM UTC 24 Oct 03 11:58:01 AM UTC 24 47883329 ps
T238 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.734975864 Oct 03 11:54:03 AM UTC 24 Oct 03 11:58:04 AM UTC 24 2474617217 ps
T239 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.1915063801 Oct 03 11:57:06 AM UTC 24 Oct 03 11:58:08 AM UTC 24 306529700 ps
T240 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.1219024410 Oct 03 11:58:05 AM UTC 24 Oct 03 11:58:11 AM UTC 24 61612356 ps
T241 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.1125920685 Oct 03 11:58:02 AM UTC 24 Oct 03 11:58:11 AM UTC 24 238959353 ps
T242 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_alert_test.3203442542 Oct 03 11:58:11 AM UTC 24 Oct 03 11:58:13 AM UTC 24 35923803 ps
T243 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_smoke.4283273589 Oct 03 11:58:14 AM UTC 24 Oct 03 11:58:18 AM UTC 24 274398087 ps
T244 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.251114452 Oct 03 11:50:56 AM UTC 24 Oct 03 11:58:20 AM UTC 24 6010760137 ps
T139 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_regwen.1761287368 Oct 03 11:46:36 AM UTC 24 Oct 03 11:58:24 AM UTC 24 25948738979 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1427905841 Oct 03 11:53:47 AM UTC 24 Oct 03 11:58:24 AM UTC 24 6798277622 ps
T245 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.566699960 Oct 03 11:52:55 AM UTC 24 Oct 03 11:58:26 AM UTC 24 51722438339 ps
T246 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.1961363276 Oct 03 11:52:33 AM UTC 24 Oct 03 11:58:28 AM UTC 24 11271064558 ps
T247 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.4173169413 Oct 03 11:55:08 AM UTC 24 Oct 03 11:58:31 AM UTC 24 16007842607 ps
T248 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.2883242526 Oct 03 11:57:07 AM UTC 24 Oct 03 11:58:31 AM UTC 24 863621770 ps
T249 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.1192438096 Oct 03 11:52:39 AM UTC 24 Oct 03 11:58:38 AM UTC 24 7284791816 ps
T250 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.3894154882 Oct 03 11:51:47 AM UTC 24 Oct 03 11:58:42 AM UTC 24 4629406695 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2973308115 Oct 03 11:52:25 AM UTC 24 Oct 03 11:58:44 AM UTC 24 8867921507 ps
T251 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.3041664504 Oct 03 11:58:32 AM UTC 24 Oct 03 11:58:48 AM UTC 24 4352942499 ps
T252 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.2347880151 Oct 03 11:58:49 AM UTC 24 Oct 03 11:58:51 AM UTC 24 57372964 ps
T253 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.2238204911 Oct 03 11:58:29 AM UTC 24 Oct 03 11:58:51 AM UTC 24 83897985 ps
T254 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.1148986578 Oct 03 11:58:32 AM UTC 24 Oct 03 11:58:52 AM UTC 24 88124420 ps
T255 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access.3661199781 Oct 03 11:58:25 AM UTC 24 Oct 03 11:58:57 AM UTC 24 241204308 ps
T256 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.2864441994 Oct 03 11:58:53 AM UTC 24 Oct 03 11:59:00 AM UTC 24 177728212 ps
T257 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.793692881 Oct 03 11:58:52 AM UTC 24 Oct 03 11:59:02 AM UTC 24 908479217 ps
T258 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_bijection.397658698 Oct 03 11:58:21 AM UTC 24 Oct 03 11:59:02 AM UTC 24 2680990764 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_alert_test.3198755602 Oct 03 11:59:00 AM UTC 24 Oct 03 11:59:02 AM UTC 24 40527272 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1463789118 Oct 03 11:58:54 AM UTC 24 Oct 03 11:59:16 AM UTC 24 202195416 ps
T142 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_executable.658861467 Oct 03 11:49:07 AM UTC 24 Oct 03 11:59:21 AM UTC 24 8805323674 ps
T260 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access.1918695367 Oct 03 11:59:22 AM UTC 24 Oct 03 11:59:42 AM UTC 24 892360982 ps
T261 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.2618399669 Oct 03 11:47:53 AM UTC 24 Oct 03 11:59:47 AM UTC 24 10168388145 ps
T262 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.1989191165 Oct 03 11:56:28 AM UTC 24 Oct 03 11:59:47 AM UTC 24 1725367901 ps
T263 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.1925762762 Oct 03 11:59:48 AM UTC 24 Oct 03 12:00:10 PM UTC 24 448630186 ps
T264 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.3112346260 Oct 03 11:59:48 AM UTC 24 Oct 03 12:00:15 PM UTC 24 249156195 ps
T265 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.3947591048 Oct 03 12:00:11 PM UTC 24 Oct 03 12:00:22 PM UTC 24 1950627664 ps
T266 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_bijection.685367792 Oct 03 11:59:03 AM UTC 24 Oct 03 12:00:24 PM UTC 24 4761241168 ps
T267 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_executable.2486357538 Oct 03 11:57:37 AM UTC 24 Oct 03 12:00:27 PM UTC 24 9869373241 ps
T268 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.712563248 Oct 03 12:00:28 PM UTC 24 Oct 03 12:00:30 PM UTC 24 85811966 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1788002811 Oct 03 11:58:09 AM UTC 24 Oct 03 12:00:32 PM UTC 24 3848927234 ps
T155 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_smoke.3472335158 Oct 03 11:59:02 AM UTC 24 Oct 03 12:00:33 PM UTC 24 1537442470 ps
T269 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.1647993956 Oct 03 12:00:34 PM UTC 24 Oct 03 12:00:38 PM UTC 24 164775894 ps
T270 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.4103105651 Oct 03 11:59:03 AM UTC 24 Oct 03 12:00:41 PM UTC 24 534241250 ps
T271 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_alert_test.2633891217 Oct 03 12:00:42 PM UTC 24 Oct 03 12:00:44 PM UTC 24 24915045 ps
T272 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.3157223268 Oct 03 12:00:31 PM UTC 24 Oct 03 12:00:45 PM UTC 24 548336640 ps
T273 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.3469985004 Oct 03 11:52:02 AM UTC 24 Oct 03 12:00:51 PM UTC 24 2657722285 ps
T274 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_smoke.4127088886 Oct 03 12:00:45 PM UTC 24 Oct 03 12:00:52 PM UTC 24 188296210 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_bijection.34048652 Oct 03 12:00:52 PM UTC 24 Oct 03 12:01:13 PM UTC 24 960584013 ps
T143 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_regwen.1301021932 Oct 03 11:58:45 AM UTC 24 Oct 03 12:01:14 PM UTC 24 16081684173 ps
T276 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.2569357947 Oct 03 11:49:47 AM UTC 24 Oct 03 12:01:20 PM UTC 24 2771336138 ps
T277 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.4034694836 Oct 03 12:01:21 PM UTC 24 Oct 03 12:01:25 PM UTC 24 46371885 ps
T278 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.2553184420 Oct 03 12:01:26 PM UTC 24 Oct 03 12:01:29 PM UTC 24 68733670 ps
T279 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.1999525873 Oct 03 12:01:30 PM UTC 24 Oct 03 12:01:33 PM UTC 24 92093025 ps
T140 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.2833209702 Oct 03 11:51:06 AM UTC 24 Oct 03 12:01:43 PM UTC 24 6323052548 ps
T280 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.1150972562 Oct 03 11:56:11 AM UTC 24 Oct 03 12:01:49 PM UTC 24 6384420279 ps
T156 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1233632755 Oct 03 12:00:35 PM UTC 24 Oct 03 12:01:53 PM UTC 24 1354757089 ps
T281 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.1508710985 Oct 03 12:01:54 PM UTC 24 Oct 03 12:01:56 PM UTC 24 42369177 ps
T282 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access.1192498956 Oct 03 12:01:14 PM UTC 24 Oct 03 12:01:58 PM UTC 24 405992037 ps
T283 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.2533074962 Oct 03 12:01:59 PM UTC 24 Oct 03 12:02:04 PM UTC 24 158233441 ps
T284 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.2068463716 Oct 03 11:46:06 AM UTC 24 Oct 03 12:02:05 PM UTC 24 43759212622 ps
T136 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.3986409785 Oct 03 11:53:33 AM UTC 24 Oct 03 12:02:10 PM UTC 24 1346600970 ps
T285 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_alert_test.3971209105 Oct 03 12:02:11 PM UTC 24 Oct 03 12:02:12 PM UTC 24 18965167 ps
T157 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.248732971 Oct 03 11:52:10 AM UTC 24 Oct 03 12:02:14 PM UTC 24 1163999478 ps
T286 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.4227898166 Oct 03 12:01:57 PM UTC 24 Oct 03 12:02:15 PM UTC 24 1308783942 ps
T287 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.2677374610 Oct 03 11:58:25 AM UTC 24 Oct 03 12:02:19 PM UTC 24 9563563921 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_smoke.4080942571 Oct 03 12:02:14 PM UTC 24 Oct 03 12:02:22 PM UTC 24 129392051 ps
T289 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.2876003252 Oct 03 11:50:38 AM UTC 24 Oct 03 12:02:23 PM UTC 24 3617164667 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access.1213494998 Oct 03 12:02:20 PM UTC 24 Oct 03 12:02:28 PM UTC 24 229137292 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all.1515069532 Oct 03 12:00:39 PM UTC 24 Oct 03 12:02:34 PM UTC 24 6435009471 ps
T292 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.2657434041 Oct 03 12:02:35 PM UTC 24 Oct 03 12:02:45 PM UTC 24 426118402 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.1633776776 Oct 03 12:02:23 PM UTC 24 Oct 03 12:02:47 PM UTC 24 352619639 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.1709834557 Oct 03 12:00:53 PM UTC 24 Oct 03 12:02:51 PM UTC 24 1223679283 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.1153274612 Oct 03 11:48:56 AM UTC 24 Oct 03 12:03:02 PM UTC 24 5785640754 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.2008564611 Oct 03 11:51:30 AM UTC 24 Oct 03 12:03:02 PM UTC 24 11403712654 ps
T297 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.3661732227 Oct 03 12:03:03 PM UTC 24 Oct 03 12:03:05 PM UTC 24 28913080 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.2300854986 Oct 03 12:03:06 PM UTC 24 Oct 03 12:03:11 PM UTC 24 395197671 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.1483501185 Oct 03 12:03:03 PM UTC 24 Oct 03 12:03:17 PM UTC 24 1197199222 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.3304123052 Oct 03 11:59:17 AM UTC 24 Oct 03 12:03:25 PM UTC 24 2395562421 ps
T301 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_bijection.667914698 Oct 03 12:02:16 PM UTC 24 Oct 03 12:03:28 PM UTC 24 3614284005 ps
T302 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_alert_test.235466166 Oct 03 12:03:26 PM UTC 24 Oct 03 12:03:28 PM UTC 24 23737864 ps
T303 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_smoke.808099522 Oct 03 12:03:29 PM UTC 24 Oct 03 12:03:44 PM UTC 24 231162525 ps
T304 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.1008613413 Oct 03 12:03:11 PM UTC 24 Oct 03 12:03:54 PM UTC 24 239378884 ps
T305 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.2367101278 Oct 03 11:55:28 AM UTC 24 Oct 03 12:03:56 PM UTC 24 6605003118 ps
T306 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.4024608362 Oct 03 12:02:29 PM UTC 24 Oct 03 12:03:57 PM UTC 24 662446227 ps
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T311 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.2392767415 Oct 03 12:04:23 PM UTC 24 Oct 03 12:04:36 PM UTC 24 898941617 ps
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