Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

---

Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	149470683	1			T2	13834		T4	26		T5	1866
instr_valid_dis	113959674	1			T2	13834		T4	26		T5	1866
instr_en	23862598	1			T25	164		T103	94674		T100	20054

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	12305353	1			T103	117988		T100	26856		T101	35250
sram_ifetch_valid_disable	114228014	1			T2	13834		T4	26		T5	1866
sram_ifetch_enable	22937316	1			T24	28320		T25	164		T103	13662

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	149470683	1			T2	13834		T4	26		T5	1866
hw_debug_en_valid_off	113587364	1			T2	13834		T4	26		T5	1866
hw_debug_en_on	24055451	1			T24	16966		T103	77696		T100	168714

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	114228014	1			T2	13834		T4	26		T5	1866
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	100305340	1			T2	13834		T4	26		T5	1866
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9591231	1			T103	35562		T100	20054		T133	20000
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4797453	1			T103	75186		T100	21874		T101	35250
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1985965	1			T103	19466		T100	21874		T101	35250
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1931054	1			T103	55720		T130	55074		T20	57974
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4931894	1			T103	39410		T100	4982		T133	41058
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1594790	1			T103	39410		T100	4982		T135	47220
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2403622	1			T133	41058		T130	17256		T132	27990
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9451210	1			T103	38286		T100	58660		T101	64518
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4212390	1			T103	20000		T100	58660		T101	64518
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3860274	1			T103	18286		T134	5072		T20	46220

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9169225	1			T25	164		T134	58506		T19	20000
lc_exec_en	9672347	1			T24	16966		T100	105072		T101	73892
valid_exec_dis	108585309	1			T2	13834		T4	26		T5	1866
invalid_exec_dis	35242669	1			T24	28320		T25	164		T103	131650