Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.63 99.48 96.05 99.72 100.00 97.29 99.12 98.72


Total tests in report: 1075
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
82.95 82.95 94.70 94.70 81.59 81.59 94.17 94.17 57.14 57.14 86.50 86.50 94.88 94.88 71.66 71.66 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1867469380
89.66 6.71 97.04 2.35 83.97 2.38 94.94 0.76 90.48 33.33 90.50 4.00 95.02 0.15 75.69 4.02 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.692194487
92.87 3.21 98.26 1.22 86.34 2.38 97.09 2.15 100.00 9.52 93.25 2.75 96.19 1.17 78.98 3.29 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.3458200118
94.27 1.39 98.52 0.26 88.84 2.49 97.30 0.21 100.00 0.00 94.75 1.50 96.19 0.00 84.28 5.30 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_regwen.715622790
95.22 0.96 98.87 0.35 91.09 2.26 98.20 0.90 100.00 0.00 96.25 1.50 96.78 0.59 85.37 1.10 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.560671007
95.95 0.73 98.87 0.00 91.45 0.36 98.20 0.00 100.00 0.00 96.25 0.00 96.78 0.00 90.13 4.75 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2482128323
96.37 0.42 98.87 0.00 91.45 0.00 98.23 0.03 100.00 0.00 96.25 0.00 96.93 0.15 92.87 2.74 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.1091018111
96.70 0.33 99.13 0.26 92.28 0.83 98.23 0.00 100.00 0.00 97.25 1.00 96.93 0.00 93.05 0.18 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_readback_err.471986454
96.98 0.28 99.13 0.00 92.52 0.24 98.30 0.07 100.00 0.00 97.25 0.00 98.24 1.32 93.42 0.37 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.950510568
97.23 0.25 99.39 0.26 92.52 0.00 98.30 0.00 100.00 0.00 97.50 0.25 99.12 0.88 93.78 0.37 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.2839901996
97.44 0.21 99.39 0.00 92.52 0.00 98.30 0.00 100.00 0.00 97.50 0.00 99.12 0.00 95.25 1.46 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_regwen.1344511603
97.57 0.13 99.48 0.09 92.52 0.00 99.13 0.83 100.00 0.00 97.50 0.00 99.12 0.00 95.25 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.4005205333
97.69 0.12 99.48 0.00 92.64 0.12 99.65 0.52 100.00 0.00 97.50 0.00 99.12 0.00 95.43 0.18 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2636185169
97.79 0.10 99.48 0.00 92.64 0.00 99.65 0.00 100.00 0.00 97.50 0.00 99.12 0.00 96.16 0.73 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1474239918
97.90 0.10 99.48 0.00 92.64 0.00 99.65 0.00 100.00 0.00 97.50 0.00 99.12 0.00 96.89 0.73 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2220186186
97.98 0.08 99.48 0.00 92.64 0.00 99.65 0.00 100.00 0.00 97.50 0.00 99.12 0.00 97.44 0.55 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.1976066019
98.04 0.06 99.48 0.00 92.99 0.36 99.72 0.07 100.00 0.00 97.50 0.00 99.12 0.00 97.44 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.1001987648
98.09 0.05 99.48 0.00 92.99 0.00 99.72 0.00 100.00 0.00 97.50 0.00 99.12 0.00 97.81 0.37 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3445105138
98.14 0.05 99.48 0.00 92.99 0.00 99.72 0.00 100.00 0.00 97.50 0.00 99.12 0.00 98.17 0.37 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.874711855
98.17 0.03 99.48 0.00 92.99 0.00 99.72 0.00 100.00 0.00 97.50 0.00 99.12 0.00 98.35 0.18 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.4020193820
98.19 0.03 99.48 0.00 92.99 0.00 99.72 0.00 100.00 0.00 97.50 0.00 99.12 0.00 98.54 0.18 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.2344947325
98.22 0.03 99.48 0.00 92.99 0.00 99.72 0.00 100.00 0.00 97.50 0.00 99.12 0.00 98.72 0.18 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all.1714920693

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1939170632
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.195996836
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3108216818
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.96899992
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2922901823
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3812903925
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1096348038
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1629534077
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3132494921
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.715918399
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.393970708
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1838406076
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1344829726
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1849754605
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2313004315
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1356455355
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.4207395235
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3169597383
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2844233109
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1619213585
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2979816837
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2882855980
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.899897518
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2513092557
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1860425736
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3146535365
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.4166468318
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1011855424
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2572465263
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3011743904
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3531150138
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2883673169
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1943800288
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2944545956
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1416279409
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1356721754
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1439300645
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2132839680
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1952976628
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2447440868
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3526589100
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.189716602
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3108259479
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1114899077
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.249248726
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2058264933
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1019198960
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.376629611
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2439233452
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.35605519
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.143118171
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2888834899
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3345406147
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1704322004
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3017595652
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.401782892
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3630975198
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.657452291
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3929060035
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3227799461
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4114318858
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.4103738831
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2171148523
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1592328343
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2347808683
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3187124066
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.776951989
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1884937141
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.196656149
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1751355562
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.384260280
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3536188705
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3484141471
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2258063268
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1217318119
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.4278183688
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2060084308
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.763174854
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.101503659
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.4201398332
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.550301026
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2807541101
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2112069199
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3288727201
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3905019272
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2698213332
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.4023047691
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2741024508
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3101740761
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1072363266
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2268629614
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1329885459
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.293860826
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.4246721731
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1931739886
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2902694878
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.4216351449
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.925230834
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3401790416
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3461747974
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.488981571
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1156870175
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.51859761
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3763310842
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2264263536
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1455974462
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2753726162
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1065592493
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3528765459
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.80495773
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2586299687
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2431723707
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3470276286
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1301066301
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3224393114
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.150229233
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2186408393
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3505954476
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3145133267
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1537635487
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1539318587
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2679807247
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.842040611
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.4116020240
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.4246585402
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2054520055
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.758702918
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.3498642437
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_bijection.479458874
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_executable.2314024083
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.2772309959
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.3195824413
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.3166053246
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access.2226555042
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_readback_err.2263485710
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_regwen.3695752139
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.544014536
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_smoke.4068182845
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.2912633314
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.2220767628
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.1461779571
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_alert_test.739005842
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_bijection.338723861
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_executable.2402257933
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.1345177711
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.3758713741
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.4167033068
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.1317031934
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access.3787747513
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.1176650529
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.4275257224
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.1302539117
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_smoke.681943585
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all.2510534855
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.2239552264
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.4178410685
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.519966988
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_alert_test.1983711007
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_bijection.243260019
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_executable.4017891162
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.180158246
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.3866816591
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.234191611
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.2667872049
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.2307556932
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access.2239235865
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.3216824505
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.3926393620
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_readback_err.2188572485
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_regwen.882633667
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_smoke.4289633849
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all.2650985909
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.781458157
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.85225778
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.3290291698
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.3789607531
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_alert_test.3868911106
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_bijection.2235818963
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_executable.13948966
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.4017493840
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.1071597411
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.3670593924
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.2787641697
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.3415515638
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access.890803073
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.4001712528
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.1389189725
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_readback_err.4148923456
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_regwen.491995936
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_smoke.2659948192
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all.1219130842
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.3014772089
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.1370034540
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.3064477967
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_alert_test.3325772363
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_bijection.2663835791
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_executable.420416680
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.898918973
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.3313613562
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.3175681103
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.237654365
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.2642101043
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access.4262161840
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.73933840
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.2093417482
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_readback_err.2292541532
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_regwen.363418800
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_smoke.3306672495
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all.105750790
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2215531823
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.2876354121
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.2561964725
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.26632733
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_alert_test.1636036326
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_bijection.4100449135
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_executable.2587876474
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.2981674684
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.2624464345
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.1032796144
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.1708851860
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.3605401728
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access.423440959
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.436544054
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.157850880
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_readback_err.2953706890
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_regwen.1840678601
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_smoke.2439842169
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all.3965902177
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.2775228154
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.2939676602
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.2583463775
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_alert_test.2882450624
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_bijection.2875753931
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_executable.2200881283
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.1799437164
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.3380420292
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.2486168895
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.4160389534
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.3382585670
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access.4117128851
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.178110635
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.2608704881
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_readback_err.4213836320
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_regwen.3318117925
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_smoke.1159863495
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all.3202707676
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3697998953
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.2403105963
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.1222002769
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.3878352115
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_alert_test.1545028208
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_bijection.3311791748
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_executable.950079579
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.2759602515
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.2286634391
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.1928964030
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.3546112829
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.779664855
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access.842160469
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.1565228721
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.4110472008
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_readback_err.965022959
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_regwen.3108238201
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_smoke.2225528867
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all.4245123314
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.763595942
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.888028736
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.4137576708
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.74694538
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_alert_test.172071838
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_bijection.3120011006
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_executable.2870258808
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.1790457138
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.376764308
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.2165323669
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.1255967404
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.2600242900
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access.3296937217
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.3269834487
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.4123920055
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_readback_err.1987422302
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_regwen.528583800
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_smoke.3177399972
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all.2182810042
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3539810114
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.683412810
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.2275044305
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.2334911724
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_alert_test.2833743090
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_bijection.1794709960
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_executable.613700332
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.2839785944
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.3156500872
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.2163417311
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.1122743157
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.3144820091
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access.2987001729
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.323754055
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.2084336851
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_readback_err.429763863
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_regwen.901925931
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_smoke.628672836
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all.553804054
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.4001679644
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.928563587
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.642569315
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.1362648654
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_alert_test.2782409158
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_bijection.2207238938
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_executable.854245781
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.285419101
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.1946987331
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.2937378851
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.3054539346
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.73002916
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access.3793754161
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.2136231121
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.963358950
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_readback_err.2948636739
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_regwen.3221354395
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_smoke.1125794896
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all.3151845512
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.4175991936
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.2899070897
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.1655988113
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.1423035360
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_alert_test.679668066
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_bijection.2995319602
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_executable.3657361573
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.3952806476
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.3129407825
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.3530897482
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.659545357
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access.1268511511
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.3528332325
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.1148089080
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_readback_err.845502099
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_regwen.3035953050
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_smoke.268588509
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all.402236388
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.2898758009
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.563377028
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.346991248
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.4257775205
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_alert_test.4089269700
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_bijection.2088726082
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_executable.1547928543
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.4030951623
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.4149719974
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.107940061
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.3297009471
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.3396499361
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access.1322462084
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.1170994700
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_readback_err.2638365370
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_regwen.3296713811
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.3076953609
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_smoke.3998922530
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all.3395346549
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2747114521
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.1901289736
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.4206919581
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.2976284648
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_alert_test.86417321
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_bijection.3347738809
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_executable.4045288151
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.74139984
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.1981104413
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.3484258001
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.727073128
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.211043656
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access.3175809474
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.2436638802
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.125668827
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_readback_err.1383143360
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_regwen.410310037
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_smoke.2646378763
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all.3709568472
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.4049441558
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.101426426
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.2987075401
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.4134238187
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_alert_test.2717997679
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_bijection.2117091092
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_executable.1773349025
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.3085414729
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.3472452882
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.407601813
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.630551901
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.1155813326
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access.2325292991
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.1414773699
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.418725205
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_readback_err.2587586028
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_regwen.1979504386
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_smoke.58306364
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all.671788527
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.37847493
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.2671157346
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.1056526720
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_alert_test.4040446595
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_bijection.3387532579
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_executable.2819240650
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.4177242258
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.1000263304
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.1865579903
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.475743085
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.555188831
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access.4013892293
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.1534523682
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.3921730012
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_readback_err.2928001539
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_regwen.2355738799
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_smoke.2341137520
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all.1133722604
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.4181334842
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.821866482
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.2088967610
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.2672197940
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_alert_test.4287339121
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_bijection.2336486646
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_executable.1015263425
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.1535148010
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.2379628520
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.1979557157
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.2904666026
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.3355829415
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access.3059226189
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.3162197377
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.4147168290
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_readback_err.767133333
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_regwen.4030688623
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_smoke.47130437
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all.3583975397
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.45026245
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.1951502359
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.1762206453
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.4204704684
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_alert_test.3521210016
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_bijection.1764034076
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_executable.326022000
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.2983218468
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.544905426
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.1855575344
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.1372970216
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.3426234197
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access.4007909257
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.1378346301
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.1824110943
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_readback_err.3158202568
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_regwen.350430610
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_smoke.3401981713
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all.434064425
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.2930445698
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.1996003818
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.722147954
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_alert_test.1797509091
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_bijection.1281904747
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_executable.1226047644
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.3140241811
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.1087592613
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.49659654
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.4054964759
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.3690186910
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access.2767083406
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.3146451659
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.3234340652
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_readback_err.2921336478
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_regwen.725780307
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_smoke.1187417820
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all.265355924
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3474389689
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.2061424290
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.2198668936
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.299166077
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_alert_test.2505765458
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_bijection.4126424281
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_executable.3909492194
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.3968116235
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.123899643
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.3213877
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.1381306505
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.2537157106
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access.2511877462
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.358235900
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.1197526685
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_readback_err.1721215955
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_regwen.3875801334
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_smoke.3792983790
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all.2953829353
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.2428114567
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.3579504432
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.231948658
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.2017145898
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_alert_test.1712157014
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_bijection.1191826373
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_executable.772613931
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.2623953447
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.996003482
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.2364388652
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.3434545870
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.2242491854
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access.2994940485
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.688540328
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.3220445332
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_readback_err.681999691
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_regwen.3055675101
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_smoke.262315080
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all.1541329722
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3584612416
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.2842513802
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.1648573589
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.3832576760
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_alert_test.4244537985
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_bijection.2753822789
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_executable.180083483
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.3051706368
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.3959384418
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.4129796500
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.4063379032
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.3730523007
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access.2249827162
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.1103361855
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.211011033
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_readback_err.1103407066
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_regwen.41537313
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_smoke.2985878915
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all.1123371159
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.926041343
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.3704273540
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.1755917758
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.3229660588
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_alert_test.2695751712
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_bijection.3207233700
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_executable.2877050955
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.2186969434
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.2016001156
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.1839029150
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.2975560412
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.1790993509
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access.431692795
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.298555027
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.3307613904
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_readback_err.1108383474
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_regwen.1375711135
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_smoke.2213387049
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all.1683402972
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1936038554
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.3124319696
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.3173436328
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.3065417639
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_alert_test.115032004
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_bijection.666874267
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_executable.798780324
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.266333393
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.954539966
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.3581685854
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.2186933969
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.2854768900
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access.215793320
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.468027332
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.2845583694
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_readback_err.4159756760
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_regwen.3690042470
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.2568205455
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_smoke.650545573
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all.3325653766
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3903667287
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.1445167942
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.1064356955
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.1730290145
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_alert_test.2841202631
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_bijection.1420293731
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_executable.3275474813
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.3838473040
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.3822820392
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.2113708706
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.659259838
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.2643201116
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access.1295724181
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.835518144
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.3536165591
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_readback_err.612995079
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_regwen.988196530
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_smoke.3291342396
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all.343739316
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3334363526
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.1968929622
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.573039859
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.237309292
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_alert_test.2792507226
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_bijection.3327893298
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_executable.2195925285
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.853391271
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.2178645807
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.1641811640
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.4039383010
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.1118282510
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access.1227357283
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.547235719
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.2698863472
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_readback_err.255189751
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_regwen.3073120713
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_smoke.2589454103
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all.3072405036
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.1004615611
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.1405787441
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.1946834647
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.2475085264
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_alert_test.581057069
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_bijection.3457824043
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_executable.3596130081
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.2407390400
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.2443825640
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.4201862999
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.1291769427
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.82691562
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access.1520591062
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.3353031423
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.2507521165
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_readback_err.4030115265
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_regwen.179904162
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_smoke.2362272821
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all.3024423364
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.2871158959
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.4280619718
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.4219559879
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.2619896920
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_alert_test.614585646
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_bijection.2402395261
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_executable.2322411892
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.3785941740
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.2908887632
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.84081866
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.1098103389
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.3618087216
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access.3747548447
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.1202835202
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.2617998915
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_readback_err.3167233470
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_regwen.2527106690
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_smoke.599224444
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all.2924579897
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3566520627
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.2150647641
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.156062023
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.3917576236
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_alert_test.564292484
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_bijection.2249393952
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_executable.2707866256
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.1006663420
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.3396306350
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.1357053761
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.3855777710
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.4219515026
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access.2735160591
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.3411424291
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.1392860454
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_readback_err.1127913270
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_regwen.3739702360
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_smoke.4034907343
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all.1560668418
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3560611509
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.16788212
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.3713429359
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.2159177290
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_alert_test.876620563
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_bijection.340201453
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.935967470
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.1990081944
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.281294171
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.2830757316
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.18952086
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access.3716573427
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.3611709962
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.476316846
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_readback_err.635787911
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_regwen.3002129627
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_smoke.181954364
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all.3689360298
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.4017994683
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.1472568335
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.1002228150
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.3653982821
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_alert_test.1835306011
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_bijection.791443751
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_executable.1105647968
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.3156888067
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.985358188
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.3983090967
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.2953492180
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.3801418860
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access.4066100393
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.1008196980
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.3012197957
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_readback_err.3865394021
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_regwen.3666634683
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_smoke.4087213035
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all.3802564460
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.830848717
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.1109509695
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.3087260735
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.785776516
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_alert_test.385274594
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_bijection.1604755364
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_executable.538266405
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.812566996
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.769476856
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.2680382578
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.261980897
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.2739490967
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access.1408620722
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.1508976984
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.38692796
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_readback_err.1664192067
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_regwen.4158661109
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_smoke.3522325587
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all.1408291104
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2160997328
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.250080147
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.4226543366
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.353715720
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_alert_test.607695945
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_bijection.2195694721
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_executable.3981321314
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.2719841952
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.1132884586
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.3517328461
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.472915615
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.668817783
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access.3337456386
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.1328242579
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.1549281192
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_readback_err.2767785561
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_regwen.1850046387
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_smoke.236589035
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all.3950631021
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.728040848
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.451026419
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.2563537599
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.2554185027
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_alert_test.2115969517
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_bijection.1582712589
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_executable.3167353014
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.2483607240
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.1332145028
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.3421165844
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.3857923844
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.4269207135
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access.3963574522
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.411426389
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.3830036528
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_readback_err.3924050875
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_regwen.2596949181
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_smoke.2750756752
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all.3109400901
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.2491852779
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.1860979152
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.1802193092
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.3351239911
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_alert_test.2027832063
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_bijection.909427713
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_executable.2980983478
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.229737776
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.4122255436
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.1075000975
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.1271303143
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.859656873
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access.2828450351
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.2714210784
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.916381841
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_readback_err.249864618
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_regwen.987261497
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_smoke.2376147496
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all.360829478
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.587839745
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.3474340005
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.3834477968
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_alert_test.1991114882
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_bijection.608633497
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_executable.3091600693
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.3439137303
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.4134742256
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.4036919515
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.2125120746
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.1620097469
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access.650383970
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.3243414841
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.3013266493
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_readback_err.1558099455
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_regwen.1642523622
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_smoke.3295304102
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all.1976608781
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.3210519824
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.1641908767
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.25151721
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.1665338836
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_alert_test.94405815
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_bijection.3544647750
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_executable.177336405
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.3631298145
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.2174414961
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.3881703075
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.690395949
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.501330863
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access.2210026771
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.2343364485
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.3501720783
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_readback_err.2477580090
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_regwen.1187128422
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_smoke.4129964094
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all.4169468258
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.978799782
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.503576046
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.2737686257
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.2420683363
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_alert_test.288232260
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_bijection.3302401709
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_executable.2416630772
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.1199818051
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.3757730409
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.2466389454
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.15615885
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.1651194681
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access.2004908242
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.3800990082
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.140447781
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_readback_err.1112258746
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_regwen.3559701715
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_smoke.1750667501
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all.1863664640
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.996491345
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.4003834536
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.161442432
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_alert_test.4174571271
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_bijection.1707749133
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_executable.2982813365
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.609994857
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.2963095148
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.716080529
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.4275532215
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.2193836422
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access.1928278405
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.1897823174
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.2791801683
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_readback_err.1411663751
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_regwen.519620326
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_smoke.92619375
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all.3567798033
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3801497963
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.1363387313
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.3661132953
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.4141517453
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_alert_test.1933503421
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_bijection.453808573
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_executable.246042504
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.1855117622
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.2657424029
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.3445008811
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.3136018112
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.2592494195
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access.398734524
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.1088667171
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.739744894
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_readback_err.2925731570
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_regwen.2857513078
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_smoke.2644256916
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all.2667478434
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.4060387879
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.1572419946
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.3759244104
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.3885915038
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_alert_test.1052702530
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_bijection.860292892
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_executable.3020176706
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.1983091712
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.4126035888
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.2515629726
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.1554919284
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.845663410
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access.730800759
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.633785257
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.509373668
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_readback_err.1679189313
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_regwen.2705941223
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_smoke.1563963245
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all.1530715382
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1492708255
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.58289271
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.3669188782
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.169035177
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_alert_test.4245314722
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_bijection.2167677521
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_executable.3800539951
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.251456485
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.3361869226
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.2076751220
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.3585120420
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.3825059317
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access.929743025
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.3710583437
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.4052211138
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_readback_err.1498696125
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_regwen.820828390
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_smoke.2395283176
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all.4179895384
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1169674419
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.958342353
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.3036418816
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.3181291204
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_alert_test.2210529529
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_bijection.3906120697
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_executable.3321101244
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.1229942000
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.4210923581
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.838804862
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.1211489016
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.3056002345
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access.2721248211
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.2506433046
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.2342070333
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_readback_err.1124099088
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_regwen.3098422601
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_smoke.4234856823
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all.1153429323
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.2293768342
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.2082033601
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.4224668094
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_alert_test.2626757170
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_bijection.2430367388
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_executable.4214720999
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.1359599343
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.771785550
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.1211700674
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.2100943951
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.58400756
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access.3876326310
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.3521143785
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.3697600683
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_readback_err.25559749
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_regwen.3084368829
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_smoke.796741229
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all.2900033566
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2555594114
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.2955215635
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.2819759361
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.3076477809
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_alert_test.260486916
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_bijection.3878143227
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_executable.1576745875
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.1066027969
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.1787717755
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.3914745392
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.1423135066
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.3212689314
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access.1093510274
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.1488092205
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.1704702456
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_readback_err.3071248056
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_regwen.4035435859
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_smoke.358779707
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all.1650661173
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.262969440
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.1430057476
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.2425045913
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.3518915459
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_alert_test.2705339739
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_bijection.694182812
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_executable.1726183605
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.3484846711
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.2019505881
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.396761714
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.3691638438
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.4060409904
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access.773131274
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.1258940548
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.1254932687
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_readback_err.34434711
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_smoke.1785396925
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all.2784301615
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.1084616099
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.3005157855
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.2986551755
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_alert_test.592723888
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_bijection.3897762068
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_executable.3565113175
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.3015751856
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.1916576417
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.322925430
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.3693600351
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.3977514472
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access.1270967574
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.3560879020
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.3736022676
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_readback_err.2239569777
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_regwen.3396372333
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_smoke.706930925
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all.3885374503
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.1702364831
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.4263349664
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.296426643
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.816807023
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.651299382
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.2771375256
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.688764838
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.1131889749
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.2313110080
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.1563653896
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.3086553308
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.2952811486
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.2123100700
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.1941041800
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_readback_err.1202706409
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.2362661049
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.2042616209
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.2680633801
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.3916576820
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.3019514011
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.2957357971
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.2703353741
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.3749903384
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.3718103458
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.2954227145
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.3543403049
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.4134658712
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.1919485146
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.3243866554
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.2376682531
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.1014278749
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_readback_err.87965347
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.1833830118
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.2687510788
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.1546710961
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.4043588243
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.2409535956
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.3247118059
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.2605708929
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.3164920638
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.2122920662
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.3998572763
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.810174109
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.20532464
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.2527433088
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.549054477
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.3680583547
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.168948443
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_readback_err.2795922266
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.4165524207
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.3237914753
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.3832317697
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3829673884
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.4089198307
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.873647811



Total test records in report: 1075
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.4005205333 Oct 09 08:49:44 AM UTC 24 Oct 09 08:49:46 AM UTC 24 49109573 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.2362661049 Oct 09 08:57:14 AM UTC 24 Oct 09 08:57:27 AM UTC 24 177995506 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.1001987648 Oct 09 08:49:45 AM UTC 24 Oct 09 08:49:47 AM UTC 24 43856763 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_readback_err.2263485710 Oct 09 08:49:45 AM UTC 24 Oct 09 08:49:47 AM UTC 24 105796858 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.2772309959 Oct 09 08:49:44 AM UTC 24 Oct 09 08:49:49 AM UTC 24 64604709 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.3458200118 Oct 09 08:49:43 AM UTC 24 Oct 09 08:49:49 AM UTC 24 866506123 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.544014536 Oct 09 08:49:45 AM UTC 24 Oct 09 08:49:50 AM UTC 24 204064285 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.4178410685 Oct 09 08:49:50 AM UTC 24 Oct 09 08:49:55 AM UTC 24 103582366 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.3195824413 Oct 09 08:49:44 AM UTC 24 Oct 09 08:49:56 AM UTC 24 683252798 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1867469380 Oct 09 08:49:45 AM UTC 24 Oct 09 08:49:58 AM UTC 24 529891097 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_smoke.681943585 Oct 09 08:49:45 AM UTC 24 Oct 09 08:49:59 AM UTC 24 722326622 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.4275257224 Oct 09 08:49:57 AM UTC 24 Oct 09 08:49:59 AM UTC 24 32067099 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.1345177711 Oct 09 08:49:51 AM UTC 24 Oct 09 08:50:03 AM UTC 24 1148906126 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_readback_err.471986454 Oct 09 08:50:01 AM UTC 24 Oct 09 08:50:03 AM UTC 24 117165767 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.2839901996 Oct 09 08:49:58 AM UTC 24 Oct 09 08:50:04 AM UTC 24 45759852 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_smoke.4068182845 Oct 09 08:49:42 AM UTC 24 Oct 09 08:50:05 AM UTC 24 3476218089 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_alert_test.739005842 Oct 09 08:50:04 AM UTC 24 Oct 09 08:50:06 AM UTC 24 30749203 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access.3787747513 Oct 09 08:49:47 AM UTC 24 Oct 09 08:50:09 AM UTC 24 236384624 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.1302539117 Oct 09 08:50:04 AM UTC 24 Oct 09 08:50:09 AM UTC 24 784440609 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.4167033068 Oct 09 08:49:58 AM UTC 24 Oct 09 08:50:13 AM UTC 24 5009307935 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.4206919581 Oct 09 08:50:16 AM UTC 24 Oct 09 08:50:19 AM UTC 24 171229689 ps
T154 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access.1322462084 Oct 09 08:50:09 AM UTC 24 Oct 09 08:50:20 AM UTC 24 1231209398 ps
T153 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_smoke.3998922530 Oct 09 08:50:05 AM UTC 24 Oct 09 08:50:24 AM UTC 24 793114398 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.4030951623 Oct 09 08:50:20 AM UTC 24 Oct 09 08:50:32 AM UTC 24 2249742027 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.1170994700 Oct 09 08:50:31 AM UTC 24 Oct 09 08:50:34 AM UTC 24 73091435 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_readback_err.2638365370 Oct 09 08:50:35 AM UTC 24 Oct 09 08:50:38 AM UTC 24 103969753 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.107940061 Oct 09 08:50:34 AM UTC 24 Oct 09 08:50:40 AM UTC 24 373551581 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.3297009471 Oct 09 08:50:34 AM UTC 24 Oct 09 08:50:44 AM UTC 24 364325108 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.4149719974 Oct 09 08:50:15 AM UTC 24 Oct 09 08:50:45 AM UTC 24 88951015 ps
T148 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_bijection.479458874 Oct 09 08:49:42 AM UTC 24 Oct 09 08:50:46 AM UTC 24 6013500936 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_alert_test.4089269700 Oct 09 08:50:46 AM UTC 24 Oct 09 08:50:48 AM UTC 24 12640281 ps
T141 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access.2226555042 Oct 09 08:49:42 AM UTC 24 Oct 09 08:50:49 AM UTC 24 383793624 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_smoke.650545573 Oct 09 08:50:46 AM UTC 24 Oct 09 08:50:51 AM UTC 24 375767809 ps
T149 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_bijection.338723861 Oct 09 08:49:46 AM UTC 24 Oct 09 08:50:51 AM UTC 24 16475511161 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.3076953609 Oct 09 08:50:45 AM UTC 24 Oct 09 08:50:51 AM UTC 24 886992540 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.692194487 Oct 09 08:50:01 AM UTC 24 Oct 09 08:50:52 AM UTC 24 1728162617 ps
T140 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.2220767628 Oct 09 08:49:43 AM UTC 24 Oct 09 08:50:52 AM UTC 24 202271051 ps
T155 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_bijection.2088726082 Oct 09 08:50:07 AM UTC 24 Oct 09 08:51:05 AM UTC 24 10397472831 ps
T156 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.2854768900 Oct 09 08:50:49 AM UTC 24 Oct 09 08:51:08 AM UTC 24 677672420 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.266333393 Oct 09 08:51:05 AM UTC 24 Oct 09 08:51:09 AM UTC 24 241196446 ps
T150 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.3758713741 Oct 09 08:49:49 AM UTC 24 Oct 09 08:51:21 AM UTC 24 574113293 ps
T151 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.2845583694 Oct 09 08:51:21 AM UTC 24 Oct 09 08:51:24 AM UTC 24 27167202 ps
T157 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.954539966 Oct 09 08:50:53 AM UTC 24 Oct 09 08:51:31 AM UTC 24 403045049 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.2186933969 Oct 09 08:51:25 AM UTC 24 Oct 09 08:51:34 AM UTC 24 226841589 ps
T158 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_readback_err.4159756760 Oct 09 08:51:35 AM UTC 24 Oct 09 08:51:37 AM UTC 24 32541006 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.3581685854 Oct 09 08:51:32 AM UTC 24 Oct 09 08:51:42 AM UTC 24 905610225 ps
T159 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.874711855 Oct 09 08:49:43 AM UTC 24 Oct 09 08:51:47 AM UTC 24 140558289 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.2568205455 Oct 09 08:51:43 AM UTC 24 Oct 09 08:51:47 AM UTC 24 1254605598 ps
T160 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_bijection.666874267 Oct 09 08:50:49 AM UTC 24 Oct 09 08:51:48 AM UTC 24 2843277160 ps
T152 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_alert_test.115032004 Oct 09 08:51:48 AM UTC 24 Oct 09 08:51:51 AM UTC 24 14511451 ps
T142 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_smoke.2376147496 Oct 09 08:51:48 AM UTC 24 Oct 09 08:52:00 AM UTC 24 63348909 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2747114521 Oct 09 08:50:39 AM UTC 24 Oct 09 08:52:11 AM UTC 24 12978485834 ps
T138 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access.215793320 Oct 09 08:50:52 AM UTC 24 Oct 09 08:52:25 AM UTC 24 601721335 ps
T143 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.1064356955 Oct 09 08:50:53 AM UTC 24 Oct 09 08:52:26 AM UTC 24 282094091 ps
T161 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.4122255436 Oct 09 08:52:26 AM UTC 24 Oct 09 08:52:32 AM UTC 24 80809314 ps
T145 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.3474340005 Oct 09 08:52:27 AM UTC 24 Oct 09 08:52:36 AM UTC 24 57425545 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.229737776 Oct 09 08:52:32 AM UTC 24 Oct 09 08:52:44 AM UTC 24 1134666507 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3903667287 Oct 09 08:51:38 AM UTC 24 Oct 09 08:52:46 AM UTC 24 17839979361 ps
T139 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access.2828450351 Oct 09 08:52:09 AM UTC 24 Oct 09 08:52:56 AM UTC 24 456058656 ps
T162 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.916381841 Oct 09 08:52:57 AM UTC 24 Oct 09 08:52:59 AM UTC 24 27850240 ps
T163 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_bijection.909427713 Oct 09 08:51:52 AM UTC 24 Oct 09 08:52:59 AM UTC 24 1726615711 ps
T164 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_readback_err.249864618 Oct 09 08:53:08 AM UTC 24 Oct 09 08:53:10 AM UTC 24 67722700 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.1075000975 Oct 09 08:53:08 AM UTC 24 Oct 09 08:53:16 AM UTC 24 356199168 ps
T165 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.1271303143 Oct 09 08:53:07 AM UTC 24 Oct 09 08:53:17 AM UTC 24 355652979 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.560671007 Oct 09 08:53:13 AM UTC 24 Oct 09 08:53:18 AM UTC 24 883167527 ps
T166 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_alert_test.2027832063 Oct 09 08:53:16 AM UTC 24 Oct 09 08:53:18 AM UTC 24 70774176 ps
T167 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_smoke.1785396925 Oct 09 08:53:18 AM UTC 24 Oct 09 08:53:38 AM UTC 24 252115013 ps
T168 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_bijection.694182812 Oct 09 08:53:19 AM UTC 24 Oct 09 08:53:44 AM UTC 24 716651378 ps
T169 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access.773131274 Oct 09 08:53:45 AM UTC 24 Oct 09 08:53:47 AM UTC 24 168086180 ps
T88 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.1901289736 Oct 09 08:50:08 AM UTC 24 Oct 09 08:53:57 AM UTC 24 2050716372 ps
T170 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.2019505881 Oct 09 08:53:58 AM UTC 24 Oct 09 08:54:01 AM UTC 24 153313607 ps
T89 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.2239552264 Oct 09 08:49:47 AM UTC 24 Oct 09 08:54:04 AM UTC 24 1961918760 ps
T146 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.3484846711 Oct 09 08:54:01 AM UTC 24 Oct 09 08:54:12 AM UTC 24 5287381981 ps
T90 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.1445167942 Oct 09 08:50:51 AM UTC 24 Oct 09 08:54:32 AM UTC 24 1618755432 ps
T171 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.1254932687 Oct 09 08:54:34 AM UTC 24 Oct 09 08:54:36 AM UTC 24 47298893 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.396761714 Oct 09 08:54:37 AM UTC 24 Oct 09 08:54:45 AM UTC 24 1594987417 ps
T147 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_readback_err.34434711 Oct 09 08:54:46 AM UTC 24 Oct 09 08:54:48 AM UTC 24 155755513 ps
T91 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.2912633314 Oct 09 08:49:42 AM UTC 24 Oct 09 08:54:52 AM UTC 24 3347833175 ps
T172 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_smoke.706930925 Oct 09 08:54:57 AM UTC 24 Oct 09 08:55:22 AM UTC 24 1557741083 ps
T173 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.3691638438 Oct 09 08:54:36 AM UTC 24 Oct 09 08:54:53 AM UTC 24 2119069919 ps
T174 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_alert_test.2705339739 Oct 09 08:54:54 AM UTC 24 Oct 09 08:54:56 AM UTC 24 13802150 ps
T175 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.3005157855 Oct 09 08:53:59 AM UTC 24 Oct 09 08:55:12 AM UTC 24 253025940 ps
T92 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.1091018111 Oct 09 08:50:11 AM UTC 24 Oct 09 08:55:35 AM UTC 24 11046255942 ps
T93 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.587839745 Oct 09 08:52:01 AM UTC 24 Oct 09 08:55:51 AM UTC 24 8203287171 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.3977514472 Oct 09 08:55:13 AM UTC 24 Oct 09 08:55:56 AM UTC 24 2175448572 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.1916576417 Oct 09 08:56:02 AM UTC 24 Oct 09 08:56:05 AM UTC 24 35656618 ps
T94 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.1176650529 Oct 09 08:49:48 AM UTC 24 Oct 09 08:56:19 AM UTC 24 26809010108 ps
T178 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.4263349664 Oct 09 08:56:05 AM UTC 24 Oct 09 08:56:22 AM UTC 24 80826687 ps
T112 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.3015751856 Oct 09 08:56:19 AM UTC 24 Oct 09 08:56:28 AM UTC 24 483244157 ps
T95 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.468027332 Oct 09 08:50:53 AM UTC 24 Oct 09 08:56:50 AM UTC 24 12215341083 ps
T179 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.3736022676 Oct 09 08:56:51 AM UTC 24 Oct 09 08:56:54 AM UTC 24 28325202 ps
T180 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_bijection.3897762068 Oct 09 08:55:23 AM UTC 24 Oct 09 08:56:58 AM UTC 24 55324430317 ps
T181 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_readback_err.2239569777 Oct 09 08:56:59 AM UTC 24 Oct 09 08:57:01 AM UTC 24 100669355 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.322925430 Oct 09 08:56:58 AM UTC 24 Oct 09 08:57:07 AM UTC 24 208602944 ps
T182 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.3693600351 Oct 09 08:56:55 AM UTC 24 Oct 09 08:57:11 AM UTC 24 442016806 ps
T183 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_alert_test.592723888 Oct 09 08:57:11 AM UTC 24 Oct 09 08:57:13 AM UTC 24 22423505 ps
T184 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access.1270967574 Oct 09 08:55:52 AM UTC 24 Oct 09 08:57:25 AM UTC 24 9122890552 ps
T185 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.2344947325 Oct 09 08:49:42 AM UTC 24 Oct 09 08:57:28 AM UTC 24 65399995164 ps
T186 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all.1714920693 Oct 09 08:49:45 AM UTC 24 Oct 09 08:57:45 AM UTC 24 10992888692 ps
T103 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_executable.1547928543 Oct 09 08:50:25 AM UTC 24 Oct 09 08:58:26 AM UTC 24 7657602156 ps
T187 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.651299382 Oct 09 08:57:26 AM UTC 24 Oct 09 08:58:27 AM UTC 24 772987209 ps
T188 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.1131889749 Oct 09 08:58:27 AM UTC 24 Oct 09 08:58:30 AM UTC 24 42499871 ps
T189 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.2952811486 Oct 09 08:57:29 AM UTC 24 Oct 09 08:58:37 AM UTC 24 201465091 ps
T190 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.688764838 Oct 09 08:58:31 AM UTC 24 Oct 09 08:58:39 AM UTC 24 850561247 ps
T191 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.1941041800 Oct 09 08:58:40 AM UTC 24 Oct 09 08:58:42 AM UTC 24 30228811 ps
T192 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.2714210784 Oct 09 08:52:12 AM UTC 24 Oct 09 08:58:59 AM UTC 24 14354468353 ps
T193 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.1563653896 Oct 09 08:58:43 AM UTC 24 Oct 09 08:59:00 AM UTC 24 1843293787 ps
T194 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_readback_err.1202706409 Oct 09 08:59:01 AM UTC 24 Oct 09 08:59:04 AM UTC 24 41250523 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.2313110080 Oct 09 08:58:59 AM UTC 24 Oct 09 08:59:05 AM UTC 24 757730093 ps
T100 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_regwen.715622790 Oct 09 08:49:56 AM UTC 24 Oct 09 08:59:23 AM UTC 24 26450729360 ps
T195 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.816807023 Oct 09 08:59:21 AM UTC 24 Oct 09 08:59:24 AM UTC 24 13796919 ps
T196 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.3916576820 Oct 09 08:58:28 AM UTC 24 Oct 09 08:59:26 AM UTC 24 495029475 ps
T197 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.2687510788 Oct 09 08:59:24 AM UTC 24 Oct 09 08:59:34 AM UTC 24 292145229 ps
T198 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.1084616099 Oct 09 08:53:39 AM UTC 24 Oct 09 08:59:47 AM UTC 24 7227891574 ps
T199 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.859656873 Oct 09 08:51:50 AM UTC 24 Oct 09 09:00:01 AM UTC 24 6039969141 ps
T200 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.3243866554 Oct 09 08:59:48 AM UTC 24 Oct 09 09:00:11 AM UTC 24 3876224825 ps
T101 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_regwen.3296713811 Oct 09 08:50:26 AM UTC 24 Oct 09 09:00:18 AM UTC 24 51584749850 ps
T201 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.3718103458 Oct 09 09:00:21 AM UTC 24 Oct 09 09:00:30 AM UTC 24 1495296259 ps
T202 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.2703353741 Oct 09 08:59:28 AM UTC 24 Oct 09 09:00:38 AM UTC 24 2566650562 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.3498642437 Oct 09 08:49:43 AM UTC 24 Oct 09 09:00:40 AM UTC 24 2889206001 ps
T203 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.1014278749 Oct 09 09:00:44 AM UTC 24 Oct 09 09:00:46 AM UTC 24 80952266 ps
T144 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.1258940548 Oct 09 08:53:48 AM UTC 24 Oct 09 09:00:49 AM UTC 24 15903398333 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.1461779571 Oct 09 08:49:51 AM UTC 24 Oct 09 09:00:50 AM UTC 24 3038926994 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_readback_err.87965347 Oct 09 09:00:51 AM UTC 24 Oct 09 09:00:54 AM UTC 24 34398443 ps
T204 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.2954227145 Oct 09 09:00:12 AM UTC 24 Oct 09 09:00:55 AM UTC 24 103906862 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.3351239911 Oct 09 08:52:37 AM UTC 24 Oct 09 09:00:56 AM UTC 24 2416362044 ps
T205 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.2957357971 Oct 09 09:00:56 AM UTC 24 Oct 09 09:00:58 AM UTC 24 22138427 ps
T206 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.3543403049 Oct 09 09:00:50 AM UTC 24 Oct 09 09:00:59 AM UTC 24 320738351 ps
T207 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.4134658712 Oct 09 09:00:47 AM UTC 24 Oct 09 09:01:02 AM UTC 24 184767140 ps
T208 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.3560879020 Oct 09 08:55:57 AM UTC 24 Oct 09 09:01:12 AM UTC 24 12515786624 ps
T209 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.3237914753 Oct 09 09:00:59 AM UTC 24 Oct 09 09:01:14 AM UTC 24 444903276 ps
T210 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.3396499361 Oct 09 08:50:06 AM UTC 24 Oct 09 09:01:23 AM UTC 24 15694038900 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.3166053246 Oct 09 08:49:42 AM UTC 24 Oct 09 09:01:25 AM UTC 24 7092391939 ps
T102 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_regwen.3695752139 Oct 09 08:49:43 AM UTC 24 Oct 09 09:01:25 AM UTC 24 6201310818 ps
T212 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.3998572763 Oct 09 09:01:23 AM UTC 24 Oct 09 09:01:26 AM UTC 24 132264780 ps
T213 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.2122920662 Oct 09 09:01:25 AM UTC 24 Oct 09 09:01:30 AM UTC 24 503203505 ps
T214 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.549054477 Oct 09 09:01:15 AM UTC 24 Oct 09 09:01:36 AM UTC 24 3602408400 ps
T133 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_executable.3565113175 Oct 09 08:56:32 AM UTC 24 Oct 09 09:01:36 AM UTC 24 29922488293 ps
T215 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.168948443 Oct 09 09:01:37 AM UTC 24 Oct 09 09:01:39 AM UTC 24 46237143 ps
T216 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.4043588243 Oct 09 09:00:19 AM UTC 24 Oct 09 09:01:43 AM UTC 24 368049118 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_readback_err.2795922266 Oct 09 09:01:40 AM UTC 24 Oct 09 09:01:43 AM UTC 24 29152099 ps
T217 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.810174109 Oct 09 09:01:40 AM UTC 24 Oct 09 09:01:50 AM UTC 24 670837292 ps
T218 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.20532464 Oct 09 09:01:37 AM UTC 24 Oct 09 09:01:50 AM UTC 24 135116828 ps
T219 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.3247118059 Oct 09 09:01:51 AM UTC 24 Oct 09 09:01:52 AM UTC 24 12080652 ps
T220 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.3065417639 Oct 09 08:51:06 AM UTC 24 Oct 09 09:01:58 AM UTC 24 5070910013 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3829673884 Oct 09 09:01:43 AM UTC 24 Oct 09 09:02:05 AM UTC 24 418751078 ps
T221 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.873647811 Oct 09 09:01:24 AM UTC 24 Oct 09 09:02:14 AM UTC 24 451271039 ps
T222 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.2680633801 Oct 09 08:57:29 AM UTC 24 Oct 09 09:02:28 AM UTC 24 2679445092 ps
T223 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.1702364831 Oct 09 08:55:36 AM UTC 24 Oct 09 09:02:32 AM UTC 24 11967581901 ps
T224 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.3866816591 Oct 09 09:02:32 AM UTC 24 Oct 09 09:02:35 AM UTC 24 118818734 ps
T225 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.3290291698 Oct 09 09:02:36 AM UTC 24 Oct 09 09:02:48 AM UTC 24 65043553 ps
T226 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.2605708929 Oct 09 09:01:03 AM UTC 24 Oct 09 09:02:51 AM UTC 24 31162872535 ps
T227 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_bijection.243260019 Oct 09 09:01:59 AM UTC 24 Oct 09 09:02:54 AM UTC 24 7536138593 ps
T228 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.3926393620 Oct 09 09:02:55 AM UTC 24 Oct 09 09:02:58 AM UTC 24 85623946 ps
T229 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.180158246 Oct 09 09:02:49 AM UTC 24 Oct 09 09:02:58 AM UTC 24 421386090 ps
T230 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.234191611 Oct 09 09:02:59 AM UTC 24 Oct 09 09:03:07 AM UTC 24 67926615 ps
T231 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_readback_err.2188572485 Oct 09 09:03:09 AM UTC 24 Oct 09 09:03:11 AM UTC 24 33578224 ps
T232 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.1546710961 Oct 09 08:59:35 AM UTC 24 Oct 09 09:03:13 AM UTC 24 8029069929 ps
T233 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.2667872049 Oct 09 09:02:58 AM UTC 24 Oct 09 09:03:17 AM UTC 24 2286044892 ps
T234 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_alert_test.1983711007 Oct 09 09:03:18 AM UTC 24 Oct 09 09:03:20 AM UTC 24 14833085 ps
T235 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_smoke.4289633849 Oct 09 09:01:52 AM UTC 24 Oct 09 09:03:40 AM UTC 24 3682890963 ps
T236 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.2123100700 Oct 09 08:57:46 AM UTC 24 Oct 09 09:03:42 AM UTC 24 31721748019 ps
T237 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access.2239235865 Oct 09 09:02:15 AM UTC 24 Oct 09 09:04:06 AM UTC 24 248870289 ps
T238 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access.890803073 Oct 09 09:04:07 AM UTC 24 Oct 09 09:04:15 AM UTC 24 248396241 ps
T239 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_bijection.2235818963 Oct 09 09:03:40 AM UTC 24 Oct 09 09:04:31 AM UTC 24 2430261850 ps
T240 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.2527433088 Oct 09 09:00:59 AM UTC 24 Oct 09 09:04:32 AM UTC 24 2237065341 ps
T241 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all.2650985909 Oct 09 09:03:14 AM UTC 24 Oct 09 09:04:34 AM UTC 24 4210874851 ps
T242 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.4017493840 Oct 09 09:04:35 AM UTC 24 Oct 09 09:04:44 AM UTC 24 522893389 ps
T243 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_smoke.2659948192 Oct 09 09:03:21 AM UTC 24 Oct 09 09:04:52 AM UTC 24 3943780610 ps
T244 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.2376682531 Oct 09 09:00:02 AM UTC 24 Oct 09 09:04:53 AM UTC 24 22501599697 ps
T134 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_executable.1726183605 Oct 09 08:54:13 AM UTC 24 Oct 09 09:04:56 AM UTC 24 9651978868 ps
T245 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.1389189725 Oct 09 09:04:57 AM UTC 24 Oct 09 09:04:59 AM UTC 24 78554153 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.781458157 Oct 09 09:03:12 AM UTC 24 Oct 09 09:05:01 AM UTC 24 24534093707 ps
T246 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.3670593924 Oct 09 09:05:02 AM UTC 24 Oct 09 09:05:11 AM UTC 24 1355212273 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2636185169 Oct 09 08:59:04 AM UTC 24 Oct 09 09:05:15 AM UTC 24 1246422906 ps
T247 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_readback_err.4148923456 Oct 09 09:05:12 AM UTC 24 Oct 09 09:05:15 AM UTC 24 145126924 ps
T248 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.2787641697 Oct 09 09:05:00 AM UTC 24 Oct 09 09:05:16 AM UTC 24 1383716724 ps
T249 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_alert_test.3868911106 Oct 09 09:05:18 AM UTC 24 Oct 09 09:05:20 AM UTC 24 33902527 ps
T250 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_smoke.3306672495 Oct 09 09:05:21 AM UTC 24 Oct 09 09:05:30 AM UTC 24 259076323 ps
T251 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.3019514011 Oct 09 09:00:31 AM UTC 24 Oct 09 09:05:48 AM UTC 24 4703172621 ps
T252 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.1370034540 Oct 09 09:04:33 AM UTC 24 Oct 09 09:05:53 AM UTC 24 145167314 ps
T131 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.4165524207 Oct 09 09:01:32 AM UTC 24 Oct 09 09:05:58 AM UTC 24 1455981668 ps
T130 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_executable.2402257933 Oct 09 08:49:52 AM UTC 24 Oct 09 09:06:08 AM UTC 24 12487648653 ps
T253 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.1071597411 Oct 09 09:04:32 AM UTC 24 Oct 09 09:06:16 AM UTC 24 429597077 ps
T254 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.4257775205 Oct 09 08:50:21 AM UTC 24 Oct 09 09:06:16 AM UTC 24 50888054449 ps
T255 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.898918973 Oct 09 09:06:17 AM UTC 24 Oct 09 09:06:26 AM UTC 24 6452772997 ps
T132 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_executable.798780324 Oct 09 08:51:09 AM UTC 24 Oct 09 09:06:28 AM UTC 24 2905356043 ps
T256 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.85225778 Oct 09 09:02:06 AM UTC 24 Oct 09 09:06:33 AM UTC 24 4496271550 ps
T257 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.519966988 Oct 09 09:02:49 AM UTC 24 Oct 09 09:06:34 AM UTC 24 2286427895 ps
T258 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.2093417482 Oct 09 09:06:35 AM UTC 24 Oct 09 09:06:37 AM UTC 24 89431754 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access.4262161840 Oct 09 09:06:05 AM UTC 24 Oct 09 09:06:41 AM UTC 24 165123286 ps
T260 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.3313613562 Oct 09 09:06:09 AM UTC 24 Oct 09 09:06:42 AM UTC 24 106006317 ps
T261 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_bijection.2663835791 Oct 09 09:05:49 AM UTC 24 Oct 09 09:06:43 AM UTC 24 1890582037 ps
T262 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_readback_err.2292541532 Oct 09 09:06:42 AM UTC 24 Oct 09 09:06:45 AM UTC 24 98714793 ps
T263 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.237654365 Oct 09 09:06:38 AM UTC 24 Oct 09 09:06:46 AM UTC 24 335555741 ps
T264 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.3175681103 Oct 09 09:06:42 AM UTC 24 Oct 09 09:06:47 AM UTC 24 205417549 ps
T265 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_alert_test.3325772363 Oct 09 09:06:47 AM UTC 24 Oct 09 09:06:49 AM UTC 24 38219758 ps
T266 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_smoke.2439842169 Oct 09 09:06:48 AM UTC 24 Oct 09 09:06:54 AM UTC 24 185587725 ps
T267 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_executable.420416680 Oct 09 09:06:29 AM UTC 24 Oct 09 09:07:13 AM UTC 24 2260549256 ps
T268 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.4089198307 Oct 09 09:01:13 AM UTC 24 Oct 09 09:07:15 AM UTC 24 6875637178 ps
T269 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access.423440959 Oct 09 09:07:14 AM UTC 24 Oct 09 09:07:18 AM UTC 24 274996018 ps
T270 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.3014772089 Oct 09 09:03:43 AM UTC 24 Oct 09 09:07:32 AM UTC 24 9030239676 ps
T271 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.4060409904 Oct 09 08:53:19 AM UTC 24 Oct 09 09:07:47 AM UTC 24 7364854476 ps
T272 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.2561964725 Oct 09 09:06:17 AM UTC 24 Oct 09 09:07:47 AM UTC 24 183453298 ps
T273 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.2981674684 Oct 09 09:07:41 AM UTC 24 Oct 09 09:07:51 AM UTC 24 459416331 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_regwen.3690042470 Oct 09 08:51:10 AM UTC 24 Oct 09 09:07:58 AM UTC 24 13962723990 ps
T274 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.157850880 Oct 09 09:07:59 AM UTC 24 Oct 09 09:08:01 AM UTC 24 29927253 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_regwen.1840678601 Oct 09 09:07:52 AM UTC 24 Oct 09 09:08:13 AM UTC 24 1083945538 ps
T276 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.1708851860 Oct 09 09:08:02 AM UTC 24 Oct 09 09:08:19 AM UTC 24 5975703821 ps
T277 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.1032796144 Oct 09 09:08:14 AM UTC 24 Oct 09 09:08:20 AM UTC 24 100787779 ps
T278 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_readback_err.2953706890 Oct 09 09:08:19 AM UTC 24 Oct 09 09:08:22 AM UTC 24 94072317 ps
T279 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.3216824505 Oct 09 09:02:29 AM UTC 24 Oct 09 09:08:32 AM UTC 24 36543177532 ps
T280 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_bijection.4100449135 Oct 09 09:06:50 AM UTC 24 Oct 09 09:08:33 AM UTC 24 10424340857 ps
T281 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_alert_test.1636036326 Oct 09 09:08:33 AM UTC 24 Oct 09 09:08:35 AM UTC 24 36448774 ps
T136 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.2771375256 Oct 09 08:58:40 AM UTC 24 Oct 09 09:08:42 AM UTC 24 8069282279 ps
T282 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.2624464345 Oct 09 09:07:18 AM UTC 24 Oct 09 09:08:43 AM UTC 24 228179304 ps
T283 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_smoke.1159863495 Oct 09 09:08:34 AM UTC 24 Oct 09 09:08:47 AM UTC 24 158764343 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2215531823 Oct 09 09:06:43 AM UTC 24 Oct 09 09:09:00 AM UTC 24 6453753882 ps
T284 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.4001712528 Oct 09 09:04:16 AM UTC 24 Oct 09 09:09:03 AM UTC 24 52401368132 ps
T285 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_bijection.2875753931 Oct 09 09:08:42 AM UTC 24 Oct 09 09:09:11 AM UTC 24 1377707062 ps
T286 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.1222002769 Oct 09 09:09:12 AM UTC 24 Oct 09 09:09:24 AM UTC 24 77297218 ps
T287 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.2939676602 Oct 09 09:07:32 AM UTC 24 Oct 09 09:09:30 AM UTC 24 2428874564 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.26632733 Oct 09 09:07:48 AM UTC 24 Oct 09 09:09:34 AM UTC 24 1629150907 ps
T289 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.1799437164 Oct 09 09:09:25 AM UTC 24 Oct 09 09:09:35 AM UTC 24 713392001 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access.4117128851 Oct 09 09:08:47 AM UTC 24 Oct 09 09:09:36 AM UTC 24 313386067 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.2608704881 Oct 09 09:09:37 AM UTC 24 Oct 09 09:09:40 AM UTC 24 33080659 ps
T292 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.3380420292 Oct 09 09:09:04 AM UTC 24 Oct 09 09:09:43 AM UTC 24 356986190 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.2486168895 Oct 09 09:09:44 AM UTC 24 Oct 09 09:09:49 AM UTC 24 351850220 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.4160389534 Oct 09 09:09:41 AM UTC 24 Oct 09 09:09:49 AM UTC 24 453489047 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_readback_err.4213836320 Oct 09 09:09:50 AM UTC 24 Oct 09 09:09:52 AM UTC 24 135304829 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.3680583547 Oct 09 09:01:19 AM UTC 24 Oct 09 09:10:05 AM UTC 24 206493659004 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_regwen.882633667 Oct 09 09:02:52 AM UTC 24 Oct 09 09:10:05 AM UTC 24 1441030663 ps
T297 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_smoke.628672836 Oct 09 09:13:26 AM UTC 24 Oct 09 09:14:18 AM UTC 24 131678147 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_alert_test.2882450624 Oct 09 09:10:06 AM UTC 24 Oct 09 09:10:08 AM UTC 24 12410018 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all.3885374503 Oct 09 08:57:08 AM UTC 24 Oct 09 09:10:43 AM UTC 24 9850225994 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.2307556932 Oct 09 09:01:54 AM UTC 24 Oct 09 09:10:50 AM UTC 24 54679754225 ps
T301 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.73933840 Oct 09 09:06:06 AM UTC 24 Oct 09 09:10:54 AM UTC 24 19339475361 ps
T302 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_smoke.2225528867 Oct 09 09:10:06 AM UTC 24 Oct 09 09:10:57 AM UTC 24 574369128 ps
T135 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_executable.2314024083 Oct 09 08:49:43 AM UTC 24 Oct 09 09:11:02 AM UTC 24 50064568227 ps
T303 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.2775228154 Oct 09 09:06:55 AM UTC 24 Oct 09 09:11:05 AM UTC 24 9480314951 ps
T304 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.2759602515 Oct 09 09:11:06 AM UTC 24 Oct 09 09:11:09 AM UTC 24 549004349 ps
T305 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access.842160469 Oct 09 09:10:52 AM UTC 24 Oct 09 09:11:12 AM UTC 24 4806537260 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2220186186 Oct 09 09:08:21 AM UTC 24 Oct 09 09:11:26 AM UTC 24 6342354139 ps
T111 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_regwen.1344511603 Oct 09 08:54:27 AM UTC 24 Oct 09 09:11:44 AM UTC 24 203442151535 ps
T306 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.4110472008 Oct 09 09:11:45 AM UTC 24 Oct 09 09:11:47 AM UTC 24 28779755 ps
T307 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.296426643 Oct 09 08:58:37 AM UTC 24 Oct 09 09:11:49 AM UTC 24 8295055123 ps
T308 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.779664855 Oct 09 09:10:10 AM UTC 24 Oct 09 09:11:50 AM UTC 24 16066647151 ps
T309 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_readback_err.965022959 Oct 09 09:11:51 AM UTC 24 Oct 09 09:11:54 AM UTC 24 29173570 ps
T310 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.2583463775 Oct 09 09:09:30 AM UTC 24 Oct 09 09:11:55 AM UTC 24 4584787914 ps
T311 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_bijection.3311791748 Oct 09 09:10:47 AM UTC 24 Oct 09 09:11:57 AM UTC 24 2298620684 ps
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