Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.63 99.48 96.05 99.72 100.00 97.29 99.12 98.72


Total tests in report: 1077
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
71.09 71.09 91.74 91.74 70.78 70.78 83.84 83.84 33.33 33.33 82.50 82.50 93.57 93.57 41.86 41.86 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.3762405604
86.24 15.15 96.17 4.43 83.37 12.59 93.17 9.33 71.43 38.10 88.00 5.50 95.47 1.90 76.05 34.19 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.1200060030
91.20 4.96 97.74 1.57 83.85 0.48 93.17 0.00 100.00 28.57 91.00 3.00 95.47 0.00 77.15 1.10 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1676035560
92.89 1.69 98.09 0.35 87.05 3.21 93.38 0.21 100.00 0.00 93.25 2.25 95.47 0.00 83.00 5.85 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_regwen.22092432
94.14 1.25 98.43 0.35 89.43 2.38 96.43 3.05 100.00 0.00 94.75 1.50 96.05 0.58 83.91 0.91 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.4083078564
95.12 0.97 99.04 0.61 91.57 2.14 98.30 1.87 100.00 0.00 96.75 2.00 96.05 0.00 84.10 0.18 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_readback_err.4086983346
95.87 0.76 99.04 0.00 91.92 0.36 98.30 0.00 100.00 0.00 96.75 0.00 96.05 0.00 89.03 4.94 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1175448259
96.38 0.51 99.30 0.26 91.92 0.00 98.30 0.00 100.00 0.00 97.00 0.25 96.20 0.15 91.96 2.93 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.1278258187
96.73 0.35 99.30 0.00 91.92 0.00 98.40 0.10 100.00 0.00 97.00 0.00 97.08 0.88 93.42 1.46 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.491625071
97.02 0.28 99.30 0.00 92.16 0.24 98.47 0.07 100.00 0.00 97.00 0.00 98.39 1.32 93.78 0.37 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1578063038
97.26 0.25 99.30 0.00 92.28 0.12 98.47 0.00 100.00 0.00 97.00 0.00 98.54 0.15 95.25 1.46 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all.19719446
97.43 0.17 99.39 0.09 92.28 0.00 99.58 1.11 100.00 0.00 97.00 0.00 98.54 0.00 95.25 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.3935914537
97.56 0.13 99.39 0.00 92.28 0.00 99.58 0.00 100.00 0.00 97.00 0.00 98.54 0.00 96.16 0.91 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_executable.2235421763
97.69 0.13 99.48 0.09 92.28 0.00 99.58 0.00 100.00 0.00 97.25 0.25 98.54 0.00 96.71 0.55 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3220071000
97.77 0.08 99.48 0.00 92.28 0.00 99.58 0.00 100.00 0.00 97.25 0.00 99.12 0.58 96.71 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.1288198512
97.85 0.08 99.48 0.00 92.28 0.00 99.58 0.00 100.00 0.00 97.25 0.00 99.12 0.00 97.26 0.55 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2353518303
97.92 0.07 99.48 0.00 92.64 0.36 99.69 0.10 100.00 0.00 97.25 0.00 99.12 0.00 97.26 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.3453598811
97.97 0.05 99.48 0.00 92.76 0.12 99.69 0.00 100.00 0.00 97.50 0.25 99.12 0.00 97.26 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1634296298
98.02 0.05 99.48 0.00 92.76 0.00 99.69 0.00 100.00 0.00 97.50 0.00 99.12 0.00 97.62 0.37 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3482809342
98.08 0.05 99.48 0.00 92.76 0.00 99.69 0.00 100.00 0.00 97.50 0.00 99.12 0.00 97.99 0.37 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.3693836917
98.13 0.05 99.48 0.00 92.76 0.00 99.69 0.00 100.00 0.00 97.50 0.00 99.12 0.00 98.35 0.37 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_executable.1235889636
98.15 0.03 99.48 0.00 92.76 0.00 99.69 0.00 100.00 0.00 97.50 0.00 99.12 0.00 98.54 0.18 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2625954553
98.18 0.03 99.48 0.00 92.76 0.00 99.69 0.00 100.00 0.00 97.50 0.00 99.12 0.00 98.72 0.18 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all.2572105660
98.20 0.02 99.48 0.00 92.87 0.12 99.72 0.03 100.00 0.00 97.50 0.00 99.12 0.00 98.72 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_readback_err.1484721549
98.22 0.02 99.48 0.00 92.99 0.12 99.72 0.00 100.00 0.00 97.50 0.00 99.12 0.00 98.72 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all.1982833722

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4148850169
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1380696012
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.952151955
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2168543732
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2106289782
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2186718267
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.89195727
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.818514860
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.4103068146
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.793268684
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.363649256
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3710555463
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4130873243
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3191480270
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1423911711
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2197264771
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1934306797
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1327409819
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2809706724
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1329694547
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1895459549
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1631493143
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1461756266
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3453543347
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.372066117
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2925153333
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2192917901
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1429320391
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1022904728
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3923168948
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3028126366
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2983838630
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.18918613
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.917317686
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1200821636
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3195214948
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.690359835
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2533151107
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3772430325
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1438683428
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.690510835
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.507428732
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1390421567
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2763284460
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2122377677
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3667200699
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2239157521
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.56116726
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2833875307
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2669215487
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1822381964
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3636683073
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1730372479
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1368149235
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1159531857
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2328526655
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3116290785
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1433909950
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3682130714
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1977352053
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.4013449677
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3296500446
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2902612973
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1389636936
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.5947504
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3802486803
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1841879720
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.194188528
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.703596413
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2833990215
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.785767854
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3195555577
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3295380556
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.252481284
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3649915872
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3056003679
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3914173576
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2700564088
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1649076052
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3294006067
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3326269633
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1807145668
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/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_readback_err.4002866844
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.385165969
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/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.4191806439



Total test records in report: 1077
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.107765991 Oct 15 03:03:46 AM UTC 24 Oct 15 03:03:49 AM UTC 24 54058094 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_readback_err.1484721549 Oct 15 03:03:47 AM UTC 24 Oct 15 03:03:49 AM UTC 24 221121997 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.3453598811 Oct 15 03:03:50 AM UTC 24 Oct 15 03:03:52 AM UTC 24 14499800 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.3228409698 Oct 15 03:03:47 AM UTC 24 Oct 15 03:03:53 AM UTC 24 292266743 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.491625071 Oct 15 03:03:47 AM UTC 24 Oct 15 03:03:54 AM UTC 24 128543185 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.1065212670 Oct 15 03:03:49 AM UTC 24 Oct 15 03:03:56 AM UTC 24 387797660 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_smoke.1147463649 Oct 15 03:03:45 AM UTC 24 Oct 15 03:03:57 AM UTC 24 489801029 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.3762405604 Oct 15 03:03:46 AM UTC 24 Oct 15 03:03:58 AM UTC 24 691313360 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.1328781148 Oct 15 03:03:46 AM UTC 24 Oct 15 03:03:59 AM UTC 24 292841964 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.2079682794 Oct 15 03:03:59 AM UTC 24 Oct 15 03:04:04 AM UTC 24 714945893 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access.125948779 Oct 15 03:03:55 AM UTC 24 Oct 15 03:04:06 AM UTC 24 1164059345 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.3935914537 Oct 15 03:04:07 AM UTC 24 Oct 15 03:04:09 AM UTC 24 38240660 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.2315784572 Oct 15 03:03:46 AM UTC 24 Oct 15 03:04:09 AM UTC 24 86424284 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_smoke.3572818781 Oct 15 03:03:50 AM UTC 24 Oct 15 03:04:10 AM UTC 24 948964499 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_readback_err.4086983346 Oct 15 03:04:11 AM UTC 24 Oct 15 03:04:14 AM UTC 24 122213181 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.1237018545 Oct 15 03:04:10 AM UTC 24 Oct 15 03:04:17 AM UTC 24 282766685 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.2650872947 Oct 15 03:04:10 AM UTC 24 Oct 15 03:04:20 AM UTC 24 183070740 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.3644505507 Oct 15 03:04:21 AM UTC 24 Oct 15 03:04:26 AM UTC 24 288273175 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_bijection.239079542 Oct 15 03:03:45 AM UTC 24 Oct 15 03:04:27 AM UTC 24 4569541952 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_alert_test.2614041043 Oct 15 03:04:28 AM UTC 24 Oct 15 03:04:30 AM UTC 24 34434101 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.1202375767 Oct 15 03:03:59 AM UTC 24 Oct 15 03:04:32 AM UTC 24 250610100 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_bijection.2239025290 Oct 15 03:03:53 AM UTC 24 Oct 15 03:04:36 AM UTC 24 2620988921 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.4261468421 Oct 15 03:03:57 AM UTC 24 Oct 15 03:04:50 AM UTC 24 120405677 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3303719039 Oct 15 03:03:48 AM UTC 24 Oct 15 03:04:53 AM UTC 24 25758648344 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access.2891505512 Oct 15 03:04:51 AM UTC 24 Oct 15 03:05:00 AM UTC 24 372940544 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.2490153473 Oct 15 03:05:01 AM UTC 24 Oct 15 03:05:07 AM UTC 24 178856249 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.3899609123 Oct 15 03:05:17 AM UTC 24 Oct 15 03:05:21 AM UTC 24 281996865 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access.775477252 Oct 15 03:03:45 AM UTC 24 Oct 15 03:05:32 AM UTC 24 743830131 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.2469503547 Oct 15 03:05:07 AM UTC 24 Oct 15 03:05:33 AM UTC 24 363010607 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_bijection.4261897728 Oct 15 03:04:33 AM UTC 24 Oct 15 03:05:59 AM UTC 24 2475881522 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.1295351167 Oct 15 03:06:00 AM UTC 24 Oct 15 03:06:03 AM UTC 24 28411898 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_smoke.617646843 Oct 15 03:04:29 AM UTC 24 Oct 15 03:06:08 AM UTC 24 1446436514 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.868399994 Oct 15 03:06:01 AM UTC 24 Oct 15 03:06:11 AM UTC 24 575704917 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_readback_err.367163301 Oct 15 03:06:09 AM UTC 24 Oct 15 03:06:12 AM UTC 24 101131877 ps
T86 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.2405242231 Oct 15 03:06:04 AM UTC 24 Oct 15 03:06:12 AM UTC 24 985614788 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.4083078564 Oct 15 03:06:13 AM UTC 24 Oct 15 03:06:17 AM UTC 24 293753678 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_alert_test.3055320514 Oct 15 03:06:18 AM UTC 24 Oct 15 03:06:21 AM UTC 24 16360852 ps
T188 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_smoke.4122225139 Oct 15 03:06:19 AM UTC 24 Oct 15 03:06:41 AM UTC 24 1067309379 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.1200060030 Oct 15 03:06:11 AM UTC 24 Oct 15 03:06:55 AM UTC 24 1433392542 ps
T197 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access.2417330430 Oct 15 03:06:56 AM UTC 24 Oct 15 03:06:59 AM UTC 24 59598449 ps
T193 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_bijection.3783979071 Oct 15 03:06:27 AM UTC 24 Oct 15 03:07:35 AM UTC 24 2831465001 ps
T103 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.1278258187 Oct 15 03:03:45 AM UTC 24 Oct 15 03:07:47 AM UTC 24 6990277189 ps
T194 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.2241741829 Oct 15 03:07:48 AM UTC 24 Oct 15 03:07:54 AM UTC 24 52179598 ps
T71 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.2334977173 Oct 15 03:07:55 AM UTC 24 Oct 15 03:08:06 AM UTC 24 1728033474 ps
T104 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.817612492 Oct 15 03:04:37 AM UTC 24 Oct 15 03:08:14 AM UTC 24 36969953215 ps
T198 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.1550215546 Oct 15 03:08:15 AM UTC 24 Oct 15 03:08:17 AM UTC 24 31471513 ps
T196 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.2427681927 Oct 15 03:07:36 AM UTC 24 Oct 15 03:08:19 AM UTC 24 101171708 ps
T87 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.1488757112 Oct 15 03:08:20 AM UTC 24 Oct 15 03:08:27 AM UTC 24 753087757 ps
T192 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_readback_err.3165884415 Oct 15 03:08:28 AM UTC 24 Oct 15 03:08:30 AM UTC 24 51438974 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.3763392540 Oct 15 03:08:18 AM UTC 24 Oct 15 03:08:33 AM UTC 24 1883315644 ps
T105 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.4045754630 Oct 15 03:03:56 AM UTC 24 Oct 15 03:09:14 AM UTC 24 13006976352 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.541996749 Oct 15 03:09:16 AM UTC 24 Oct 15 03:09:20 AM UTC 24 448678180 ps
T106 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.788424850 Oct 15 03:03:54 AM UTC 24 Oct 15 03:09:20 AM UTC 24 2622941788 ps
T107 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.2171299145 Oct 15 03:03:45 AM UTC 24 Oct 15 03:09:22 AM UTC 24 2959675971 ps
T191 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_alert_test.222426579 Oct 15 03:09:21 AM UTC 24 Oct 15 03:09:23 AM UTC 24 82545105 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_regwen.3328439282 Oct 15 03:05:34 AM UTC 24 Oct 15 03:09:25 AM UTC 24 1444077087 ps
T199 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access.1832017420 Oct 15 03:09:26 AM UTC 24 Oct 15 03:09:51 AM UTC 24 10877346172 ps
T187 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.2922603801 Oct 15 03:04:31 AM UTC 24 Oct 15 03:10:04 AM UTC 24 29650430817 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2909040747 Oct 15 03:08:31 AM UTC 24 Oct 15 03:10:05 AM UTC 24 921894634 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.2019943455 Oct 15 03:10:07 AM UTC 24 Oct 15 03:10:14 AM UTC 24 796191875 ps
T200 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.3631106902 Oct 15 03:10:05 AM UTC 24 Oct 15 03:10:48 AM UTC 24 107194623 ps
T201 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.325358415 Oct 15 03:11:04 AM UTC 24 Oct 15 03:11:07 AM UTC 24 31894494 ps
T202 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_bijection.1332336854 Oct 15 03:09:24 AM UTC 24 Oct 15 03:11:10 AM UTC 24 3868078129 ps
T203 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.3466314803 Oct 15 03:09:52 AM UTC 24 Oct 15 03:11:11 AM UTC 24 129871322 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_executable.2057903290 Oct 15 03:04:02 AM UTC 24 Oct 15 03:11:12 AM UTC 24 889911769 ps
T204 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_smoke.1936375932 Oct 15 03:09:21 AM UTC 24 Oct 15 03:11:12 AM UTC 24 513593169 ps
T205 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_readback_err.779018462 Oct 15 03:11:12 AM UTC 24 Oct 15 03:11:14 AM UTC 24 151865392 ps
T206 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.1674925423 Oct 15 03:11:07 AM UTC 24 Oct 15 03:11:15 AM UTC 24 76888339 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.3584881270 Oct 15 03:11:10 AM UTC 24 Oct 15 03:11:16 AM UTC 24 106084260 ps
T207 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_alert_test.3297686594 Oct 15 03:11:16 AM UTC 24 Oct 15 03:11:18 AM UTC 24 16891651 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.3110937218 Oct 15 03:11:15 AM UTC 24 Oct 15 03:11:20 AM UTC 24 2345864110 ps
T108 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.3241746950 Oct 15 03:06:42 AM UTC 24 Oct 15 03:11:26 AM UTC 24 6645365316 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.3769660127 Oct 15 03:11:13 AM UTC 24 Oct 15 03:11:30 AM UTC 24 135952601 ps
T208 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_smoke.4200126524 Oct 15 03:11:17 AM UTC 24 Oct 15 03:11:39 AM UTC 24 2640751745 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.2368771815 Oct 15 03:03:46 AM UTC 24 Oct 15 03:12:34 AM UTC 24 8401718066 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.1251981301 Oct 15 03:05:21 AM UTC 24 Oct 15 03:12:37 AM UTC 24 1446240043 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.2374469959 Oct 15 03:07:56 AM UTC 24 Oct 15 03:12:43 AM UTC 24 6834134803 ps
T209 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_smoke.680399872 Oct 15 03:13:43 AM UTC 24 Oct 15 03:14:59 AM UTC 24 636537011 ps
T210 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access.1851554261 Oct 15 03:11:30 AM UTC 24 Oct 15 03:12:44 AM UTC 24 667479944 ps
T175 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.409045687 Oct 15 03:12:43 AM UTC 24 Oct 15 03:12:46 AM UTC 24 410546964 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_bijection.3059817811 Oct 15 03:11:21 AM UTC 24 Oct 15 03:13:02 AM UTC 24 17844376409 ps
T212 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.3316836701 Oct 15 03:12:36 AM UTC 24 Oct 15 03:13:07 AM UTC 24 286194872 ps
T213 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.3612261379 Oct 15 03:13:08 AM UTC 24 Oct 15 03:13:10 AM UTC 24 106365914 ps
T214 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.2844407162 Oct 15 03:13:11 AM UTC 24 Oct 15 03:13:25 AM UTC 24 142165425 ps
T88 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.540767298 Oct 15 03:13:23 AM UTC 24 Oct 15 03:13:28 AM UTC 24 153892002 ps
T195 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_readback_err.2810466919 Oct 15 03:13:26 AM UTC 24 Oct 15 03:13:28 AM UTC 24 52695224 ps
T109 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.1017295965 Oct 15 03:07:00 AM UTC 24 Oct 15 03:13:39 AM UTC 24 12701035642 ps
T215 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_alert_test.353722359 Oct 15 03:13:40 AM UTC 24 Oct 15 03:13:42 AM UTC 24 32308333 ps
T216 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.1469270052 Oct 15 03:12:37 AM UTC 24 Oct 15 03:13:42 AM UTC 24 142936559 ps
T110 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.3917162099 Oct 15 03:04:54 AM UTC 24 Oct 15 03:14:26 AM UTC 24 99102394822 ps
T217 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_bijection.1210793087 Oct 15 03:14:11 AM UTC 24 Oct 15 03:14:38 AM UTC 24 436605414 ps
T218 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access.1949550191 Oct 15 03:14:39 AM UTC 24 Oct 15 03:15:02 AM UTC 24 2146620741 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.2135915882 Oct 15 03:14:59 AM UTC 24 Oct 15 03:15:03 AM UTC 24 796875239 ps
T219 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.2943378858 Oct 15 03:14:57 AM UTC 24 Oct 15 03:15:28 AM UTC 24 358709713 ps
T220 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.1811880699 Oct 15 03:15:29 AM UTC 24 Oct 15 03:15:31 AM UTC 24 83213400 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.1688294037 Oct 15 03:15:32 AM UTC 24 Oct 15 03:15:40 AM UTC 24 228853658 ps
T89 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.1248135038 Oct 15 03:15:41 AM UTC 24 Oct 15 03:15:46 AM UTC 24 201661899 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_readback_err.1651636130 Oct 15 03:15:47 AM UTC 24 Oct 15 03:15:51 AM UTC 24 49206029 ps
T221 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.1503426992 Oct 15 03:14:47 AM UTC 24 Oct 15 03:15:52 AM UTC 24 122164118 ps
T123 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_regwen.226307835 Oct 15 03:04:05 AM UTC 24 Oct 15 03:16:13 AM UTC 24 19923586909 ps
T222 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.3947376031 Oct 15 03:04:00 AM UTC 24 Oct 15 03:16:15 AM UTC 24 5517065970 ps
T223 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_alert_test.3476506389 Oct 15 03:16:13 AM UTC 24 Oct 15 03:16:15 AM UTC 24 42346283 ps
T189 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.1725395808 Oct 15 03:11:40 AM UTC 24 Oct 15 03:16:34 AM UTC 24 46477167203 ps
T224 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.2920866512 Oct 15 03:16:35 AM UTC 24 Oct 15 03:16:38 AM UTC 24 225530025 ps
T225 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.3693836917 Oct 15 03:03:51 AM UTC 24 Oct 15 03:16:42 AM UTC 24 46274423019 ps
T226 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.679181906 Oct 15 03:16:15 AM UTC 24 Oct 15 03:16:49 AM UTC 24 4294587760 ps
T227 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.2439274430 Oct 15 03:11:19 AM UTC 24 Oct 15 03:16:57 AM UTC 24 22378426276 ps
T228 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.3966481536 Oct 15 03:16:50 AM UTC 24 Oct 15 03:17:00 AM UTC 24 2497251973 ps
T229 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.1668734868 Oct 15 03:11:26 AM UTC 24 Oct 15 03:17:40 AM UTC 24 14109318496 ps
T230 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.559885544 Oct 15 03:17:46 AM UTC 24 Oct 15 03:17:48 AM UTC 24 53132322 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.3556141242 Oct 15 03:17:49 AM UTC 24 Oct 15 03:18:01 AM UTC 24 688749631 ps
T231 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.2424592054 Oct 15 03:09:42 AM UTC 24 Oct 15 03:18:09 AM UTC 24 16406108858 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_executable.3359048649 Oct 15 03:03:46 AM UTC 24 Oct 15 03:18:10 AM UTC 24 9948674356 ps
T232 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.1837033492 Oct 15 03:18:02 AM UTC 24 Oct 15 03:18:11 AM UTC 24 421405247 ps
T233 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_readback_err.3410850992 Oct 15 03:18:11 AM UTC 24 Oct 15 03:18:13 AM UTC 24 96369179 ps
T234 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.228003058 Oct 15 03:18:14 AM UTC 24 Oct 15 03:18:16 AM UTC 24 46124023 ps
T235 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.1227961408 Oct 15 03:09:25 AM UTC 24 Oct 15 03:18:22 AM UTC 24 5176025015 ps
T236 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.3733304534 Oct 15 03:16:43 AM UTC 24 Oct 15 03:18:25 AM UTC 24 593390080 ps
T237 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.339707787 Oct 15 03:18:17 AM UTC 24 Oct 15 03:18:31 AM UTC 24 138787036 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3220071000 Oct 15 03:13:29 AM UTC 24 Oct 15 03:18:39 AM UTC 24 6379526330 ps
T238 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.3361510316 Oct 15 03:16:40 AM UTC 24 Oct 15 03:18:41 AM UTC 24 869516577 ps
T239 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.3713091424 Oct 15 03:18:32 AM UTC 24 Oct 15 03:18:46 AM UTC 24 2286607023 ps
T240 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.4066709932 Oct 15 03:18:40 AM UTC 24 Oct 15 03:18:47 AM UTC 24 166674675 ps
T241 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.2638376555 Oct 15 03:18:43 AM UTC 24 Oct 15 03:18:49 AM UTC 24 205817195 ps
T242 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.1230356303 Oct 15 03:18:47 AM UTC 24 Oct 15 03:18:53 AM UTC 24 677510426 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_regwen.22092432 Oct 15 03:03:46 AM UTC 24 Oct 15 03:18:54 AM UTC 24 187221453869 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_executable.2472826873 Oct 15 03:10:49 AM UTC 24 Oct 15 03:18:56 AM UTC 24 9516924060 ps
T243 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.3847118419 Oct 15 03:18:55 AM UTC 24 Oct 15 03:18:57 AM UTC 24 31125832 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.3350383780 Oct 15 03:18:58 AM UTC 24 Oct 15 03:19:03 AM UTC 24 908900266 ps
T244 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_readback_err.1055668655 Oct 15 03:19:03 AM UTC 24 Oct 15 03:19:06 AM UTC 24 123351681 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.1112452729 Oct 15 03:18:57 AM UTC 24 Oct 15 03:19:13 AM UTC 24 599121891 ps
T245 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.401271929 Oct 15 03:19:14 AM UTC 24 Oct 15 03:19:16 AM UTC 24 17172576 ps
T246 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.786968638 Oct 15 03:03:45 AM UTC 24 Oct 15 03:19:33 AM UTC 24 16464819909 ps
T247 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.2753029962 Oct 15 03:18:23 AM UTC 24 Oct 15 03:19:44 AM UTC 24 3022267996 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.10400518 Oct 15 03:19:04 AM UTC 24 Oct 15 03:19:50 AM UTC 24 9745589458 ps
T248 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.1350855831 Oct 15 03:06:21 AM UTC 24 Oct 15 03:20:00 AM UTC 24 6914090026 ps
T249 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.3658375329 Oct 15 03:14:45 AM UTC 24 Oct 15 03:20:07 AM UTC 24 4452913065 ps
T250 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.1144628698 Oct 15 03:19:17 AM UTC 24 Oct 15 03:20:16 AM UTC 24 505882991 ps
T251 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.830829943 Oct 15 03:19:45 AM UTC 24 Oct 15 03:20:20 AM UTC 24 2314824151 ps
T252 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.4191806439 Oct 15 03:20:17 AM UTC 24 Oct 15 03:20:24 AM UTC 24 218375281 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.2484489208 Oct 15 03:20:21 AM UTC 24 Oct 15 03:20:37 AM UTC 24 931543938 ps
T253 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3676900439 Oct 15 03:20:54 AM UTC 24 Oct 15 03:20:56 AM UTC 24 125694615 ps
T254 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.4197791728 Oct 15 03:20:09 AM UTC 24 Oct 15 03:21:03 AM UTC 24 158937073 ps
T255 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.1816660703 Oct 15 03:20:57 AM UTC 24 Oct 15 03:21:04 AM UTC 24 74318861 ps
T256 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_readback_err.4002866844 Oct 15 03:21:05 AM UTC 24 Oct 15 03:21:07 AM UTC 24 34164339 ps
T257 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.449150212 Oct 15 03:21:04 AM UTC 24 Oct 15 03:21:08 AM UTC 24 131825508 ps
T258 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.983039358 Oct 15 03:19:56 AM UTC 24 Oct 15 03:21:21 AM UTC 24 852027936 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.2194902139 Oct 15 03:21:22 AM UTC 24 Oct 15 03:21:24 AM UTC 24 45351911 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1676035560 Oct 15 03:21:08 AM UTC 24 Oct 15 03:21:26 AM UTC 24 855801605 ps
T260 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.2221486980 Oct 15 03:16:15 AM UTC 24 Oct 15 03:21:52 AM UTC 24 2933538577 ps
T261 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.3197694064 Oct 15 03:12:45 AM UTC 24 Oct 15 03:22:22 AM UTC 24 11781614247 ps
T262 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.3169053434 Oct 15 03:14:26 AM UTC 24 Oct 15 03:22:23 AM UTC 24 22262474614 ps
T263 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_smoke.2239334286 Oct 15 03:21:25 AM UTC 24 Oct 15 03:22:23 AM UTC 24 1794615481 ps
T179 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.1342599948 Oct 15 03:17:01 AM UTC 24 Oct 15 03:22:25 AM UTC 24 15293136922 ps
T184 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_executable.3577221384 Oct 15 03:12:47 AM UTC 24 Oct 15 03:22:30 AM UTC 24 30104470059 ps
T264 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_smoke.22965151 Oct 15 03:28:03 AM UTC 24 Oct 15 03:28:31 AM UTC 24 1051332304 ps
T265 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access.1458043165 Oct 15 03:22:24 AM UTC 24 Oct 15 03:22:35 AM UTC 24 152632340 ps
T266 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.2080546283 Oct 15 03:22:32 AM UTC 24 Oct 15 03:22:39 AM UTC 24 259216375 ps
T267 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_bijection.4045373128 Oct 15 03:21:53 AM UTC 24 Oct 15 03:22:44 AM UTC 24 4113441316 ps
T268 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.3026913566 Oct 15 03:22:54 AM UTC 24 Oct 15 03:22:56 AM UTC 24 27930825 ps
T269 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.4069919167 Oct 15 03:19:34 AM UTC 24 Oct 15 03:23:01 AM UTC 24 2074835012 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.2521660613 Oct 15 03:23:02 AM UTC 24 Oct 15 03:23:07 AM UTC 24 98332348 ps
T270 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.1281301475 Oct 15 03:22:57 AM UTC 24 Oct 15 03:23:09 AM UTC 24 176269710 ps
T271 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_readback_err.4063967848 Oct 15 03:23:08 AM UTC 24 Oct 15 03:23:11 AM UTC 24 38253591 ps
T272 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_alert_test.3095763933 Oct 15 03:23:14 AM UTC 24 Oct 15 03:23:15 AM UTC 24 55969509 ps
T273 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_smoke.1948574238 Oct 15 03:23:17 AM UTC 24 Oct 15 03:23:29 AM UTC 24 387541663 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.4275262076 Oct 15 03:15:51 AM UTC 24 Oct 15 03:23:47 AM UTC 24 4259446359 ps
T274 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.2973067887 Oct 15 03:22:31 AM UTC 24 Oct 15 03:23:58 AM UTC 24 157358457 ps
T185 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_executable.940615819 Oct 15 03:05:33 AM UTC 24 Oct 15 03:24:07 AM UTC 24 13923934946 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.1885936530 Oct 15 03:22:26 AM UTC 24 Oct 15 03:24:10 AM UTC 24 142072446 ps
T276 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.3184780946 Oct 15 03:09:23 AM UTC 24 Oct 15 03:24:11 AM UTC 24 117430624521 ps
T277 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.3089847042 Oct 15 03:10:16 AM UTC 24 Oct 15 03:24:18 AM UTC 24 3065551067 ps
T143 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all.2285709924 Oct 15 03:11:14 AM UTC 24 Oct 15 03:24:23 AM UTC 24 19975614770 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.4143152670 Oct 15 03:24:20 AM UTC 24 Oct 15 03:24:31 AM UTC 24 1166088383 ps
T151 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_bijection.108925790 Oct 15 03:23:30 AM UTC 24 Oct 15 03:24:33 AM UTC 24 1155534585 ps
T152 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.3062981550 Oct 15 03:19:51 AM UTC 24 Oct 15 03:24:42 AM UTC 24 3114216118 ps
T153 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.3258355728 Oct 15 03:24:43 AM UTC 24 Oct 15 03:24:44 AM UTC 24 130446717 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.1261221682 Oct 15 03:24:45 AM UTC 24 Oct 15 03:24:50 AM UTC 24 108458431 ps
T154 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_readback_err.180930490 Oct 15 03:24:51 AM UTC 24 Oct 15 03:24:53 AM UTC 24 81785472 ps
T155 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access.560214701 Oct 15 03:23:59 AM UTC 24 Oct 15 03:24:56 AM UTC 24 656631117 ps
T156 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.2522270858 Oct 15 03:24:44 AM UTC 24 Oct 15 03:24:56 AM UTC 24 543239480 ps
T157 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_alert_test.2279091127 Oct 15 03:24:57 AM UTC 24 Oct 15 03:24:59 AM UTC 24 49600541 ps
T278 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_smoke.3355479619 Oct 15 03:25:00 AM UTC 24 Oct 15 03:25:04 AM UTC 24 541826654 ps
T279 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.1204269913 Oct 15 03:20:01 AM UTC 24 Oct 15 03:25:10 AM UTC 24 31104445250 ps
T280 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.1152183630 Oct 15 03:24:13 AM UTC 24 Oct 15 03:25:32 AM UTC 24 169433292 ps
T281 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_bijection.798750392 Oct 15 03:25:11 AM UTC 24 Oct 15 03:25:41 AM UTC 24 910498184 ps
T282 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.3134317318 Oct 15 03:22:23 AM UTC 24 Oct 15 03:25:49 AM UTC 24 6389829083 ps
T283 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access.1452824584 Oct 15 03:25:42 AM UTC 24 Oct 15 03:25:51 AM UTC 24 338082183 ps
T284 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.619525618 Oct 15 03:16:36 AM UTC 24 Oct 15 03:25:54 AM UTC 24 165036685793 ps
T285 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.4195761154 Oct 15 03:25:55 AM UTC 24 Oct 15 03:25:58 AM UTC 24 153689143 ps
T286 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.846689802 Oct 15 03:24:11 AM UTC 24 Oct 15 03:25:59 AM UTC 24 191191609 ps
T178 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_executable.774778799 Oct 15 03:15:03 AM UTC 24 Oct 15 03:26:00 AM UTC 24 5357029260 ps
T287 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.4073476518 Oct 15 03:25:58 AM UTC 24 Oct 15 03:26:06 AM UTC 24 1568995607 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.4227544253 Oct 15 03:17:40 AM UTC 24 Oct 15 03:26:13 AM UTC 24 17925807973 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.3337539392 Oct 15 03:26:14 AM UTC 24 Oct 15 03:26:16 AM UTC 24 121228569 ps
T289 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.1980138559 Oct 15 03:18:25 AM UTC 24 Oct 15 03:26:16 AM UTC 24 15402447397 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.2835088938 Oct 15 03:15:02 AM UTC 24 Oct 15 03:26:17 AM UTC 24 2872464386 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_readback_err.1571343983 Oct 15 03:26:18 AM UTC 24 Oct 15 03:26:20 AM UTC 24 111626064 ps
T292 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.2636856215 Oct 15 03:26:17 AM UTC 24 Oct 15 03:26:25 AM UTC 24 155789945 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.3053697656 Oct 15 03:26:17 AM UTC 24 Oct 15 03:26:28 AM UTC 24 146382912 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_alert_test.1126695500 Oct 15 03:26:28 AM UTC 24 Oct 15 03:26:30 AM UTC 24 17470761 ps
T183 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.1533501618 Oct 15 03:18:50 AM UTC 24 Oct 15 03:26:46 AM UTC 24 4329447769 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.3027861355 Oct 15 03:25:52 AM UTC 24 Oct 15 03:26:52 AM UTC 24 484324390 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2153214469 Oct 15 03:18:11 AM UTC 24 Oct 15 03:27:13 AM UTC 24 1488941334 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access.147368639 Oct 15 03:27:14 AM UTC 24 Oct 15 03:27:20 AM UTC 24 144558499 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all.1982833722 Oct 15 03:03:48 AM UTC 24 Oct 15 03:27:20 AM UTC 24 48963493303 ps
T297 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.992075168 Oct 15 03:27:38 AM UTC 24 Oct 15 03:27:41 AM UTC 24 127230628 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.3451837841 Oct 15 03:22:35 AM UTC 24 Oct 15 03:27:42 AM UTC 24 1311120555 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_bijection.4157755256 Oct 15 03:26:47 AM UTC 24 Oct 15 03:27:45 AM UTC 24 698334575 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.855773777 Oct 15 03:18:37 AM UTC 24 Oct 15 03:27:46 AM UTC 24 190520247026 ps
T301 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.3718526514 Oct 15 03:27:38 AM UTC 24 Oct 15 03:27:46 AM UTC 24 64565129 ps
T302 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.490331529 Oct 15 03:27:47 AM UTC 24 Oct 15 03:27:49 AM UTC 24 69386203 ps
T303 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.3363497917 Oct 15 03:27:47 AM UTC 24 Oct 15 03:27:55 AM UTC 24 1248134010 ps
T304 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_readback_err.3644852932 Oct 15 03:27:56 AM UTC 24 Oct 15 03:27:58 AM UTC 24 32701349 ps
T305 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.1280670951 Oct 15 03:27:50 AM UTC 24 Oct 15 03:27:59 AM UTC 24 172045735 ps
T306 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.3043807919 Oct 15 03:16:14 AM UTC 24 Oct 15 03:28:00 AM UTC 24 20642397890 ps
T307 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_alert_test.2230340428 Oct 15 03:28:00 AM UTC 24 Oct 15 03:28:02 AM UTC 24 31657470 ps
T308 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_smoke.2461119106 Oct 15 03:26:32 AM UTC 24 Oct 15 03:28:21 AM UTC 24 1054045791 ps
T309 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.1662907034 Oct 15 03:27:20 AM UTC 24 Oct 15 03:28:23 AM UTC 24 117036464 ps
T310 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.1988946421 Oct 15 03:24:24 AM UTC 24 Oct 15 03:28:27 AM UTC 24 6548372532 ps
T311 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.2630022194 Oct 15 03:26:00 AM UTC 24 Oct 15 03:28:38 AM UTC 24 900851693 ps
T312 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access.3849557669 Oct 15 03:28:32 AM UTC 24 Oct 15 03:28:42 AM UTC 24 665340035 ps
T313 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.3627660463 Oct 15 03:28:42 AM UTC 24 Oct 15 03:28:45 AM UTC 24 42469597 ps
T314 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.3893508198 Oct 15 03:23:48 AM UTC 24 Oct 15 03:28:49 AM UTC 24 2594507286 ps
T315 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_bijection.4250944016 Oct 15 03:28:24 AM UTC 24 Oct 15 03:28:50 AM UTC 24 5945588806 ps
T316 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.540767012 Oct 15 03:28:49 AM UTC 24 Oct 15 03:28:59 AM UTC 24 506407035 ps
T317 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_regwen.1023367290 Oct 15 03:11:01 AM UTC 24 Oct 15 03:29:06 AM UTC 24 12566693968 ps
T318 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_regwen.1252998239 Oct 15 03:08:15 AM UTC 24 Oct 15 03:29:22 AM UTC 24 13431817831 ps
T319 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.3323757877 Oct 15 03:29:23 AM UTC 24 Oct 15 03:29:25 AM UTC 24 44662895 ps
T320 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.2594675206 Oct 15 03:29:26 AM UTC 24 Oct 15 03:29:36 AM UTC 24 464098001 ps
T321 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.2688421355 Oct 15 03:29:36 AM UTC 24 Oct 15 03:29:46 AM UTC 24 209324040 ps
T144 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_regwen.264395514 Oct 15 03:15:15 AM UTC 24 Oct 15 03:29:47 AM UTC 24 28575388852 ps
T322 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.790688695 Oct 15 03:28:45 AM UTC 24 Oct 15 03:29:49 AM UTC 24 472007286 ps
T323 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_readback_err.700173437 Oct 15 03:29:47 AM UTC 24 Oct 15 03:29:49 AM UTC 24 76149417 ps
T324 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_alert_test.2661814097 Oct 15 03:29:50 AM UTC 24 Oct 15 03:29:52 AM UTC 24 33880314 ps
T325 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.1736711730 Oct 15 03:25:33 AM UTC 24 Oct 15 03:29:54 AM UTC 24 7222642566 ps
T326 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_smoke.2926198576 Oct 15 03:29:53 AM UTC 24 Oct 15 03:29:59 AM UTC 24 299360998 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1655193679 Oct 15 03:29:48 AM UTC 24 Oct 15 03:30:12 AM UTC 24 185031038 ps
T186 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_executable.2235421763 Oct 15 03:08:07 AM UTC 24 Oct 15 03:30:29 AM UTC 24 181502750292 ps
T327 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.794706659 Oct 15 03:28:52 AM UTC 24 Oct 15 03:30:35 AM UTC 24 2026421712 ps
T328 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.1137184642 Oct 15 03:26:53 AM UTC 24 Oct 15 03:30:35 AM UTC 24 1714676829 ps
T329 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.151932399 Oct 15 03:24:07 AM UTC 24 Oct 15 03:30:40 AM UTC 24 36260564108 ps
T330 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access.4065942099 Oct 15 03:30:31 AM UTC 24 Oct 15 03:30:40 AM UTC 24 1093428472 ps
T145 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all.19719446 Oct 15 03:06:12 AM UTC 24 Oct 15 03:30:44 AM UTC 24 32816314999 ps
T331 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.1072238962 Oct 15 03:30:41 AM UTC 24 Oct 15 03:30:48 AM UTC 24 83609689 ps
T332 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.2425117522 Oct 15 03:13:43 AM UTC 24 Oct 15 03:30:49 AM UTC 24 22122242147 ps
T333 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.1819360695 Oct 15 03:30:41 AM UTC 24 Oct 15 03:30:51 AM UTC 24 6255876455 ps
T334 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.3931642698 Oct 15 03:30:52 AM UTC 24 Oct 15 03:30:54 AM UTC 24 28347792 ps
T335 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.1664707858 Oct 15 03:16:58 AM UTC 24 Oct 15 03:30:55 AM UTC 24 2677487910 ps
T336 /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.4212470622 Oct 15 03:18:21 AM UTC 24 Oct 15 03:31:01 AM UTC 24 10462686519 ps