Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
845 |
1 |
|
|
T36 |
13 |
|
T63 |
8 |
|
T50 |
6 |
| auto[1] |
810 |
1 |
|
|
T36 |
7 |
|
T63 |
12 |
|
T50 |
9 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
824 |
1 |
|
|
T36 |
10 |
|
T63 |
11 |
|
T50 |
8 |
| auto[1] |
831 |
1 |
|
|
T36 |
10 |
|
T63 |
9 |
|
T50 |
7 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
827 |
1 |
|
|
T36 |
12 |
|
T63 |
11 |
|
T50 |
11 |
| auto[1] |
828 |
1 |
|
|
T36 |
8 |
|
T63 |
9 |
|
T50 |
4 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
817 |
1 |
|
|
T36 |
8 |
|
T63 |
9 |
|
T50 |
7 |
| auto[1] |
838 |
1 |
|
|
T36 |
12 |
|
T63 |
11 |
|
T50 |
8 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
833 |
1 |
|
|
T36 |
10 |
|
T63 |
10 |
|
T50 |
7 |
| auto[1] |
822 |
1 |
|
|
T36 |
10 |
|
T63 |
10 |
|
T50 |
8 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
860 |
1 |
|
|
T36 |
13 |
|
T63 |
12 |
|
T50 |
6 |
| auto[1] |
795 |
1 |
|
|
T36 |
7 |
|
T63 |
8 |
|
T50 |
9 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
771 |
1 |
|
|
T36 |
9 |
|
T63 |
12 |
|
T50 |
7 |
| auto[1] |
884 |
1 |
|
|
T36 |
11 |
|
T63 |
8 |
|
T50 |
8 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
829 |
1 |
|
|
T36 |
10 |
|
T63 |
6 |
|
T50 |
8 |
| auto[1] |
826 |
1 |
|
|
T36 |
10 |
|
T63 |
14 |
|
T50 |
7 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
804 |
1 |
|
|
T36 |
9 |
|
T63 |
11 |
|
T50 |
9 |
| auto[1] |
851 |
1 |
|
|
T36 |
11 |
|
T63 |
9 |
|
T50 |
6 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
816 |
1 |
|
|
T36 |
10 |
|
T63 |
12 |
|
T50 |
8 |
| auto[1] |
839 |
1 |
|
|
T36 |
10 |
|
T63 |
8 |
|
T50 |
7 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
823 |
1 |
|
|
T36 |
10 |
|
T63 |
6 |
|
T50 |
7 |
| auto[1] |
832 |
1 |
|
|
T36 |
10 |
|
T63 |
14 |
|
T50 |
8 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
816 |
1 |
|
|
T36 |
5 |
|
T63 |
8 |
|
T50 |
7 |
| auto[1] |
839 |
1 |
|
|
T36 |
15 |
|
T63 |
12 |
|
T50 |
8 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
848 |
1 |
|
|
T36 |
10 |
|
T63 |
10 |
|
T50 |
9 |
| auto[1] |
807 |
1 |
|
|
T36 |
10 |
|
T63 |
10 |
|
T50 |
6 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
824 |
1 |
|
|
T36 |
10 |
|
T63 |
11 |
|
T50 |
8 |
| auto[1] |
831 |
1 |
|
|
T36 |
10 |
|
T63 |
9 |
|
T50 |
7 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
872 |
1 |
|
|
T36 |
15 |
|
T63 |
9 |
|
T50 |
9 |
| auto[1] |
783 |
1 |
|
|
T36 |
5 |
|
T63 |
11 |
|
T50 |
6 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
854 |
1 |
|
|
T36 |
9 |
|
T63 |
9 |
|
T50 |
9 |
| auto[1] |
801 |
1 |
|
|
T36 |
11 |
|
T63 |
11 |
|
T50 |
6 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
853 |
1 |
|
|
T36 |
8 |
|
T63 |
12 |
|
T50 |
10 |
| auto[1] |
802 |
1 |
|
|
T36 |
12 |
|
T63 |
8 |
|
T50 |
5 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
822 |
1 |
|
|
T36 |
11 |
|
T63 |
12 |
|
T50 |
9 |
| auto[1] |
833 |
1 |
|
|
T36 |
9 |
|
T63 |
8 |
|
T50 |
6 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
818 |
1 |
|
|
T36 |
9 |
|
T63 |
12 |
|
T50 |
9 |
| auto[1] |
837 |
1 |
|
|
T36 |
11 |
|
T63 |
8 |
|
T50 |
6 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
842 |
1 |
|
|
T36 |
8 |
|
T63 |
10 |
|
T50 |
8 |
| auto[1] |
813 |
1 |
|
|
T36 |
12 |
|
T63 |
10 |
|
T50 |
7 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
813 |
1 |
|
|
T36 |
10 |
|
T63 |
12 |
|
T50 |
6 |
| auto[1] |
842 |
1 |
|
|
T36 |
10 |
|
T63 |
8 |
|
T50 |
9 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
849 |
1 |
|
|
T36 |
8 |
|
T63 |
10 |
|
T50 |
9 |
| auto[1] |
806 |
1 |
|
|
T36 |
12 |
|
T63 |
10 |
|
T50 |
6 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
814 |
1 |
|
|
T36 |
10 |
|
T63 |
8 |
|
T50 |
10 |
| auto[1] |
841 |
1 |
|
|
T36 |
10 |
|
T63 |
12 |
|
T50 |
5 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
816 |
1 |
|
|
T36 |
5 |
|
T63 |
8 |
|
T50 |
7 |
| auto[1] |
839 |
1 |
|
|
T36 |
15 |
|
T63 |
12 |
|
T50 |
8 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
439 |
1 |
|
|
T36 |
9 |
|
T63 |
4 |
|
T50 |
6 |
| auto[0] |
auto[1] |
433 |
1 |
|
|
T36 |
6 |
|
T63 |
5 |
|
T50 |
3 |
| auto[1] |
auto[0] |
388 |
1 |
|
|
T36 |
3 |
|
T63 |
7 |
|
T50 |
5 |
| auto[1] |
auto[1] |
395 |
1 |
|
|
T36 |
2 |
|
T63 |
4 |
|
T50 |
1 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
425 |
1 |
|
|
T36 |
4 |
|
T63 |
3 |
|
T50 |
4 |
| auto[0] |
auto[1] |
429 |
1 |
|
|
T36 |
5 |
|
T63 |
6 |
|
T50 |
5 |
| auto[1] |
auto[0] |
392 |
1 |
|
|
T36 |
4 |
|
T63 |
6 |
|
T50 |
3 |
| auto[1] |
auto[1] |
409 |
1 |
|
|
T36 |
7 |
|
T63 |
5 |
|
T50 |
3 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
419 |
1 |
|
|
T36 |
5 |
|
T63 |
6 |
|
T50 |
3 |
| auto[0] |
auto[1] |
434 |
1 |
|
|
T36 |
3 |
|
T63 |
6 |
|
T50 |
7 |
| auto[1] |
auto[0] |
414 |
1 |
|
|
T36 |
5 |
|
T63 |
4 |
|
T50 |
4 |
| auto[1] |
auto[1] |
388 |
1 |
|
|
T36 |
7 |
|
T63 |
4 |
|
T50 |
1 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
417 |
1 |
|
|
T36 |
8 |
|
T63 |
7 |
|
T50 |
2 |
| auto[0] |
auto[1] |
405 |
1 |
|
|
T36 |
3 |
|
T63 |
5 |
|
T50 |
7 |
| auto[1] |
auto[0] |
443 |
1 |
|
|
T36 |
5 |
|
T63 |
5 |
|
T50 |
4 |
| auto[1] |
auto[1] |
390 |
1 |
|
|
T36 |
4 |
|
T63 |
3 |
|
T50 |
2 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
389 |
1 |
|
|
T36 |
4 |
|
T63 |
6 |
|
T50 |
3 |
| auto[0] |
auto[1] |
429 |
1 |
|
|
T36 |
5 |
|
T63 |
6 |
|
T50 |
6 |
| auto[1] |
auto[0] |
382 |
1 |
|
|
T36 |
5 |
|
T63 |
6 |
|
T50 |
4 |
| auto[1] |
auto[1] |
455 |
1 |
|
|
T36 |
6 |
|
T63 |
2 |
|
T50 |
2 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
430 |
1 |
|
|
T36 |
4 |
|
T63 |
2 |
|
T50 |
3 |
| auto[0] |
auto[1] |
412 |
1 |
|
|
T36 |
4 |
|
T63 |
8 |
|
T50 |
5 |
| auto[1] |
auto[0] |
399 |
1 |
|
|
T36 |
6 |
|
T63 |
4 |
|
T50 |
5 |
| auto[1] |
auto[1] |
414 |
1 |
|
|
T36 |
6 |
|
T63 |
6 |
|
T50 |
2 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
412 |
1 |
|
|
T36 |
3 |
|
T63 |
7 |
|
T50 |
5 |
| auto[0] |
auto[1] |
437 |
1 |
|
|
T36 |
5 |
|
T63 |
3 |
|
T50 |
4 |
| auto[1] |
auto[0] |
404 |
1 |
|
|
T36 |
7 |
|
T63 |
5 |
|
T50 |
3 |
| auto[1] |
auto[1] |
402 |
1 |
|
|
T36 |
5 |
|
T63 |
5 |
|
T50 |
3 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
398 |
1 |
|
|
T36 |
4 |
|
T63 |
3 |
|
T50 |
5 |
| auto[0] |
auto[1] |
416 |
1 |
|
|
T36 |
6 |
|
T63 |
5 |
|
T50 |
5 |
| auto[1] |
auto[0] |
425 |
1 |
|
|
T36 |
6 |
|
T63 |
3 |
|
T50 |
2 |
| auto[1] |
auto[1] |
416 |
1 |
|
|
T36 |
4 |
|
T63 |
9 |
|
T50 |
3 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
434 |
1 |
|
|
T36 |
7 |
|
T63 |
3 |
|
T50 |
2 |
| auto[0] |
auto[1] |
414 |
1 |
|
|
T36 |
3 |
|
T63 |
7 |
|
T50 |
7 |
| auto[1] |
auto[0] |
411 |
1 |
|
|
T36 |
6 |
|
T63 |
5 |
|
T50 |
4 |
| auto[1] |
auto[1] |
396 |
1 |
|
|
T36 |
4 |
|
T63 |
5 |
|
T50 |
2 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
824 |
1 |
|
|
T36 |
10 |
|
T63 |
11 |
|
T50 |
8 |
| auto[1] |
auto[1] |
831 |
1 |
|
|
T36 |
10 |
|
T63 |
9 |
|
T50 |
7 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
393 |
1 |
|
|
T36 |
4 |
|
T63 |
6 |
|
T50 |
3 |
| auto[0] |
auto[1] |
420 |
1 |
|
|
T36 |
6 |
|
T63 |
6 |
|
T50 |
3 |
| auto[1] |
auto[0] |
411 |
1 |
|
|
T36 |
5 |
|
T63 |
5 |
|
T50 |
6 |
| auto[1] |
auto[1] |
431 |
1 |
|
|
T36 |
5 |
|
T63 |
3 |
|
T50 |
3 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
816 |
1 |
|
|
T36 |
5 |
|
T63 |
8 |
|
T50 |
7 |
| auto[1] |
auto[1] |
839 |
1 |
|
|
T36 |
15 |
|
T63 |
12 |
|
T50 |
8 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
128 |
1 |
|
|
T78 |
11 |
|
T144 |
3 |
|
T207 |
6 |
| auto[1] |
121 |
1 |
|
|
T78 |
9 |
|
T144 |
6 |
|
T207 |
14 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
131 |
1 |
|
|
T78 |
10 |
|
T144 |
7 |
|
T207 |
10 |
| auto[1] |
118 |
1 |
|
|
T78 |
10 |
|
T144 |
2 |
|
T207 |
10 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
121 |
1 |
|
|
T78 |
8 |
|
T144 |
3 |
|
T207 |
8 |
| auto[1] |
128 |
1 |
|
|
T78 |
12 |
|
T144 |
6 |
|
T207 |
12 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
135 |
1 |
|
|
T78 |
10 |
|
T144 |
1 |
|
T207 |
11 |
| auto[1] |
114 |
1 |
|
|
T78 |
10 |
|
T144 |
8 |
|
T207 |
9 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
127 |
1 |
|
|
T78 |
9 |
|
T144 |
4 |
|
T207 |
9 |
| auto[1] |
122 |
1 |
|
|
T78 |
11 |
|
T144 |
5 |
|
T207 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
127 |
1 |
|
|
T78 |
8 |
|
T144 |
4 |
|
T207 |
12 |
| auto[1] |
122 |
1 |
|
|
T78 |
12 |
|
T144 |
5 |
|
T207 |
8 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
124 |
1 |
|
|
T78 |
9 |
|
T144 |
4 |
|
T207 |
8 |
| auto[1] |
125 |
1 |
|
|
T78 |
11 |
|
T144 |
5 |
|
T207 |
12 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
134 |
1 |
|
|
T78 |
11 |
|
T144 |
2 |
|
T207 |
13 |
| auto[1] |
115 |
1 |
|
|
T78 |
9 |
|
T144 |
7 |
|
T207 |
7 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
118 |
1 |
|
|
T78 |
7 |
|
T144 |
4 |
|
T207 |
10 |
| auto[1] |
131 |
1 |
|
|
T78 |
13 |
|
T144 |
5 |
|
T207 |
10 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
129 |
1 |
|
|
T78 |
10 |
|
T144 |
6 |
|
T207 |
11 |
| auto[1] |
120 |
1 |
|
|
T78 |
10 |
|
T144 |
3 |
|
T207 |
9 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126 |
1 |
|
|
T78 |
13 |
|
T144 |
7 |
|
T207 |
8 |
| auto[1] |
123 |
1 |
|
|
T78 |
7 |
|
T144 |
2 |
|
T207 |
12 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
120 |
1 |
|
|
T78 |
10 |
|
T144 |
6 |
|
T207 |
8 |
| auto[1] |
129 |
1 |
|
|
T78 |
10 |
|
T144 |
3 |
|
T207 |
12 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
124 |
1 |
|
|
T78 |
10 |
|
T144 |
6 |
|
T207 |
9 |
| auto[1] |
125 |
1 |
|
|
T78 |
10 |
|
T144 |
3 |
|
T207 |
11 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
131 |
1 |
|
|
T78 |
10 |
|
T144 |
7 |
|
T207 |
10 |
| auto[1] |
118 |
1 |
|
|
T78 |
10 |
|
T144 |
2 |
|
T207 |
10 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126 |
1 |
|
|
T78 |
7 |
|
T144 |
9 |
|
T207 |
11 |
| auto[1] |
123 |
1 |
|
|
T78 |
13 |
|
T207 |
9 |
|
T343 |
5 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
120 |
1 |
|
|
T78 |
11 |
|
T144 |
7 |
|
T207 |
10 |
| auto[1] |
129 |
1 |
|
|
T78 |
9 |
|
T144 |
2 |
|
T207 |
10 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
133 |
1 |
|
|
T78 |
10 |
|
T144 |
7 |
|
T207 |
9 |
| auto[1] |
116 |
1 |
|
|
T78 |
10 |
|
T144 |
2 |
|
T207 |
11 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
131 |
1 |
|
|
T78 |
15 |
|
T144 |
7 |
|
T207 |
10 |
| auto[1] |
118 |
1 |
|
|
T78 |
5 |
|
T144 |
2 |
|
T207 |
10 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
132 |
1 |
|
|
T78 |
13 |
|
T144 |
6 |
|
T207 |
11 |
| auto[1] |
117 |
1 |
|
|
T78 |
7 |
|
T144 |
3 |
|
T207 |
9 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
116 |
1 |
|
|
T78 |
7 |
|
T144 |
8 |
|
T207 |
10 |
| auto[1] |
133 |
1 |
|
|
T78 |
13 |
|
T144 |
1 |
|
T207 |
10 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
113 |
1 |
|
|
T78 |
7 |
|
T144 |
5 |
|
T207 |
7 |
| auto[1] |
136 |
1 |
|
|
T78 |
13 |
|
T144 |
4 |
|
T207 |
13 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
129 |
1 |
|
|
T78 |
13 |
|
T144 |
7 |
|
T207 |
12 |
| auto[1] |
120 |
1 |
|
|
T78 |
7 |
|
T144 |
2 |
|
T207 |
8 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
134 |
1 |
|
|
T78 |
10 |
|
T144 |
8 |
|
T207 |
9 |
| auto[1] |
115 |
1 |
|
|
T78 |
10 |
|
T144 |
1 |
|
T207 |
11 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
120 |
1 |
|
|
T78 |
10 |
|
T144 |
6 |
|
T207 |
8 |
| auto[1] |
129 |
1 |
|
|
T78 |
10 |
|
T144 |
3 |
|
T207 |
12 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
65 |
1 |
|
|
T78 |
4 |
|
T144 |
3 |
|
T207 |
6 |
| auto[0] |
auto[1] |
61 |
1 |
|
|
T78 |
3 |
|
T144 |
6 |
|
T207 |
5 |
| auto[1] |
auto[0] |
56 |
1 |
|
|
T78 |
4 |
|
T207 |
2 |
|
T343 |
4 |
| auto[1] |
auto[1] |
67 |
1 |
|
|
T78 |
9 |
|
T207 |
7 |
|
T343 |
1 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
69 |
1 |
|
|
T78 |
7 |
|
T144 |
1 |
|
T207 |
7 |
| auto[0] |
auto[1] |
51 |
1 |
|
|
T78 |
4 |
|
T144 |
6 |
|
T207 |
3 |
| auto[1] |
auto[0] |
66 |
1 |
|
|
T78 |
3 |
|
T207 |
4 |
|
T343 |
4 |
| auto[1] |
auto[1] |
63 |
1 |
|
|
T78 |
6 |
|
T144 |
2 |
|
T207 |
6 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
67 |
1 |
|
|
T78 |
4 |
|
T144 |
3 |
|
T207 |
2 |
| auto[0] |
auto[1] |
66 |
1 |
|
|
T78 |
6 |
|
T144 |
4 |
|
T207 |
7 |
| auto[1] |
auto[0] |
60 |
1 |
|
|
T78 |
5 |
|
T144 |
1 |
|
T207 |
7 |
| auto[1] |
auto[1] |
56 |
1 |
|
|
T78 |
5 |
|
T144 |
1 |
|
T207 |
4 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
66 |
1 |
|
|
T78 |
6 |
|
T144 |
3 |
|
T207 |
4 |
| auto[0] |
auto[1] |
65 |
1 |
|
|
T78 |
9 |
|
T144 |
4 |
|
T207 |
6 |
| auto[1] |
auto[0] |
61 |
1 |
|
|
T78 |
2 |
|
T144 |
1 |
|
T207 |
8 |
| auto[1] |
auto[1] |
57 |
1 |
|
|
T78 |
3 |
|
T144 |
1 |
|
T207 |
2 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
63 |
1 |
|
|
T78 |
5 |
|
T144 |
1 |
|
T207 |
5 |
| auto[0] |
auto[1] |
69 |
1 |
|
|
T78 |
8 |
|
T144 |
5 |
|
T207 |
6 |
| auto[1] |
auto[0] |
61 |
1 |
|
|
T78 |
4 |
|
T144 |
3 |
|
T207 |
3 |
| auto[1] |
auto[1] |
56 |
1 |
|
|
T78 |
3 |
|
T207 |
6 |
|
T343 |
7 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
60 |
1 |
|
|
T78 |
3 |
|
T144 |
1 |
|
T207 |
7 |
| auto[0] |
auto[1] |
56 |
1 |
|
|
T78 |
4 |
|
T144 |
7 |
|
T207 |
3 |
| auto[1] |
auto[0] |
74 |
1 |
|
|
T78 |
8 |
|
T144 |
1 |
|
T207 |
6 |
| auto[1] |
auto[1] |
59 |
1 |
|
|
T78 |
5 |
|
T207 |
4 |
|
T343 |
6 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
68 |
1 |
|
|
T78 |
7 |
|
T144 |
6 |
|
T207 |
7 |
| auto[0] |
auto[1] |
61 |
1 |
|
|
T78 |
6 |
|
T144 |
1 |
|
T207 |
5 |
| auto[1] |
auto[0] |
61 |
1 |
|
|
T78 |
3 |
|
T207 |
4 |
|
T343 |
8 |
| auto[1] |
auto[1] |
59 |
1 |
|
|
T78 |
4 |
|
T144 |
2 |
|
T207 |
4 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
69 |
1 |
|
|
T78 |
7 |
|
T144 |
7 |
|
T207 |
4 |
| auto[0] |
auto[1] |
65 |
1 |
|
|
T78 |
3 |
|
T144 |
1 |
|
T207 |
5 |
| auto[1] |
auto[0] |
57 |
1 |
|
|
T78 |
6 |
|
T207 |
4 |
|
T343 |
4 |
| auto[1] |
auto[1] |
58 |
1 |
|
|
T78 |
4 |
|
T144 |
1 |
|
T207 |
7 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
69 |
1 |
|
|
T78 |
5 |
|
T144 |
2 |
|
T207 |
2 |
| auto[0] |
auto[1] |
55 |
1 |
|
|
T78 |
5 |
|
T144 |
4 |
|
T207 |
7 |
| auto[1] |
auto[0] |
59 |
1 |
|
|
T78 |
6 |
|
T144 |
1 |
|
T207 |
4 |
| auto[1] |
auto[1] |
66 |
1 |
|
|
T78 |
4 |
|
T144 |
2 |
|
T207 |
7 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
131 |
1 |
|
|
T78 |
10 |
|
T144 |
7 |
|
T207 |
10 |
| auto[1] |
auto[1] |
118 |
1 |
|
|
T78 |
10 |
|
T144 |
2 |
|
T207 |
10 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
56 |
1 |
|
|
T78 |
2 |
|
T144 |
2 |
|
T207 |
5 |
| auto[0] |
auto[1] |
57 |
1 |
|
|
T78 |
5 |
|
T144 |
3 |
|
T207 |
2 |
| auto[1] |
auto[0] |
62 |
1 |
|
|
T78 |
5 |
|
T144 |
2 |
|
T207 |
5 |
| auto[1] |
auto[1] |
74 |
1 |
|
|
T78 |
8 |
|
T144 |
2 |
|
T207 |
8 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
120 |
1 |
|
|
T78 |
10 |
|
T144 |
6 |
|
T207 |
8 |
| auto[1] |
auto[1] |
129 |
1 |
|
|
T78 |
10 |
|
T144 |
3 |
|
T207 |
12 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
57 |
1 |
|
|
T78 |
9 |
|
T343 |
11 |
|
T126 |
9 |
| auto[1] |
63 |
1 |
|
|
T78 |
11 |
|
T343 |
9 |
|
T126 |
11 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
62 |
1 |
|
|
T78 |
11 |
|
T343 |
8 |
|
T126 |
12 |
| auto[1] |
58 |
1 |
|
|
T78 |
9 |
|
T343 |
12 |
|
T126 |
8 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
62 |
1 |
|
|
T78 |
9 |
|
T343 |
10 |
|
T126 |
11 |
| auto[1] |
58 |
1 |
|
|
T78 |
11 |
|
T343 |
10 |
|
T126 |
9 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
66 |
1 |
|
|
T78 |
13 |
|
T343 |
9 |
|
T126 |
10 |
| auto[1] |
54 |
1 |
|
|
T78 |
7 |
|
T343 |
11 |
|
T126 |
10 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
66 |
1 |
|
|
T78 |
12 |
|
T343 |
9 |
|
T126 |
8 |
| auto[1] |
54 |
1 |
|
|
T78 |
8 |
|
T343 |
11 |
|
T126 |
12 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
54 |
1 |
|
|
T78 |
10 |
|
T343 |
10 |
|
T126 |
5 |
| auto[1] |
66 |
1 |
|
|
T78 |
10 |
|
T343 |
10 |
|
T126 |
15 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
60 |
1 |
|
|
T78 |
10 |
|
T343 |
11 |
|
T126 |
11 |
| auto[1] |
60 |
1 |
|
|
T78 |
10 |
|
T343 |
9 |
|
T126 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
56 |
1 |
|
|
T78 |
9 |
|
T343 |
9 |
|
T126 |
11 |
| auto[1] |
64 |
1 |
|
|
T78 |
11 |
|
T343 |
11 |
|
T126 |
9 |