Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.75	99.31	96.35	100.00	96.15	98.68	99.44	94.29

Total tests in report: 916

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
61.05	61.05	71.64	71.64	63.46	63.46	56.61	56.61	96.15	96.15	76.09	76.09	57.40	57.40	5.97	5.97	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.3355122793
72.20	11.15	85.52	13.87	76.28	12.82	65.03	8.43	96.15	0.00	87.54	11.45	73.97	16.57	20.87	14.90	/workspace/coverage/default/41.sysrst_ctrl_stress_all.2694204565
79.44	7.24	86.56	1.04	79.31	3.03	95.44	30.41	96.15	0.00	87.57	0.03	74.72	0.75	36.29	15.42	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.773404224
85.53	6.09	93.02	6.46	85.65	6.34	95.90	0.46	96.15	0.00	92.73	5.15	89.14	14.42	46.11	9.81	/workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.3337396011
88.31	2.79	95.80	2.78	88.39	2.74	97.72	1.82	96.15	0.00	94.60	1.88	93.82	4.68	51.71	5.61	/workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.1467359850
90.36	2.05	95.80	0.00	88.39	0.00	97.72	0.00	96.15	0.00	94.60	0.00	93.82	0.00	66.04	14.33	/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.4262614747
91.59	1.22	96.68	0.89	89.34	0.95	98.18	0.46	96.15	0.00	95.51	0.90	96.07	2.25	69.16	3.12	/workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.2297203465
92.55	0.96	96.75	0.07	89.37	0.02	98.18	0.00	96.15	0.00	95.61	0.10	96.16	0.09	75.60	6.44	/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.450404438
93.24	0.69	97.03	0.28	93.28	3.91	98.18	0.00	96.15	0.00	96.17	0.56	96.25	0.09	75.60	0.00	/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.203493357
93.84	0.60	97.10	0.07	93.37	0.10	98.18	0.00	96.15	0.00	96.24	0.07	96.44	0.19	79.39	3.79	/workspace/coverage/default/3.sysrst_ctrl_combo_detect.2127460987
94.26	0.42	97.46	0.36	93.66	0.29	98.63	0.46	96.15	0.00	96.52	0.28	97.28	0.84	80.11	0.73	/workspace/coverage/default/40.sysrst_ctrl_stress_all.253699753
94.66	0.39	97.53	0.07	93.87	0.21	98.86	0.23	96.15	0.00	96.59	0.07	97.28	0.00	82.29	2.18	/workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.242552157
94.98	0.32	97.64	0.10	94.02	0.14	98.86	0.00	96.15	0.00	96.69	0.10	97.28	0.00	84.22	1.92	/workspace/coverage/default/0.sysrst_ctrl_combo_detect.2068417719
95.30	0.32	98.61	0.97	94.26	0.24	98.86	0.00	96.15	0.00	97.74	1.04	97.28	0.00	84.22	0.00	/workspace/coverage/default/1.sysrst_ctrl_feature_disable.1077542606
95.59	0.29	98.61	0.00	95.14	0.88	98.86	0.00	96.15	0.00	97.77	0.03	97.47	0.19	85.15	0.93	/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2773451044
95.82	0.22	98.63	0.02	95.16	0.02	99.32	0.46	96.15	0.00	97.81	0.03	97.47	0.00	86.19	1.04	/workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.3765379695
96.00	0.18	98.66	0.03	95.18	0.02	99.32	0.00	96.15	0.00	97.84	0.03	97.57	0.09	87.28	1.09	/workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.2140527935
96.18	0.18	98.70	0.03	95.28	0.10	99.32	0.00	96.15	0.00	97.84	0.00	97.57	0.00	88.42	1.14	/workspace/coverage/default/22.sysrst_ctrl_combo_detect.3555765180
96.31	0.13	98.70	0.00	95.30	0.02	100.00	0.68	96.15	0.00	97.84	0.00	97.66	0.09	88.53	0.10	/workspace/coverage/default/1.sysrst_ctrl_sec_cm.2735808336
96.43	0.12	98.73	0.03	95.33	0.02	100.00	0.00	96.15	0.00	97.88	0.03	97.75	0.09	89.20	0.67	/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.2016670700
96.54	0.11	98.84	0.10	95.42	0.10	100.00	0.00	96.15	0.00	97.98	0.10	98.03	0.28	89.36	0.16	/workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.848835485
96.64	0.10	98.84	0.00	95.42	0.00	100.00	0.00	96.15	0.00	97.98	0.00	98.03	0.00	90.08	0.73	/workspace/coverage/default/29.sysrst_ctrl_combo_detect.3017214754
96.72	0.08	98.84	0.00	95.42	0.00	100.00	0.00	96.15	0.00	97.98	0.00	98.60	0.56	90.08	0.00	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.4209348637
96.79	0.07	98.85	0.02	95.42	0.00	100.00	0.00	96.15	0.00	98.02	0.03	98.60	0.00	90.50	0.42	/workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.1272615703
96.86	0.06	98.87	0.02	95.47	0.05	100.00	0.00	96.15	0.00	98.05	0.03	98.69	0.09	90.76	0.26	/workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.846148712
96.92	0.06	98.87	0.00	95.47	0.00	100.00	0.00	96.15	0.00	98.05	0.00	98.69	0.00	91.17	0.42	/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.1703863545
96.97	0.05	98.87	0.00	95.85	0.38	100.00	0.00	96.15	0.00	98.05	0.00	98.69	0.00	91.17	0.00	/workspace/coverage/default/0.sysrst_ctrl_feature_disable.1419845473
97.02	0.05	98.94	0.07	95.90	0.05	100.00	0.00	96.15	0.00	98.12	0.07	98.88	0.19	91.17	0.00	/workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.3465653328
97.08	0.05	99.01	0.07	95.95	0.05	100.00	0.00	96.15	0.00	98.19	0.07	99.06	0.19	91.17	0.00	/workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.4282132590
97.12	0.04	99.01	0.00	95.95	0.00	100.00	0.00	96.15	0.00	98.19	0.00	99.06	0.00	91.48	0.31	/workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.1669043158
97.16	0.04	99.01	0.00	95.97	0.02	100.00	0.00	96.15	0.00	98.19	0.00	99.06	0.00	91.74	0.26	/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.4214158210
97.20	0.04	99.06	0.05	95.97	0.00	100.00	0.00	96.15	0.00	98.29	0.10	99.06	0.00	91.85	0.10	/workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.1173635084
97.24	0.04	99.06	0.00	95.97	0.00	100.00	0.00	96.15	0.00	98.29	0.00	99.06	0.00	92.11	0.26	/workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.3595134407
97.27	0.04	99.06	0.00	95.97	0.00	100.00	0.00	96.15	0.00	98.29	0.00	99.06	0.00	92.37	0.26	/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.3567222699
97.31	0.03	99.10	0.03	96.00	0.02	100.00	0.00	96.15	0.00	98.33	0.03	99.16	0.09	92.42	0.05	/workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.3424882519
97.34	0.03	99.10	0.00	96.00	0.00	100.00	0.00	96.15	0.00	98.33	0.00	99.16	0.00	92.63	0.21	/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.2802225142
97.36	0.03	99.13	0.03	96.02	0.02	100.00	0.00	96.15	0.00	98.36	0.03	99.25	0.09	92.63	0.00	/workspace/coverage/default/14.sysrst_ctrl_edge_detect.3808208316
97.39	0.03	99.17	0.03	96.04	0.02	100.00	0.00	96.15	0.00	98.40	0.03	99.34	0.09	92.63	0.00	/workspace/coverage/default/24.sysrst_ctrl_edge_detect.2137013040
97.42	0.03	99.20	0.03	96.07	0.02	100.00	0.00	96.15	0.00	98.43	0.03	99.44	0.09	92.63	0.00	/workspace/coverage/default/34.sysrst_ctrl_edge_detect.1942823505
97.44	0.02	99.20	0.00	96.07	0.00	100.00	0.00	96.15	0.00	98.43	0.00	99.44	0.00	92.78	0.16	/workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.3768476130
97.46	0.02	99.22	0.02	96.09	0.02	100.00	0.00	96.15	0.00	98.47	0.03	99.44	0.00	92.83	0.05	/workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.3059508339
97.48	0.02	99.22	0.00	96.11	0.02	100.00	0.00	96.15	0.00	98.47	0.00	99.44	0.00	92.94	0.10	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1648020583
97.49	0.01	99.25	0.03	96.11	0.00	100.00	0.00	96.15	0.00	98.54	0.07	99.44	0.00	92.94	0.00	/workspace/coverage/default/23.sysrst_ctrl_stress_all.1462923076
97.51	0.01	99.25	0.00	96.11	0.00	100.00	0.00	96.15	0.00	98.54	0.00	99.44	0.00	93.04	0.10	/workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.3808127004
97.52	0.01	99.25	0.00	96.11	0.00	100.00	0.00	96.15	0.00	98.54	0.00	99.44	0.00	93.15	0.10	/workspace/coverage/default/10.sysrst_ctrl_pin_override_test.1805351937
97.54	0.01	99.25	0.00	96.11	0.00	100.00	0.00	96.15	0.00	98.54	0.00	99.44	0.00	93.25	0.10	/workspace/coverage/default/12.sysrst_ctrl_combo_detect.976957201
97.55	0.01	99.25	0.00	96.11	0.00	100.00	0.00	96.15	0.00	98.54	0.00	99.44	0.00	93.35	0.10	/workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.2003172861
97.57	0.01	99.25	0.00	96.11	0.00	100.00	0.00	96.15	0.00	98.54	0.00	99.44	0.00	93.46	0.10	/workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.1517986266
97.58	0.01	99.25	0.00	96.11	0.00	100.00	0.00	96.15	0.00	98.54	0.00	99.44	0.00	93.56	0.10	/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.7597068
97.59	0.01	99.25	0.00	96.11	0.00	100.00	0.00	96.15	0.00	98.54	0.00	99.44	0.00	93.67	0.10	/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.1937058817
97.61	0.01	99.25	0.00	96.21	0.10	100.00	0.00	96.15	0.00	98.54	0.00	99.44	0.00	93.67	0.00	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.1479969735
97.62	0.01	99.25	0.00	96.26	0.05	100.00	0.00	96.15	0.00	98.57	0.03	99.44	0.00	93.67	0.00	/workspace/coverage/default/35.sysrst_ctrl_alert_test.3093645972
97.63	0.01	99.27	0.02	96.26	0.00	100.00	0.00	96.15	0.00	98.61	0.03	99.44	0.00	93.67	0.00	/workspace/coverage/default/0.sysrst_ctrl_edge_detect.3855202413
97.64	0.01	99.29	0.02	96.26	0.00	100.00	0.00	96.15	0.00	98.64	0.03	99.44	0.00	93.67	0.00	/workspace/coverage/default/27.sysrst_ctrl_edge_detect.3044955094
97.64	0.01	99.31	0.02	96.26	0.00	100.00	0.00	96.15	0.00	98.68	0.03	99.44	0.00	93.67	0.00	/workspace/coverage/default/28.sysrst_ctrl_edge_detect.2263419043
97.65	0.01	99.31	0.00	96.26	0.00	100.00	0.00	96.15	0.00	98.68	0.00	99.44	0.00	93.72	0.05	/workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.2076223418
97.66	0.01	99.31	0.00	96.26	0.00	100.00	0.00	96.15	0.00	98.68	0.00	99.44	0.00	93.77	0.05	/workspace/coverage/default/1.sysrst_ctrl_combo_detect.1902164699
97.66	0.01	99.31	0.00	96.26	0.00	100.00	0.00	96.15	0.00	98.68	0.00	99.44	0.00	93.82	0.05	/workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.1438628753
97.67	0.01	99.31	0.00	96.26	0.00	100.00	0.00	96.15	0.00	98.68	0.00	99.44	0.00	93.87	0.05	/workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.1077239206
97.68	0.01	99.31	0.00	96.26	0.00	100.00	0.00	96.15	0.00	98.68	0.00	99.44	0.00	93.93	0.05	/workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.596264520
97.69	0.01	99.31	0.00	96.26	0.00	100.00	0.00	96.15	0.00	98.68	0.00	99.44	0.00	93.98	0.05	/workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.2688261429
97.69	0.01	99.31	0.00	96.26	0.00	100.00	0.00	96.15	0.00	98.68	0.00	99.44	0.00	94.03	0.05	/workspace/coverage/default/27.sysrst_ctrl_combo_detect.2805577809
97.70	0.01	99.31	0.00	96.26	0.00	100.00	0.00	96.15	0.00	98.68	0.00	99.44	0.00	94.08	0.05	/workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.708195409
97.71	0.01	99.31	0.00	96.26	0.00	100.00	0.00	96.15	0.00	98.68	0.00	99.44	0.00	94.13	0.05	/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.2603208320
97.72	0.01	99.31	0.00	96.26	0.00	100.00	0.00	96.15	0.00	98.68	0.00	99.44	0.00	94.18	0.05	/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2368609254
97.72	0.01	99.31	0.00	96.26	0.00	100.00	0.00	96.15	0.00	98.68	0.00	99.44	0.00	94.24	0.05	/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.1308520382
97.73	0.01	99.31	0.00	96.26	0.00	100.00	0.00	96.15	0.00	98.68	0.00	99.44	0.00	94.29	0.05	/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.3237809214
97.73	0.01	99.31	0.00	96.28	0.02	100.00	0.00	96.15	0.00	98.68	0.00	99.44	0.00	94.29	0.00	/workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.1798441164
97.74	0.01	99.31	0.00	96.31	0.02	100.00	0.00	96.15	0.00	98.68	0.00	99.44	0.00	94.29	0.00	/workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.2111850020
97.74	0.01	99.31	0.00	96.33	0.02	100.00	0.00	96.15	0.00	98.68	0.00	99.44	0.00	94.29	0.00	/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.1322125471

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.817079989
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3532608958
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.848458551
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.2017943539
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.2063602935
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.2786931766
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2814839247
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.1401563092
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2095367003
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1475300349
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.983009868
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.4150073515
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.1344972552
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2671675770
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2824814218
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3100835795
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2772517203
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.3500639512
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.682381603
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3178194077
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.2704396458
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.351760908
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.3990424188
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.4009148637
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.762133254
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3891360118
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.1442253675
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.1791981620
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2848969005
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.2540049198
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3871736008
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.1050801850
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.2246730067
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2705277271
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.4191427680
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.3891718790
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.730852657
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3391292698
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1522580708
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.124268283
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.4233890544
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/workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.3945017939
/workspace/coverage/default/39.sysrst_ctrl_pin_access_test.3837407985
/workspace/coverage/default/39.sysrst_ctrl_pin_override_test.2323048534
/workspace/coverage/default/39.sysrst_ctrl_smoke.2319638982
/workspace/coverage/default/39.sysrst_ctrl_stress_all.1365594707
/workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.648804300
/workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.2766318487
/workspace/coverage/default/4.sysrst_ctrl_alert_test.418168040
/workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.1771103783
/workspace/coverage/default/4.sysrst_ctrl_combo_detect.143332944
/workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.157509791
/workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.2312141945
/workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.797452752
/workspace/coverage/default/4.sysrst_ctrl_edge_detect.3664288879
/workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.3066033810
/workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.2304960981
/workspace/coverage/default/4.sysrst_ctrl_pin_access_test.2622676947
/workspace/coverage/default/4.sysrst_ctrl_pin_override_test.23434877
/workspace/coverage/default/4.sysrst_ctrl_sec_cm.3364685724
/workspace/coverage/default/4.sysrst_ctrl_smoke.298591337
/workspace/coverage/default/4.sysrst_ctrl_stress_all.1201469441
/workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.3759268567
/workspace/coverage/default/40.sysrst_ctrl_alert_test.2522842385
/workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.3182570609
/workspace/coverage/default/40.sysrst_ctrl_combo_detect.2569912513
/workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.4258900568
/workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.3186274355
/workspace/coverage/default/40.sysrst_ctrl_edge_detect.1038545106
/workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.3916503688
/workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.1151934199
/workspace/coverage/default/40.sysrst_ctrl_pin_access_test.1189701019
/workspace/coverage/default/40.sysrst_ctrl_pin_override_test.2715942797
/workspace/coverage/default/40.sysrst_ctrl_smoke.4082900350
/workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.350141154
/workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.698487324
/workspace/coverage/default/41.sysrst_ctrl_alert_test.3120214655
/workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.3416602187
/workspace/coverage/default/41.sysrst_ctrl_combo_detect.1379907668
/workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.1327219098
/workspace/coverage/default/41.sysrst_ctrl_edge_detect.2723523306
/workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.2145576528
/workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.3928623930
/workspace/coverage/default/41.sysrst_ctrl_pin_access_test.3088352211
/workspace/coverage/default/41.sysrst_ctrl_pin_override_test.180833598
/workspace/coverage/default/41.sysrst_ctrl_smoke.2368544661
/workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.3303394979
/workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.3660039537
/workspace/coverage/default/42.sysrst_ctrl_alert_test.4102746468
/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.4180053159
/workspace/coverage/default/42.sysrst_ctrl_combo_detect.2877447018
/workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.2182971733
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.840097448
/workspace/coverage/default/42.sysrst_ctrl_edge_detect.2852067030
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.1920348357
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.3019685521
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.3713999392
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.2926464809
/workspace/coverage/default/42.sysrst_ctrl_smoke.3907314784
/workspace/coverage/default/42.sysrst_ctrl_stress_all.1959154633
/workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.3025247034
/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.2434529749
/workspace/coverage/default/43.sysrst_ctrl_alert_test.84992137
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.1611505672
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.2055803515
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.3114160384
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.1812813791
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.1009200809
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.4290466879
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.3195406397
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.2920502261
/workspace/coverage/default/43.sysrst_ctrl_smoke.2806187059
/workspace/coverage/default/43.sysrst_ctrl_stress_all.529219256
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.4017649229
/workspace/coverage/default/44.sysrst_ctrl_alert_test.3648096562
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.3297246962
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.1602694618
/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.457788
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.369016034
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.361130625
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.4235962459
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.757840079
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.623325671
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.759424770
/workspace/coverage/default/44.sysrst_ctrl_smoke.781555266
/workspace/coverage/default/44.sysrst_ctrl_stress_all.1831925510
/workspace/coverage/default/45.sysrst_ctrl_alert_test.3467545798
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.127977026
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.13454018
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.190677706
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.1580679347
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.3573406915
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.1245139645
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.4161209039
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.843685416
/workspace/coverage/default/45.sysrst_ctrl_smoke.699506049
/workspace/coverage/default/46.sysrst_ctrl_alert_test.1707200625
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.2313286625
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.2852644533
/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.1270847735
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.844000869
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.579059314
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.340909598
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.3173056494
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.740686756
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.2397183544
/workspace/coverage/default/46.sysrst_ctrl_smoke.1569304620
/workspace/coverage/default/46.sysrst_ctrl_stress_all.2499944565
/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1704014352
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.4113368724
/workspace/coverage/default/47.sysrst_ctrl_alert_test.1173554190
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.3768234678
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.3464001439
/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.366968157
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.3442866213
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.353774600
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.1064709206
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.1109661694
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.1753695340
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.3288726652
/workspace/coverage/default/47.sysrst_ctrl_smoke.3347165659
/workspace/coverage/default/47.sysrst_ctrl_stress_all.1719340666
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.3100025322
/workspace/coverage/default/48.sysrst_ctrl_alert_test.2534061255
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.538266632
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.2291631485
/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.4269370030
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.3394998188
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.322488360
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.1977175873
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.2829619650
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.141383769
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.4151216362
/workspace/coverage/default/48.sysrst_ctrl_smoke.3954366911
/workspace/coverage/default/48.sysrst_ctrl_stress_all.1045534743
/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.660978404
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.307553833
/workspace/coverage/default/49.sysrst_ctrl_alert_test.1265087890
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.832338779
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.2345487169
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.3307764376
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.2910776100
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.1044222141
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.3745608413
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.1686892429
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.840667466
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.2410229778
/workspace/coverage/default/49.sysrst_ctrl_smoke.3355048454
/workspace/coverage/default/49.sysrst_ctrl_stress_all.2732334399
/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.3866945827
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.3030539517
/workspace/coverage/default/5.sysrst_ctrl_alert_test.2491297596
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.2121872215
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.2417889911
/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.2693588407
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.3685889658
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.316887372
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.735599163
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.1488240485
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.668442024
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.3835411678
/workspace/coverage/default/5.sysrst_ctrl_smoke.419535003
/workspace/coverage/default/5.sysrst_ctrl_stress_all.2504771962
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.638285091
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.3719290909
/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.4198024295
/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.1417319673
/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.810914579
/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.35028577
/workspace/coverage/default/6.sysrst_ctrl_alert_test.988893417
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.2866450248
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.1118594724
/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.1840394973
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.1160236573
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.3977028574
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3265854576
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.2160416734
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.2934480264
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.3964542303
/workspace/coverage/default/6.sysrst_ctrl_smoke.2372122456
/workspace/coverage/default/6.sysrst_ctrl_stress_all.1454155594
/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.1616613584
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.1138818616
/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.3727655871
/workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.1212120774
/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.3902269151
/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.61358706
/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.1746191427
/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.4266980711
/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.3203045988
/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.968243487
/workspace/coverage/default/7.sysrst_ctrl_alert_test.720358491
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.159405536
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.34340085
/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.3464613131
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.670177131
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.2110975218
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.1724635071
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.10148266
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.2516849373
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.3480194200
/workspace/coverage/default/7.sysrst_ctrl_smoke.91232123
/workspace/coverage/default/7.sysrst_ctrl_stress_all.4263425069
/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.103593540
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.4151754391
/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.2183526577
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.1851457871
/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.1834734969
/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.182836140
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.1413548315
/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1741236683
/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.766976728
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.925517196
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.3604670645
/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.2796762540
/workspace/coverage/default/8.sysrst_ctrl_alert_test.4105982270
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.319768871
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.2312100620
/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.1344033774
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.3362983257
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.1023057411
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.1520324853
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.3510929605
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.3940327260
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.3263715687
/workspace/coverage/default/8.sysrst_ctrl_smoke.3391734624
/workspace/coverage/default/8.sysrst_ctrl_stress_all.2791261737
/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.128738968
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.2128488226
/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.537238005
/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.1334104514
/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.2528763166
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.1046897591
/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.2513071006
/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.2263624494
/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.421307798
/workspace/coverage/default/9.sysrst_ctrl_alert_test.3609009962
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.1090003375
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.1029345186
/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.804999868
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.135191643
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.1077334875
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.1668131140
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.3220336297
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.2214850860
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.2095242366
/workspace/coverage/default/9.sysrst_ctrl_smoke.1354251940
/workspace/coverage/default/9.sysrst_ctrl_stress_all.3522289192
/workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.3137745865
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.3672923306
/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.455797411
/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.2818749565
/workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.2478639116
/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.3900803322
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.4246517279
/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.1170624380

Total test records in report: 916

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.3355122793	Oct 08 01:17:47 PM PDT 23	Oct 08 01:17:49 PM PDT 23	2097242608 ps
T2	/workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.3006529615	Oct 08 12:47:03 PM PDT 23	Oct 08 12:47:34 PM PDT 23	42761202542 ps
T6	/workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.2540785949	Oct 08 01:48:29 PM PDT 23	Oct 08 01:48:36 PM PDT 23	2155029879 ps
T3	/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.2540049198	Oct 08 01:18:52 PM PDT 23	Oct 08 01:19:26 PM PDT 23	8172520388 ps
T7	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.773404224	Oct 08 12:25:59 PM PDT 23	Oct 08 12:26:29 PM PDT 23	43148548074 ps
T22	/workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.3830715200	Oct 08 01:26:19 PM PDT 23	Oct 08 01:26:21 PM PDT 23	2056461776 ps
T8	/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1401156073	Oct 08 01:21:00 PM PDT 23	Oct 08 01:22:01 PM PDT 23	22203683606 ps
T4	/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.203493357	Oct 08 01:22:52 PM PDT 23	Oct 08 01:23:04 PM PDT 23	9174431222 ps
T5	/workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.2209536896	Oct 08 01:23:11 PM PDT 23	Oct 08 01:23:18 PM PDT 23	4981837723 ps
T23	/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.682381603	Oct 08 12:37:51 PM PDT 23	Oct 08 12:37:57 PM PDT 23	2205002429 ps
T9	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1475300349	Oct 08 12:46:02 PM PDT 23	Oct 08 12:46:04 PM PDT 23	2113684149 ps
T253	/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2773451044	Oct 08 01:21:26 PM PDT 23	Oct 08 01:21:31 PM PDT 23	2161812149 ps
T37	/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2772517203	Oct 08 01:45:25 PM PDT 23	Oct 08 01:45:27 PM PDT 23	2038711993 ps
T10	/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2124055838	Oct 08 01:24:17 PM PDT 23	Oct 08 01:24:52 PM PDT 23	22199171004 ps
T11	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.2767599762	Oct 08 12:28:54 PM PDT 23	Oct 08 12:28:59 PM PDT 23	5257366878 ps
T261	/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.2246730067	Oct 08 01:22:41 PM PDT 23	Oct 08 01:22:48 PM PDT 23	2072005337 ps
T30	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2814839247	Oct 08 12:41:39 PM PDT 23	Oct 08 12:41:47 PM PDT 23	3230295789 ps
T38	/workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.242552157	Oct 08 01:36:34 PM PDT 23	Oct 08 01:36:40 PM PDT 23	2012782323 ps
T254	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.3749102501	Oct 08 12:31:05 PM PDT 23	Oct 08 12:31:14 PM PDT 23	2124506994 ps
T272	/workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.3970390105	Oct 08 01:24:20 PM PDT 23	Oct 08 01:24:26 PM PDT 23	2014835276 ps
T356	/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.2704396458	Oct 08 01:18:43 PM PDT 23	Oct 08 01:18:49 PM PDT 23	2027930954 ps
T335	/workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.3067545452	Oct 08 01:26:06 PM PDT 23	Oct 08 01:26:13 PM PDT 23	2012145976 ps
T31	/workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.602751936	Oct 08 12:44:28 PM PDT 23	Oct 08 12:44:35 PM PDT 23	2053161292 ps
T255	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2671675770	Oct 08 12:34:08 PM PDT 23	Oct 08 12:34:14 PM PDT 23	2053006347 ps
T262	/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2824814218	Oct 08 01:41:19 PM PDT 23	Oct 08 01:41:21 PM PDT 23	2079524210 ps
T283	/workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.660633459	Oct 08 01:19:23 PM PDT 23	Oct 08 01:19:26 PM PDT 23	2022177987 ps
T256	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.878944177	Oct 08 12:38:11 PM PDT 23	Oct 08 12:39:58 PM PDT 23	42446878499 ps
T273	/workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.2537664823	Oct 08 01:21:31 PM PDT 23	Oct 08 01:21:34 PM PDT 23	2025923976 ps
T277	/workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.1560093056	Oct 08 01:41:27 PM PDT 23	Oct 08 01:41:35 PM PDT 23	2047222031 ps
T287	/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.696537015	Oct 08 01:19:11 PM PDT 23	Oct 08 01:19:17 PM PDT 23	2010827149 ps
T288	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.1576473376	Oct 08 01:09:14 PM PDT 23	Oct 08 01:09:18 PM PDT 23	2022689797 ps
T263	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.945378704	Oct 08 12:44:33 PM PDT 23	Oct 08 12:47:17 PM PDT 23	68780964167 ps
T32	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.3775456815	Oct 08 01:03:56 PM PDT 23	Oct 08 01:04:32 PM PDT 23	7971047210 ps
T274	/workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.3808127004	Oct 08 01:20:45 PM PDT 23	Oct 08 01:20:51 PM PDT 23	2012498881 ps
T336	/workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.3418553760	Oct 08 01:26:08 PM PDT 23	Oct 08 01:26:14 PM PDT 23	2010643820 ps
T357	/workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.2658786603	Oct 08 01:24:34 PM PDT 23	Oct 08 01:24:36 PM PDT 23	2041456961 ps
T33	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.3282005789	Oct 08 12:34:39 PM PDT 23	Oct 08 12:34:40 PM PDT 23	2168888048 ps
T358	/workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.3593878861	Oct 08 12:31:25 PM PDT 23	Oct 08 12:31:27 PM PDT 23	2035366872 ps
T264	/workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.4167564800	Oct 08 12:36:14 PM PDT 23	Oct 08 12:36:20 PM PDT 23	2081193276 ps
T278	/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.1079093538	Oct 08 01:22:01 PM PDT 23	Oct 08 01:22:04 PM PDT 23	2128726475 ps
T279	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.1367543606	Oct 08 12:44:38 PM PDT 23	Oct 08 12:44:46 PM PDT 23	2035123882 ps
T359	/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2199666068	Oct 08 01:19:30 PM PDT 23	Oct 08 01:19:34 PM PDT 23	2414244458 ps
T360	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.3756865056	Oct 08 12:44:13 PM PDT 23	Oct 08 12:44:17 PM PDT 23	2584366859 ps
T280	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.1164137607	Oct 08 01:12:34 PM PDT 23	Oct 08 01:12:42 PM PDT 23	3153804461 ps
T361	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.1482045818	Oct 08 12:26:27 PM PDT 23	Oct 08 12:29:50 PM PDT 23	74973597955 ps
T362	/workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.729014503	Oct 08 01:44:54 PM PDT 23	Oct 08 01:44:57 PM PDT 23	2403718605 ps
T363	/workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.378749263	Oct 08 02:09:17 PM PDT 23	Oct 08 02:09:19 PM PDT 23	2039608965 ps
T281	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.2017943539	Oct 08 12:42:50 PM PDT 23	Oct 08 12:42:54 PM PDT 23	2038280079 ps
T364	/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1522580708	Oct 08 01:19:59 PM PDT 23	Oct 08 01:20:05 PM PDT 23	2063897349 ps
T365	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.1479969735	Oct 08 12:44:38 PM PDT 23	Oct 08 12:44:41 PM PDT 23	2733823855 ps
T366	/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.56357888	Oct 08 01:18:58 PM PDT 23	Oct 08 01:19:05 PM PDT 23	2033831462 ps
T367	/workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.2917499134	Oct 08 12:44:41 PM PDT 23	Oct 08 12:44:58 PM PDT 23	42740847358 ps
T368	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.2422844830	Oct 08 01:13:34 PM PDT 23	Oct 08 01:13:37 PM PDT 23	2020335827 ps
T355	/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.1134632101	Oct 08 01:19:07 PM PDT 23	Oct 08 01:19:09 PM PDT 23	2124506277 ps
T369	/workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.2921963129	Oct 08 01:21:50 PM PDT 23	Oct 08 01:21:56 PM PDT 23	2012924192 ps
T282	/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.948706547	Oct 08 01:19:28 PM PDT 23	Oct 08 01:19:30 PM PDT 23	2069949958 ps
T370	/workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.1196045797	Oct 08 01:23:52 PM PDT 23	Oct 08 01:23:58 PM PDT 23	2010858906 ps
T310	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1648020583	Oct 08 12:40:04 PM PDT 23	Oct 08 12:40:39 PM PDT 23	42762947971 ps
T371	/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.3374516481	Oct 08 01:23:45 PM PDT 23	Oct 08 01:23:48 PM PDT 23	2036143265 ps
T372	/workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.2563005124	Oct 08 01:04:54 PM PDT 23	Oct 08 01:04:56 PM PDT 23	2094826164 ps
T265	/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2320226145	Oct 08 01:20:58 PM PDT 23	Oct 08 01:21:05 PM PDT 23	2077879437 ps
T266	/workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.3331448460	Oct 08 12:43:21 PM PDT 23	Oct 08 12:43:27 PM PDT 23	2074220028 ps
T373	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.1700016909	Oct 08 12:51:02 PM PDT 23	Oct 08 12:51:10 PM PDT 23	2083349293 ps
T374	/workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.471394775	Oct 08 12:28:50 PM PDT 23	Oct 08 12:29:41 PM PDT 23	22244235134 ps
T267	/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.124268283	Oct 08 01:18:55 PM PDT 23	Oct 08 01:18:58 PM PDT 23	2048061184 ps
T296	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.2786931766	Oct 08 12:39:44 PM PDT 23	Oct 08 12:39:51 PM PDT 23	5353065625 ps
T375	/workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.767823605	Oct 08 12:43:49 PM PDT 23	Oct 08 12:43:55 PM PDT 23	2011367994 ps
T271	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.2207722939	Oct 08 01:36:15 PM PDT 23	Oct 08 01:36:21 PM PDT 23	2029618632 ps
T376	/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2848969005	Oct 08 01:19:04 PM PDT 23	Oct 08 01:19:10 PM PDT 23	2010717536 ps
T377	/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2705277271	Oct 08 01:19:21 PM PDT 23	Oct 08 01:19:23 PM PDT 23	2070149213 ps
T284	/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.1162720130	Oct 08 01:19:59 PM PDT 23	Oct 08 01:20:05 PM PDT 23	2031316051 ps
T378	/workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.3224084406	Oct 08 01:19:25 PM PDT 23	Oct 08 01:19:30 PM PDT 23	2015470980 ps
T268	/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.3531827170	Oct 08 01:20:25 PM PDT 23	Oct 08 01:20:56 PM PDT 23	42946871004 ps
T379	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.544687917	Oct 08 01:37:20 PM PDT 23	Oct 08 01:37:33 PM PDT 23	5552467615 ps
T380	/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.1791981620	Oct 08 01:21:42 PM PDT 23	Oct 08 01:21:45 PM PDT 23	2062407201 ps
T381	/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.730852657	Oct 08 01:19:51 PM PDT 23	Oct 08 01:19:56 PM PDT 23	2055791580 ps
T382	/workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.1642217924	Oct 08 01:24:22 PM PDT 23	Oct 08 01:24:56 PM PDT 23	7486220764 ps
T311	/workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.2534905796	Oct 08 12:38:51 PM PDT 23	Oct 08 12:39:09 PM PDT 23	22236718174 ps
T383	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.216239668	Oct 08 12:32:05 PM PDT 23	Oct 08 12:32:07 PM PDT 23	2099718784 ps
T269	/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.164035193	Oct 08 01:19:12 PM PDT 23	Oct 08 01:19:16 PM PDT 23	2177148927 ps
T384	/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.672020515	Oct 08 01:18:59 PM PDT 23	Oct 08 01:19:57 PM PDT 23	42417372413 ps
T385	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.643926249	Oct 08 12:47:06 PM PDT 23	Oct 08 12:48:01 PM PDT 23	22227866097 ps
T386	/workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.2163244955	Oct 08 01:26:16 PM PDT 23	Oct 08 01:26:20 PM PDT 23	2021486078 ps
T270	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.4209348637	Oct 08 12:40:14 PM PDT 23	Oct 08 12:40:21 PM PDT 23	2325584666 ps
T275	/workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.330304457	Oct 08 12:28:19 PM PDT 23	Oct 08 12:28:22 PM PDT 23	2076378318 ps
T387	/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.3990424188	Oct 08 01:21:39 PM PDT 23	Oct 08 01:21:45 PM PDT 23	2015414595 ps
T276	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.1344972552	Oct 08 12:32:22 PM PDT 23	Oct 08 12:32:35 PM PDT 23	8921855931 ps
T285	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.1142643222	Oct 08 12:45:09 PM PDT 23	Oct 08 12:45:11 PM PDT 23	4077413226 ps
T388	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.983009868	Oct 08 12:32:22 PM PDT 23	Oct 08 12:32:24 PM PDT 23	2117697791 ps
T389	/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.1764319341	Oct 08 01:24:30 PM PDT 23	Oct 08 01:24:39 PM PDT 23	8081549697 ps
T390	/workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.4135272241	Oct 08 01:25:54 PM PDT 23	Oct 08 01:26:00 PM PDT 23	2015139612 ps
T391	/workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.802353743	Oct 08 01:19:00 PM PDT 23	Oct 08 01:19:12 PM PDT 23	10204891927 ps
T392	/workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.3779842591	Oct 08 01:21:48 PM PDT 23	Oct 08 01:21:54 PM PDT 23	2016493837 ps
T393	/workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.676897076	Oct 08 01:20:01 PM PDT 23	Oct 08 01:20:04 PM PDT 23	2034449351 ps
T394	/workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.2682631208	Oct 08 12:31:25 PM PDT 23	Oct 08 12:31:28 PM PDT 23	2064478805 ps
T286	/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.153713052	Oct 08 01:20:17 PM PDT 23	Oct 08 01:20:19 PM PDT 23	2065834968 ps
T395	/workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.1035554627	Oct 08 01:20:03 PM PDT 23	Oct 08 01:20:07 PM PDT 23	2021022278 ps
T396	/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.2697949392	Oct 08 01:18:54 PM PDT 23	Oct 08 01:19:15 PM PDT 23	5266205333 ps
T397	/workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.2912969367	Oct 08 12:38:49 PM PDT 23	Oct 08 12:38:53 PM PDT 23	2027815715 ps
T398	/workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.2952674653	Oct 08 01:19:24 PM PDT 23	Oct 08 01:19:30 PM PDT 23	2018850027 ps
T399	/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.3981826070	Oct 08 01:19:08 PM PDT 23	Oct 08 01:19:10 PM PDT 23	2025802382 ps
T400	/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.1453227201	Oct 08 01:21:31 PM PDT 23	Oct 08 01:21:36 PM PDT 23	2013513543 ps
T401	/workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.753911134	Oct 08 01:36:39 PM PDT 23	Oct 08 01:36:45 PM PDT 23	5258324438 ps
T402	/workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.3564132221	Oct 08 12:33:33 PM PDT 23	Oct 08 12:33:41 PM PDT 23	2046912184 ps
T403	/workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.2550869967	Oct 08 01:20:23 PM PDT 23	Oct 08 01:20:29 PM PDT 23	2014138836 ps
T312	/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3178194077	Oct 08 01:46:22 PM PDT 23	Oct 08 01:46:39 PM PDT 23	22248664043 ps
T289	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.791137167	Oct 08 12:31:54 PM PDT 23	Oct 08 12:32:15 PM PDT 23	42040684191 ps
T64	/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3803113187	Oct 08 01:19:49 PM PDT 23	Oct 08 01:20:16 PM PDT 23	42988496120 ps
T404	/workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.2745127225	Oct 08 01:03:26 PM PDT 23	Oct 08 01:03:32 PM PDT 23	2025518075 ps
T405	/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.4009148637	Oct 08 01:21:00 PM PDT 23	Oct 08 01:21:06 PM PDT 23	5746365314 ps
T406	/workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.2193850516	Oct 08 01:23:54 PM PDT 23	Oct 08 01:24:01 PM PDT 23	2009077210 ps
T407	/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.1157542523	Oct 08 01:20:53 PM PDT 23	Oct 08 01:20:59 PM PDT 23	2030997263 ps
T408	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.4261873443	Oct 08 12:58:44 PM PDT 23	Oct 08 12:58:46 PM PDT 23	2146773409 ps
T409	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.2063602935	Oct 08 12:29:03 PM PDT 23	Oct 08 12:29:05 PM PDT 23	2046906209 ps
T410	/workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.1920527319	Oct 08 01:20:19 PM PDT 23	Oct 08 01:20:21 PM PDT 23	2057130553 ps
T290	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.1401563092	Oct 08 12:40:12 PM PDT 23	Oct 08 12:41:02 PM PDT 23	52241721472 ps
T34	/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.1417319673	Oct 08 01:25:31 PM PDT 23	Oct 08 01:25:49 PM PDT 23	27109707607 ps
T35	/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.804999868	Oct 08 01:21:10 PM PDT 23	Oct 08 01:23:50 PM PDT 23	62080962718 ps
T36	/workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.3642124657	Oct 08 01:26:40 PM PDT 23	Oct 08 01:27:27 PM PDT 23	17465563376 ps
T69	/workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.3039829872	Oct 08 01:20:55 PM PDT 23	Oct 08 01:21:05 PM PDT 23	3490069366 ps
T12	/workspace/coverage/default/40.sysrst_ctrl_stress_all.253699753	Oct 08 01:33:11 PM PDT 23	Oct 08 01:33:32 PM PDT 23	16731623980 ps
T13	/workspace/coverage/default/41.sysrst_ctrl_stress_all.2694204565	Oct 08 01:30:35 PM PDT 23	Oct 08 01:33:01 PM PDT 23	59383929485 ps
T24	/workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.952041555	Oct 08 01:23:17 PM PDT 23	Oct 08 01:23:20 PM PDT 23	2633340685 ps
T25	/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.2866450248	Oct 08 01:21:44 PM PDT 23	Oct 08 01:21:54 PM PDT 23	3580224387 ps
T26	/workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.2382620104	Oct 08 01:19:56 PM PDT 23	Oct 08 01:19:59 PM PDT 23	3391603399 ps
T27	/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.3900803322	Oct 08 01:26:06 PM PDT 23	Oct 08 01:27:07 PM PDT 23	22831755156 ps
T28	/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.2214850860	Oct 08 01:26:09 PM PDT 23	Oct 08 01:26:13 PM PDT 23	2061506854 ps
T14	/workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.3032356055	Oct 08 01:23:08 PM PDT 23	Oct 08 01:23:16 PM PDT 23	5941256056 ps
T15	/workspace/coverage/default/41.sysrst_ctrl_combo_detect.1379907668	Oct 08 01:25:05 PM PDT 23	Oct 08 01:25:51 PM PDT 23	65442139680 ps
T29	/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.2016670700	Oct 08 01:40:41 PM PDT 23	Oct 08 01:42:07 PM PDT 23	125871168522 ps
T56	/workspace/coverage/default/48.sysrst_ctrl_alert_test.2534061255	Oct 08 01:30:05 PM PDT 23	Oct 08 01:30:09 PM PDT 23	2014464848 ps
T16	/workspace/coverage/default/1.sysrst_ctrl_edge_detect.2023860505	Oct 08 01:23:36 PM PDT 23	Oct 08 01:23:42 PM PDT 23	2446825957 ps
T17	/workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.1549538735	Oct 08 01:26:20 PM PDT 23	Oct 08 01:27:38 PM PDT 23	574825615613 ps
T57	/workspace/coverage/default/7.sysrst_ctrl_smoke.91232123	Oct 08 01:23:57 PM PDT 23	Oct 08 01:24:03 PM PDT 23	2114705536 ps
T18	/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.1138818616	Oct 08 01:21:45 PM PDT 23	Oct 08 01:21:53 PM PDT 23	11123260289 ps
T58	/workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.1327219098	Oct 08 01:24:36 PM PDT 23	Oct 08 01:24:45 PM PDT 23	3079717249 ps
T257	/workspace/coverage/default/35.sysrst_ctrl_alert_test.3093645972	Oct 08 01:41:07 PM PDT 23	Oct 08 01:41:10 PM PDT 23	2025324305 ps
T63	/workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.2384378474	Oct 08 01:33:51 PM PDT 23	Oct 08 01:33:54 PM PDT 23	2479797074 ps
T118	/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.369016034	Oct 08 01:26:23 PM PDT 23	Oct 08 01:26:27 PM PDT 23	2870781377 ps
T19	/workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.576268303	Oct 08 01:22:25 PM PDT 23	Oct 08 01:23:46 PM PDT 23	31661965269 ps
T20	/workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.1467359850	Oct 08 01:21:15 PM PDT 23	Oct 08 01:21:57 PM PDT 23	145138283391 ps
T117	/workspace/coverage/default/4.sysrst_ctrl_sec_cm.3364685724	Oct 08 01:20:30 PM PDT 23	Oct 08 01:21:13 PM PDT 23	42055348294 ps
T119	/workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.767994699	Oct 08 01:36:55 PM PDT 23	Oct 08 01:37:03 PM PDT 23	2612093391 ps
T21	/workspace/coverage/default/3.sysrst_ctrl_combo_detect.2127460987	Oct 08 01:20:42 PM PDT 23	Oct 08 01:22:23 PM PDT 23	68004082540 ps
T120	/workspace/coverage/default/6.sysrst_ctrl_stress_all.1454155594	Oct 08 01:20:07 PM PDT 23	Oct 08 01:20:23 PM PDT 23	11866246594 ps
T59	/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.2128488226	Oct 08 01:22:43 PM PDT 23	Oct 08 01:22:50 PM PDT 23	5602182630 ps
T51	/workspace/coverage/default/22.sysrst_ctrl_edge_detect.3985466934	Oct 08 01:21:57 PM PDT 23	Oct 08 01:22:03 PM PDT 23	5105775046 ps
T82	/workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.2478639116	Oct 08 01:41:43 PM PDT 23	Oct 08 01:42:31 PM PDT 23	93886886560 ps
T50	/workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.3765379695	Oct 08 01:22:07 PM PDT 23	Oct 08 01:23:18 PM PDT 23	45399963038 ps
T132	/workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.2641920011	Oct 08 01:24:20 PM PDT 23	Oct 08 01:24:28 PM PDT 23	2613345397 ps
T133	/workspace/coverage/default/46.sysrst_ctrl_alert_test.1707200625	Oct 08 01:25:07 PM PDT 23	Oct 08 01:25:08 PM PDT 23	2094859970 ps
T134	/workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.3790118823	Oct 08 01:24:36 PM PDT 23	Oct 08 01:24:44 PM PDT 23	2610716549 ps
T135	/workspace/coverage/default/21.sysrst_ctrl_pin_override_test.117202348	Oct 08 01:21:44 PM PDT 23	Oct 08 01:21:48 PM PDT 23	2516435061 ps
T39	/workspace/coverage/default/12.sysrst_ctrl_stress_all.3187674496	Oct 08 01:21:12 PM PDT 23	Oct 08 01:21:37 PM PDT 23	9104787097 ps
T136	/workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.513000876	Oct 08 01:22:39 PM PDT 23	Oct 08 01:22:42 PM PDT 23	2490968781 ps
T52	/workspace/coverage/default/24.sysrst_ctrl_stress_all.2412493567	Oct 08 01:24:51 PM PDT 23	Oct 08 01:30:35 PM PDT 23	157916136842 ps
T83	/workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.2177226638	Oct 08 01:25:23 PM PDT 23	Oct 08 01:25:27 PM PDT 23	3516199317 ps
T411	/workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.3163772599	Oct 08 01:22:20 PM PDT 23	Oct 08 01:22:24 PM PDT 23	2614843516 ps
T84	/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.2313286625	Oct 08 01:31:35 PM PDT 23	Oct 08 01:31:40 PM PDT 23	3747035524 ps
T412	/workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.934354960	Oct 08 01:20:43 PM PDT 23	Oct 08 01:20:47 PM PDT 23	2617449704 ps
T413	/workspace/coverage/default/18.sysrst_ctrl_smoke.2105296733	Oct 08 01:21:38 PM PDT 23	Oct 08 01:21:42 PM PDT 23	2118870132 ps
T258	/workspace/coverage/default/10.sysrst_ctrl_alert_test.1150238826	Oct 08 01:21:49 PM PDT 23	Oct 08 01:21:51 PM PDT 23	2035850137 ps
T60	/workspace/coverage/default/26.sysrst_ctrl_stress_all.3544728327	Oct 08 01:23:19 PM PDT 23	Oct 08 01:23:45 PM PDT 23	9823751975 ps
T297	/workspace/coverage/default/1.sysrst_ctrl_stress_all.4074776476	Oct 08 01:19:27 PM PDT 23	Oct 08 01:19:32 PM PDT 23	12709600789 ps
T44	/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1741236683	Oct 08 01:27:46 PM PDT 23	Oct 08 01:28:33 PM PDT 23	65794686147 ps
T40	/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.1170624380	Oct 08 01:37:59 PM PDT 23	Oct 08 01:38:38 PM PDT 23	56310948125 ps
T351	/workspace/coverage/default/10.sysrst_ctrl_pin_override_test.1805351937	Oct 08 01:24:19 PM PDT 23	Oct 08 01:24:23 PM PDT 23	2519567983 ps
T352	/workspace/coverage/default/31.sysrst_ctrl_pin_override_test.2275230200	Oct 08 01:32:25 PM PDT 23	Oct 08 01:32:32 PM PDT 23	2509380921 ps
T85	/workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.660637191	Oct 08 01:32:53 PM PDT 23	Oct 08 01:38:25 PM PDT 23	254089152140 ps
T53	/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.3604670645	Oct 08 01:31:25 PM PDT 23	Oct 08 01:32:13 PM PDT 23	65531037767 ps
T414	/workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.2418686285	Oct 08 01:23:43 PM PDT 23	Oct 08 01:23:51 PM PDT 23	2612258489 ps
T353	/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.2397183544	Oct 08 01:31:30 PM PDT 23	Oct 08 01:31:32 PM PDT 23	2527652779 ps
T86	/workspace/coverage/default/16.sysrst_ctrl_stress_all.3855631426	Oct 08 01:22:07 PM PDT 23	Oct 08 01:22:29 PM PDT 23	8437125800 ps
T54	/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.2802225142	Oct 08 01:32:04 PM PDT 23	Oct 08 01:35:07 PM PDT 23	131205124564 ps
T46	/workspace/coverage/default/18.sysrst_ctrl_edge_detect.3353114560	Oct 08 01:21:25 PM PDT 23	Oct 08 01:21:28 PM PDT 23	2638557244 ps
T87	/workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.2370438203	Oct 08 01:34:01 PM PDT 23	Oct 08 01:45:40 PM PDT 23	293939840098 ps
T415	/workspace/coverage/default/32.sysrst_ctrl_stress_all.2581337981	Oct 08 01:26:42 PM PDT 23	Oct 08 01:26:53 PM PDT 23	6275072121 ps
T251	/workspace/coverage/default/1.sysrst_ctrl_sec_cm.2735808336	Oct 08 01:19:30 PM PDT 23	Oct 08 01:20:28 PM PDT 23	22010857722 ps
T42	/workspace/coverage/default/4.sysrst_ctrl_combo_detect.143332944	Oct 08 01:24:24 PM PDT 23	Oct 08 01:25:01 PM PDT 23	65829382474 ps
T43	/workspace/coverage/default/22.sysrst_ctrl_combo_detect.3555765180	Oct 08 01:37:02 PM PDT 23	Oct 08 01:38:20 PM PDT 23	115310499043 ps
T101	/workspace/coverage/default/38.sysrst_ctrl_pin_access_test.3217294528	Oct 08 01:24:39 PM PDT 23	Oct 08 01:24:46 PM PDT 23	2252018161 ps
T102	/workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.1997470321	Oct 08 01:21:27 PM PDT 23	Oct 08 01:21:30 PM PDT 23	2917127680 ps
T45	/workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.2297203465	Oct 08 01:33:00 PM PDT 23	Oct 08 01:34:21 PM PDT 23	819721053737 ps
T61	/workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.4121775419	Oct 08 01:24:12 PM PDT 23	Oct 08 01:25:01 PM PDT 23	38886299745 ps
T103	/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.1668131140	Oct 08 01:26:16 PM PDT 23	Oct 08 01:26:24 PM PDT 23	2612411206 ps
T104	/workspace/coverage/default/26.sysrst_ctrl_pin_override_test.4054751293	Oct 08 01:23:22 PM PDT 23	Oct 08 01:23:25 PM PDT 23	2527226635 ps
T105	/workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.2943904159	Oct 08 01:23:25 PM PDT 23	Oct 08 01:23:27 PM PDT 23	2490145219 ps
T106	/workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.3473472721	Oct 08 01:24:01 PM PDT 23	Oct 08 01:24:09 PM PDT 23	3079751566 ps
T128	/workspace/coverage/default/39.sysrst_ctrl_pin_access_test.3837407985	Oct 08 01:25:36 PM PDT 23	Oct 08 01:25:38 PM PDT 23	2203691794 ps
T129	/workspace/coverage/default/43.sysrst_ctrl_combo_detect.2055803515	Oct 08 01:24:03 PM PDT 23	Oct 08 01:27:46 PM PDT 23	83374772228 ps
T62	/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.307553833	Oct 08 01:30:31 PM PDT 23	Oct 08 01:30:36 PM PDT 23	9414314093 ps
T47	/workspace/coverage/default/23.sysrst_ctrl_edge_detect.2719172545	Oct 08 01:31:25 PM PDT 23	Oct 08 01:31:35 PM PDT 23	5135021338 ps
T122	/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.319768871	Oct 08 01:25:53 PM PDT 23	Oct 08 01:31:37 PM PDT 23	132568292643 ps
T211	/workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.3186274355	Oct 08 01:32:57 PM PDT 23	Oct 08 01:32:59 PM PDT 23	2974741612 ps
T212	/workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.3660039537	Oct 08 01:29:43 PM PDT 23	Oct 08 01:29:45 PM PDT 23	4655071516 ps
T116	/workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.1950927991	Oct 08 01:28:20 PM PDT 23	Oct 08 01:29:21 PM PDT 23	73271239816 ps
T237	/workspace/coverage/default/2.sysrst_ctrl_combo_detect.3018638579	Oct 08 01:22:36 PM PDT 23	Oct 08 01:23:39 PM PDT 23	84355713466 ps
T416	/workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.3359204136	Oct 08 01:21:02 PM PDT 23	Oct 08 01:21:10 PM PDT 23	4175962174 ps
T417	/workspace/coverage/default/8.sysrst_ctrl_alert_test.4105982270	Oct 08 01:21:43 PM PDT 23	Oct 08 01:21:44 PM PDT 23	2150555486 ps
T418	/workspace/coverage/default/44.sysrst_ctrl_stress_all.1831925510	Oct 08 01:24:57 PM PDT 23	Oct 08 01:25:02 PM PDT 23	6253512614 ps
T419	/workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.4136791987	Oct 08 01:27:02 PM PDT 23	Oct 08 01:27:11 PM PDT 23	3276811944 ps
T55	/workspace/coverage/default/3.sysrst_ctrl_edge_detect.4058909442	Oct 08 01:20:49 PM PDT 23	Oct 08 01:20:51 PM PDT 23	3296390507 ps
T420	/workspace/coverage/default/34.sysrst_ctrl_pin_access_test.2907665115	Oct 08 01:34:08 PM PDT 23	Oct 08 01:34:14 PM PDT 23	2121373295 ps
T238	/workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.260204756	Oct 08 01:23:15 PM PDT 23	Oct 08 01:24:23 PM PDT 23	53274528983 ps
T421	/workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.1645325043	Oct 08 01:22:34 PM PDT 23	Oct 08 01:22:39 PM PDT 23	2628181664 ps
T247	/workspace/coverage/default/36.sysrst_ctrl_combo_detect.1763395251	Oct 08 01:27:09 PM PDT 23	Oct 08 01:30:32 PM PDT 23	77846250633 ps
T422	/workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.3416602187	Oct 08 01:29:45 PM PDT 23	Oct 08 01:29:54 PM PDT 23	3313138591 ps
T48	/workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.3337396011	Oct 08 01:25:09 PM PDT 23	Oct 08 01:26:17 PM PDT 23	101183117929 ps
T165	/workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.1923829598	Oct 08 01:29:50 PM PDT 23	Oct 08 01:29:55 PM PDT 23	4910652459 ps
T71	/workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.1438628753	Oct 08 01:20:44 PM PDT 23	Oct 08 01:26:41 PM PDT 23	134864611770 ps
T166	/workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.3759268567	Oct 08 01:20:14 PM PDT 23	Oct 08 01:20:21 PM PDT 23	4271403374 ps
T41	/workspace/coverage/default/11.sysrst_ctrl_stress_all.2477118480	Oct 08 01:20:41 PM PDT 23	Oct 08 01:22:43 PM PDT 23	189116873882 ps
T167	/workspace/coverage/default/1.sysrst_ctrl_combo_detect.1902164699	Oct 08 01:19:30 PM PDT 23	Oct 08 01:22:08 PM PDT 23	68404282513 ps
T168	/workspace/coverage/default/7.sysrst_ctrl_edge_detect.2110975218	Oct 08 01:20:33 PM PDT 23	Oct 08 01:20:35 PM PDT 23	3611972847 ps
T169	/workspace/coverage/default/4.sysrst_ctrl_smoke.298591337	Oct 08 01:20:11 PM PDT 23	Oct 08 01:20:13 PM PDT 23	2156630912 ps
T170	/workspace/coverage/default/43.sysrst_ctrl_alert_test.84992137	Oct 08 01:31:42 PM PDT 23	Oct 08 01:31:48 PM PDT 23	2019584324 ps
T423	/workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.3025247034	Oct 08 01:24:33 PM PDT 23	Oct 08 01:25:35 PM PDT 23	21929070592 ps
T424	/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.759424770	Oct 08 01:29:40 PM PDT 23	Oct 08 01:29:42 PM PDT 23	2660301499 ps
T425	/workspace/coverage/default/40.sysrst_ctrl_pin_access_test.1189701019	Oct 08 01:34:53 PM PDT 23	Oct 08 01:35:00 PM PDT 23	2186079621 ps
T426	/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.3573406915	Oct 08 01:34:14 PM PDT 23	Oct 08 01:34:21 PM PDT 23	2613864089 ps
T427	/workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.2948630809	Oct 08 01:28:30 PM PDT 23	Oct 08 01:28:36 PM PDT 23	2457885384 ps
T428	/workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.2197443091	Oct 08 01:21:17 PM PDT 23	Oct 08 01:21:19 PM PDT 23	3345454848 ps
T429	/workspace/coverage/default/44.sysrst_ctrl_alert_test.3648096562	Oct 08 01:25:01 PM PDT 23	Oct 08 01:25:07 PM PDT 23	2018505241 ps
T121	/workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.3804339666	Oct 08 01:20:54 PM PDT 23	Oct 08 01:23:49 PM PDT 23	1104012985182 ps
T430	/workspace/coverage/default/9.sysrst_ctrl_smoke.1354251940	Oct 08 01:26:09 PM PDT 23	Oct 08 01:26:13 PM PDT 23	2111899017 ps
T234	/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.968243487	Oct 08 01:25:51 PM PDT 23	Oct 08 01:29:16 PM PDT 23	75854394953 ps
T431	/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.3100025322	Oct 08 01:31:35 PM PDT 23	Oct 08 01:31:43 PM PDT 23	6173038970 ps
T354	/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.3835411678	Oct 08 01:24:16 PM PDT 23	Oct 08 01:24:19 PM PDT 23	2526931315 ps
T432	/workspace/coverage/default/27.sysrst_ctrl_stress_all.1000156686	Oct 08 01:27:11 PM PDT 23	Oct 08 01:27:45 PM PDT 23	13426413243 ps
T433	/workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.1749498901	Oct 08 01:23:18 PM PDT 23	Oct 08 01:23:29 PM PDT 23	3604491509 ps
T434	/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.670177131	Oct 08 01:26:48 PM PDT 23	Oct 08 01:26:50 PM PDT 23	3712257190 ps
T88	/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.3719290909	Oct 08 01:25:18 PM PDT 23	Oct 08 01:26:19 PM PDT 23	24581568515 ps
T435	/workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.2308672657	Oct 08 01:23:07 PM PDT 23	Oct 08 01:23:10 PM PDT 23	2622963158 ps
T436	/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.2095242366	Oct 08 01:20:34 PM PDT 23	Oct 08 01:20:37 PM PDT 23	2528799148 ps
T49	/workspace/coverage/default/47.sysrst_ctrl_edge_detect.353774600	Oct 08 01:29:01 PM PDT 23	Oct 08 01:29:04 PM PDT 23	4216932970 ps
T193	/workspace/coverage/default/37.sysrst_ctrl_combo_detect.1003638819	Oct 08 01:25:38 PM PDT 23	Oct 08 01:26:03 PM PDT 23	63422867125 ps
T437	/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.2516849373	Oct 08 01:20:23 PM PDT 23	Oct 08 01:20:25 PM PDT 23	2157689898 ps
T70	/workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.3059508339	Oct 08 01:22:16 PM PDT 23	Oct 08 01:22:52 PM PDT 23	79684399638 ps
T107	/workspace/coverage/default/17.sysrst_ctrl_edge_detect.3174643794	Oct 08 01:28:25 PM PDT 23	Oct 08 01:28:30 PM PDT 23	3484541302 ps
T108	/workspace/coverage/default/49.sysrst_ctrl_combo_detect.2345487169	Oct 08 01:25:05 PM PDT 23	Oct 08 01:29:48 PM PDT 23	114772825179 ps
T109	/workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.250440731	Oct 08 01:22:57 PM PDT 23	Oct 08 01:23:00 PM PDT 23	3437114759 ps
T110	/workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.265223551	Oct 08 01:24:28 PM PDT 23	Oct 08 01:24:31 PM PDT 23	3389844784 ps
T111	/workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.2957795417	Oct 08 01:34:54 PM PDT 23	Oct 08 01:34:56 PM PDT 23	3470508172 ps
T112	/workspace/coverage/default/35.sysrst_ctrl_combo_detect.382337676	Oct 08 01:40:45 PM PDT 23	Oct 08 01:42:35 PM PDT 23	148864299658 ps
T113	/workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.3916503688	Oct 08 01:25:19 PM PDT 23	Oct 08 01:25:27 PM PDT 23	2614318880 ps
T114	/workspace/coverage/default/16.sysrst_ctrl_edge_detect.2794294764	Oct 08 01:21:10 PM PDT 23	Oct 08 01:21:13 PM PDT 23	3580477919 ps
T115	/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.3902269151	Oct 08 01:26:36 PM PDT 23	Oct 08 01:27:30 PM PDT 23	78624760397 ps
T78	/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.450404438	Oct 08 01:27:03 PM PDT 23	Oct 08 01:27:59 PM PDT 23	144869905585 ps
T89	/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.2818749565	Oct 08 01:36:47 PM PDT 23	Oct 08 01:37:56 PM PDT 23	24833824726 ps
T199	/workspace/coverage/default/12.sysrst_ctrl_alert_test.3143750572	Oct 08 01:20:46 PM PDT 23	Oct 08 01:20:48 PM PDT 23	2054250199 ps