4e80560e2
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | sysrst_ctrl_smoke | 6.610s | 2.114ms | 50 | 50 | 100.00 |
V1 | input_output_inverted | sysrst_ctrl_in_out_inverted | 8.540s | 2.442ms | 50 | 50 | 100.00 |
V1 | combo_detect_ec_rst | sysrst_ctrl_combo_detect_ec_rst | 7.050s | 2.424ms | 5 | 5 | 100.00 |
V1 | combo_detect_ec_rst_with_pre_cond | sysrst_ctrl_combo_detect_ec_rst_with_pre_cond | 7.170s | 2.522ms | 4 | 5 | 80.00 |
V1 | csr_hw_reset | sysrst_ctrl_csr_hw_reset | 11.530s | 4.012ms | 5 | 5 | 100.00 |
V1 | csr_rw | sysrst_ctrl_csr_rw | 6.580s | 2.053ms | 20 | 20 | 100.00 |
V1 | csr_bit_bash | sysrst_ctrl_csr_bit_bash | 3.374m | 74.974ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | sysrst_ctrl_csr_aliasing | 7.900s | 3.230ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | sysrst_ctrl_csr_mem_rw_with_rand_reset | 6.370s | 2.111ms | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | sysrst_ctrl_csr_rw | 6.580s | 2.053ms | 20 | 20 | 100.00 |
sysrst_ctrl_csr_aliasing | 7.900s | 3.230ms | 5 | 5 | 100.00 | ||
V1 | TOTAL | 164 | 165 | 99.39 | |||
V2 | combo_detect | sysrst_ctrl_combo_detect | 7.854m | 185.237ms | 50 | 50 | 100.00 |
V2 | combo_detect_with_pre_cond | sysrst_ctrl_combo_detect_with_pre_cond | 7.843m | 180.039ms | 94 | 100 | 94.00 |
V2 | auto_block_key_outputs | sysrst_ctrl_auto_blk_key_output | 11.652m | 293.940ms | 50 | 50 | 100.00 |
V2 | keyboard_input_triggered_interrupt | sysrst_ctrl_edge_detect | 17.580s | 810.058ms | 50 | 50 | 100.00 |
V2 | pin_output_keyboard_inversion_control | sysrst_ctrl_pin_override_test | 7.810s | 2.508ms | 50 | 50 | 100.00 |
V2 | pin_input_value_accessibility | sysrst_ctrl_pin_access_test | 6.760s | 2.174ms | 50 | 50 | 100.00 |
V2 | ec_power_on_reset | sysrst_ctrl_ec_pwr_on_rst | 13.050s | 4.753ms | 49 | 50 | 98.00 |
V2 | flash_write_protect_output | sysrst_ctrl_flash_wr_prot_out | 8.000s | 2.610ms | 50 | 50 | 100.00 |
V2 | ultra_low_power_test | sysrst_ctrl_ultra_low_pwr | 3.229m | 1.694s | 46 | 50 | 92.00 |
V2 | sysrst_ctrl_feature_disable | sysrst_ctrl_feature_disable | 21.050s | 31.224ms | 2 | 2 | 100.00 |
V2 | stress_all | sysrst_ctrl_stress_all | 44.886m | 1.379s | 48 | 50 | 96.00 |
V2 | alert_test | sysrst_ctrl_alert_test | 6.040s | 2.013ms | 50 | 50 | 100.00 |
V2 | intr_test | sysrst_ctrl_intr_test | 6.310s | 2.012ms | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | sysrst_ctrl_tl_errors | 8.430s | 2.125ms | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | sysrst_ctrl_tl_errors | 8.430s | 2.125ms | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | sysrst_ctrl_csr_hw_reset | 11.530s | 4.012ms | 5 | 5 | 100.00 |
sysrst_ctrl_csr_rw | 6.580s | 2.053ms | 20 | 20 | 100.00 | ||
sysrst_ctrl_csr_aliasing | 7.900s | 3.230ms | 5 | 5 | 100.00 | ||
sysrst_ctrl_same_csr_outstanding | 41.020s | 10.359ms | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | sysrst_ctrl_csr_hw_reset | 11.530s | 4.012ms | 5 | 5 | 100.00 |
sysrst_ctrl_csr_rw | 6.580s | 2.053ms | 20 | 20 | 100.00 | ||
sysrst_ctrl_csr_aliasing | 7.900s | 3.230ms | 5 | 5 | 100.00 | ||
sysrst_ctrl_same_csr_outstanding | 41.020s | 10.359ms | 20 | 20 | 100.00 | ||
V2 | TOTAL | 679 | 692 | 98.12 | |||
V2S | tl_intg_err | sysrst_ctrl_sec_cm | 1.946m | 42.010ms | 5 | 5 | 100.00 |
sysrst_ctrl_tl_intg_err | 1.788m | 42.447ms | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | sysrst_ctrl_tl_intg_err | 1.788m | 42.447ms | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | stress_all_with_rand_reset | sysrst_ctrl_stress_all_with_rand_reset | 6.573m | 1.885s | 48 | 50 | 96.00 |
V3 | TOTAL | 48 | 50 | 96.00 | |||
TOTAL | 916 | 932 | 98.28 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 9 | 9 | 8 | 88.89 |
V2 | 15 | 15 | 11 | 73.33 |
V2S | 2 | 2 | 2 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.75 | 99.31 | 96.35 | 100.00 | 96.15 | 98.68 | 99.44 | 94.29 |
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
has 6 failures:
16.sysrst_ctrl_ultra_low_pwr.1219963857
Line 513, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 2551287494 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_ERROR @ 3003787494 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:214) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 3003787494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.sysrst_ctrl_ultra_low_pwr.365996946
Line 513, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 2238844069 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_INFO @ 2466344069 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
UVM_INFO @ 6181344069 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
UVM_INFO @ 8546344069 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:234) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disble Z3 wakeup check
UVM_INFO @ 8546463015 ps: (sysrst_ctrl_base_vseq.sv:119) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Unhandled interrupt detected
... and 2 more failures.
21.sysrst_ctrl_stress_all.1649417157
Line 514, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_stress_all/latest/run.log
UVM_ERROR @ 4489018370 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_INFO @ 4496518370 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
UVM_INFO @ 5691518370 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:234) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disble Z3 wakeup check
UVM_INFO @ 5691580263 ps: (sysrst_ctrl_base_vseq.sv:119) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Unhandled interrupt detected
UVM_INFO @ 5698590357 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_combo_detect_vseq
45.sysrst_ctrl_stress_all.2511814288
Line 518, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_stress_all/latest/run.log
UVM_ERROR @ 9417128867 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_INFO @ 9444628867 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
UVM_INFO @ 12749628867 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:234) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disble Z3 wakeup check
UVM_INFO @ 12749777379 ps: (sysrst_ctrl_base_vseq.sv:119) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Unhandled interrupt detected
UVM_INFO @ 12818722335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*])
has 3 failures:
53.sysrst_ctrl_combo_detect_with_pre_cond.2196498469
Line 560, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/53.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 51797937468 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 51797937468 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 51797937468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
62.sysrst_ctrl_combo_detect_with_pre_cond.2883260850
Line 521, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/62.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 13738944196 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 24010727226 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x27
UVM_INFO @ 24010810560 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x27
UVM_INFO @ 25298944196 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0
UVM_INFO @ 25313944196 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= 1e
... and 1 more failures.
UVM_FATAL (sysrst_ctrl_base_vseq.sv:67) [sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == *
has 2 failures:
Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.
10.sysrst_ctrl_stress_all_with_rand_reset.2917263029
Line 608, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 64927773602 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
UVM_INFO @ 64927773602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sysrst_ctrl_ec_pwr_on_rst has 1 failures.
12.sysrst_ctrl_ec_pwr_on_rst.2944866667
Line 513, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_ec_pwr_on_rst/latest/run.log
UVM_FATAL @ 2272499914 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
UVM_INFO @ 2272499914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*])
has 2 failures:
63.sysrst_ctrl_combo_detect_with_pre_cond.3795004051
Line 556, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/63.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 85781811025 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 85781811025 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 85781811025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
89.sysrst_ctrl_combo_detect_with_pre_cond.3553501292
Line 531, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/89.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 37795734229 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 37795734229 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 37795734229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: *
has 1 failures:
4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2298377791
Line 515, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest/run.log
UVM_ERROR @ 2286567632 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: 0x0
UVM_INFO @ 2501907632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == * (* [*] vs * [*])
has 1 failures:
41.sysrst_ctrl_combo_detect_with_pre_cond.839006060
Line 532, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 22087389398 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 22327484855 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 4 [0x4])
UVM_INFO @ 22327484855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_vseq.sv:300) [sysrst_ctrl_combo_detect_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*])
has 1 failures:
45.sysrst_ctrl_stress_all_with_rand_reset.1475664256
Line 601, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1503494068706 ps: (sysrst_ctrl_combo_detect_vseq.sv:300) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1503523589922 ps: (cip_base_vseq.sv:719) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
Stress w/ reset is done for run 3/10
UVM_INFO @ 1503565969711 ps: (cip_base_vseq.sv:680) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 4/10
UVM_INFO @ 1503565969711 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running run_tl_errors_vseq 1/826